ifdefed ev5 vs. ev6 differences so Tlaser can work in the linux tree
arch/alpha/alpha_memory.cc: arch/alpha/ev5.hh: Ifdefed TLASER code arch/alpha/vtophys.cc: added back some code andrew removed and couldn't remember why. --HG-- extra : convert_revision : f00d255f7a8a7bdb6e74f061dd014188e3b39e73
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3 changed files with 73 additions and 20 deletions
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@ -101,18 +101,34 @@ AlphaTLB::checkCacheability(MemReqPtr &req)
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* to catch a weird case where both are used, which shouldn't happen.
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* to catch a weird case where both are used, which shouldn't happen.
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*/
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*/
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#ifdef ALPHA_TLASER
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if (req->paddr & PA_UNCACHED_BIT_39) {
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#else
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if (req->paddr & PA_UNCACHED_BIT_43) {
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if (req->paddr & PA_UNCACHED_BIT_43) {
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#endif
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// IPR memory space not implemented
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// IPR memory space not implemented
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if (PA_IPR_SPACE(req->paddr))
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if (PA_IPR_SPACE(req->paddr)) {
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if (!req->xc->misspeculating())
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if (!req->xc->misspeculating()) {
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switch (req->paddr) {
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case ULL(0xFFFFF00188):
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req->data = 0;
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break;
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default:
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panic("IPR memory space not implemented! PA=%x\n",
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panic("IPR memory space not implemented! PA=%x\n",
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req->paddr);
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req->paddr);
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}
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}
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} else {
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// mark request as uncacheable
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// mark request as uncacheable
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req->flags |= UNCACHEABLE;
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req->flags |= UNCACHEABLE;
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#ifndef ALPHA_TLASER
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// Clear bits 42:35 of the physical address (10-2 in Tsunami manual)
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// Clear bits 42:35 of the physical address (10-2 in Tsunami manual)
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req->paddr &= PA_UNCACHED_MASK;
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req->paddr &= PA_UNCACHED_MASK;
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#endif
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}
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}
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}
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}
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}
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@ -301,7 +317,13 @@ AlphaITB::translate(MemReqPtr &req) const
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// VA<42:41> == 2, VA<39:13> maps directly to PA<39:13> for EV5
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// VA<42:41> == 2, VA<39:13> maps directly to PA<39:13> for EV5
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// VA<47:41> == 0x7e, VA<40:13> maps directly to PA<40:13> for EV6
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// VA<47:41> == 0x7e, VA<40:13> maps directly to PA<40:13> for EV6
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#ifdef ALPHA_TLASER
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if ((MCSR_SP(ipr[AlphaISA::IPR_MCSR]) & 2) &&
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VA_SPACE_EV5(req->vaddr) == 2) {
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#else
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if (VA_SPACE_EV6(req->vaddr) == 0x7e) {
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if (VA_SPACE_EV6(req->vaddr) == 0x7e) {
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#endif
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// only valid in kernel mode
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// only valid in kernel mode
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if (ICM_CM(ipr[AlphaISA::IPR_ICM]) != AlphaISA::mode_kernel) {
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if (ICM_CM(ipr[AlphaISA::IPR_ICM]) != AlphaISA::mode_kernel) {
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@ -312,11 +334,13 @@ AlphaITB::translate(MemReqPtr &req) const
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req->paddr = req->vaddr & PA_IMPL_MASK;
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req->paddr = req->vaddr & PA_IMPL_MASK;
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#ifndef ALPHA_TLASER
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// sign extend the physical address properly
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// sign extend the physical address properly
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if (req->paddr & PA_UNCACHED_BIT_40)
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if (req->paddr & PA_UNCACHED_BIT_40)
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req->paddr |= ULL(0xf0000000000);
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req->paddr |= ULL(0xf0000000000);
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else
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else
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req->paddr &= ULL(0xffffffffff);
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req->paddr &= ULL(0xffffffffff);
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#endif
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} else {
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} else {
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// not a physical address: need to look up pte
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// not a physical address: need to look up pte
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@ -486,7 +510,12 @@ AlphaDTB::translate(MemReqPtr &req, bool write) const
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}
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}
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// Check for "superpage" mapping
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// Check for "superpage" mapping
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#ifdef ALPHA_TLASER
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if ((MCSR_SP(ipr[AlphaISA::IPR_MCSR]) & 2) &&
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VA_SPACE_EV5(req->vaddr) == 2) {
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#else
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if (VA_SPACE_EV6(req->vaddr) == 0x7e) {
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if (VA_SPACE_EV6(req->vaddr) == 0x7e) {
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#endif
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// only valid in kernel mode
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// only valid in kernel mode
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if (DTB_CM_CM(ipr[AlphaISA::IPR_DTB_CM]) !=
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if (DTB_CM_CM(ipr[AlphaISA::IPR_DTB_CM]) !=
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@ -498,11 +527,13 @@ AlphaDTB::translate(MemReqPtr &req, bool write) const
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req->paddr = req->vaddr & PA_IMPL_MASK;
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req->paddr = req->vaddr & PA_IMPL_MASK;
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#ifndef ALPHA_TLASER
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// sign extend the physical address properly
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// sign extend the physical address properly
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if (req->paddr & PA_UNCACHED_BIT_40)
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if (req->paddr & PA_UNCACHED_BIT_40)
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req->paddr |= ULL(0xf0000000000);
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req->paddr |= ULL(0xf0000000000);
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else
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else
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req->paddr &= ULL(0xffffffffff);
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req->paddr &= ULL(0xffffffffff);
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#endif
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} else {
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} else {
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if (write)
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if (write)
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@ -32,8 +32,15 @@
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#define ALT_MODE_AM(X) (((X) >> 3) & 0x3)
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#define ALT_MODE_AM(X) (((X) >> 3) & 0x3)
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#define DTB_CM_CM(X) (((X) >> 3) & 0x3)
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#define DTB_CM_CM(X) (((X) >> 3) & 0x3)
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#ifdef ALPHA_TLASER
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#define DTB_ASN_ASN(X) (((X) >> 57) & 0x7f)
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#define DTB_PTE_PPN(X) (((X) >> 32) & 0x07ffffff)
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#else
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#define DTB_ASN_ASN(X) (((X) >> 57) & 0xff)
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#define DTB_ASN_ASN(X) (((X) >> 57) & 0xff)
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#define DTB_PTE_PPN(X) (((X) >> 32) & 0x07fffffff)
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#define DTB_PTE_PPN(X) (((X) >> 32) & 0x07fffffff)
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#endif
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#define DTB_PTE_XRE(X) (((X) >> 8) & 0xf)
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#define DTB_PTE_XRE(X) (((X) >> 8) & 0xf)
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#define DTB_PTE_XWE(X) (((X) >> 12) & 0xf)
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#define DTB_PTE_XWE(X) (((X) >> 12) & 0xf)
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#define DTB_PTE_FONR(X) (((X) >> 1) & 0x1)
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#define DTB_PTE_FONR(X) (((X) >> 1) & 0x1)
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@ -42,8 +49,15 @@
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#define DTB_PTE_ASMA(X) (((X) >> 4) & 0x1)
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#define DTB_PTE_ASMA(X) (((X) >> 4) & 0x1)
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#define ICM_CM(X) (((X) >> 3) & 0x3)
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#define ICM_CM(X) (((X) >> 3) & 0x3)
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#ifdef ALPHA_TLASER
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#define ITB_ASN_ASN(X) (((X) >> 4) & 0x7f)
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#define ITB_PTE_PPN(X) (((X) >> 32) & 0x07ffffff)
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#else
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#define ITB_ASN_ASN(X) (((X) >> 4) & 0xff)
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#define ITB_ASN_ASN(X) (((X) >> 4) & 0xff)
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#define ITB_PTE_PPN(X) (((X) >> 32) & 0x07fffffff)
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#define ITB_PTE_PPN(X) (((X) >> 32) & 0x07fffffff)
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#endif
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#define ITB_PTE_XRE(X) (((X) >> 8) & 0xf)
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#define ITB_PTE_XRE(X) (((X) >> 8) & 0xf)
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#define ITB_PTE_FONR(X) (((X) >> 1) & 0x1)
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#define ITB_PTE_FONR(X) (((X) >> 1) & 0x1)
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#define ITB_PTE_FONW(X) (((X) >> 2) & 0x1)
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#define ITB_PTE_FONW(X) (((X) >> 2) & 0x1)
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@ -58,12 +72,17 @@
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#define VA_SPACE_EV6(X) (((X) >> 41) & 0x7f)
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#define VA_SPACE_EV6(X) (((X) >> 41) & 0x7f)
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#define VA_POFS(X) ((X) & 0x1fff)
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#define VA_POFS(X) ((X) & 0x1fff)
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#define PA_IMPL_MASK ULL(0xfffffffffff) // for Tsunami
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#define PA_UNCACHED_BIT_39 ULL(0x8000000000)
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#define PA_UNCACHED_BIT_39 ULL(0x8000000000)
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#define PA_UNCACHED_BIT_40 ULL(0x10000000000)
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#define PA_UNCACHED_BIT_40 ULL(0x10000000000)
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#define PA_UNCACHED_BIT_43 ULL(0x80000000000)
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#define PA_UNCACHED_BIT_43 ULL(0x80000000000)
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#define PA_UNCACHED_MASK ULL(0x807ffffffff) // Clear PA<42:35>
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#define PA_UNCACHED_MASK ULL(0x807ffffffff) // Clear PA<42:35>
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#ifdef ALPHA_TLASER
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#define PA_IPR_SPACE(X) ((X) >= ULL(0xFFFFF00000))
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#define PA_IMPL_MASK ULL(0xffffffffff)
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#else
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#define PA_IPR_SPACE(X) ((X) >= ULL(0xFFFFFF00000))
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#define PA_IPR_SPACE(X) ((X) >= ULL(0xFFFFFF00000))
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#define PA_IMPL_MASK ULL(0xfffffffffff) // for Tsunami
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#endif
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#define PA_PFN2PA(X) ((X) << 13)
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#define PA_PFN2PA(X) ((X) << 13)
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@ -96,20 +96,23 @@ vtophys(ExecContext *xc, Addr vaddr)
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{
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{
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Addr ptbr = xc->regs.ipr[AlphaISA::IPR_PALtemp20];
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Addr ptbr = xc->regs.ipr[AlphaISA::IPR_PALtemp20];
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Addr paddr = 0;
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Addr paddr = 0;
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// if (PC_PAL(vaddr)) {
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//@todo Andrew couldn't remember why he commented some of this code
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// paddr = vaddr & ~ULL(1);
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//so I put it back in. Perhaps something to do with gdb debugging?
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// } else {
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if (PC_PAL(vaddr)) {
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if (vaddr >= ALPHA_K0SEG_BASE && vaddr <= ALPHA_K0SEG_END) {
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paddr = vaddr & ~ULL(1);
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paddr = ALPHA_K0SEG_TO_PHYS(vaddr);
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} else if (!ptbr) {
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} else if (!ptbr) {
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paddr = vaddr;
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paddr = vaddr;
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} else {
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if (vaddr >= ALPHA_K0SEG_BASE && vaddr <= ALPHA_K0SEG_END) {
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paddr = ALPHA_K0SEG_TO_PHYS(vaddr);
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} else {
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} else {
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Addr pte = kernel_pte_lookup(xc->physmem, ptbr, vaddr);
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Addr pte = kernel_pte_lookup(xc->physmem, ptbr, vaddr);
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uint64_t entry = xc->physmem->phys_read_qword(pte);
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uint64_t entry = xc->physmem->phys_read_qword(pte);
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if (pte && entry_valid(entry))
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if (pte && entry_valid(entry))
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paddr = PMAP_PTE_PA(entry) | (vaddr & PGOFSET);
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paddr = PMAP_PTE_PA(entry) | (vaddr & PGOFSET);
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}
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}
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// }
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}
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DPRINTF(VtoPhys, "vtophys(%#x) -> %#x\n", vaddr, paddr);
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DPRINTF(VtoPhys, "vtophys(%#x) -> %#x\n", vaddr, paddr);
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