SE/FS: Build the Interrupt objects in SE mode.

src/arch/alpha/SConscript

@@ -34,6 +34,7 @@ Import('*')
 if env['TARGET_ISA'] == 'alpha':
     Source('ev5.cc')
     Source('faults.cc')
+    Source('interrupts.cc')
     Source('ipr.cc')
     Source('isa.cc')
     Source('pagetable.cc')
@@ -42,14 +43,13 @@ if env['TARGET_ISA'] == 'alpha':
     Source('tlb.cc')
     Source('utility.cc')
 
+    SimObject('AlphaInterrupts.py')
     SimObject('AlphaTLB.py')
 
     if env['FULL_SYSTEM']:
-        SimObject('AlphaInterrupts.py')
         SimObject('AlphaSystem.py')
 
         Source('idle_event.cc')
-        Source('interrupts.cc')
         Source('kernel_stats.cc')
         Source('osfpal.cc')
         Source('stacktrace.cc')

src/arch/arm/SConscript

@@ -54,6 +54,7 @@ if env['TARGET_ISA'] == 'arm':
     Source('insts/pred_inst.cc')
     Source('insts/static_inst.cc')
     Source('insts/vfp.cc')
+    Source('interrupts.cc')
     Source('isa.cc')
     Source('miscregs.cc')
     Source('predecoder.cc')
@@ -62,6 +63,7 @@ if env['TARGET_ISA'] == 'arm':
     Source('utility.cc')
     Source('remote_gdb.cc')
 
+    SimObject('ArmInterrupts.py')
     SimObject('ArmNativeTrace.py')
     SimObject('ArmTLB.py')
 
@@ -70,14 +72,12 @@ if env['TARGET_ISA'] == 'arm':
     DebugFlag('Faults', "Trace Exceptions, interrupts, svc/swi")
     DebugFlag('Predecoder', "Instructions returned by the predecoder")
     if env['FULL_SYSTEM']:
-        Source('interrupts.cc')
         Source('stacktrace.cc')
         Source('system.cc')
         Source('vtophys.cc')
         Source('linux/system.cc')
         Source('table_walker.cc')
         
-        SimObject('ArmInterrupts.py')
         SimObject('ArmSystem.py')
     else:
         Source('process.cc')

src/arch/mips/SConscript

@@ -34,6 +34,7 @@ Import('*')
 
 if env['TARGET_ISA'] == 'mips':
     Source('faults.cc')
+    Source('interrupts.cc')
     Source('isa.cc')
     Source('tlb.cc')
     Source('pagetable.cc')
@@ -41,19 +42,18 @@ if env['TARGET_ISA'] == 'mips':
     Source('dsp.cc')
     Source('remote_gdb.cc')
 
-    SimObject('MipsTLB.py')
+    SimObject('MipsInterrupts.py')
     DebugFlag('MipsPRA')
+    SimObject('MipsTLB.py')
 
     if env['FULL_SYSTEM']:
         SimObject('MipsSystem.py')
-        SimObject('MipsInterrupts.py')
         Source('idle_event.cc')
         Source('mips_core_specific.cc')
         Source('vtophys.cc')
         Source('system.cc')
         Source('stacktrace.cc')
         Source('linux/system.cc')
-        Source('interrupts.cc')
         Source('bare_iron/system.cc')
     else:
         Source('process.cc')

src/arch/mips/interrupts.cc

@@ -36,6 +36,7 @@
 #include "arch/mips/pra_constants.hh"
 #include "base/trace.hh"
 #include "cpu/thread_context.hh"
+#include "debug/Interrupt.hh"
 
 namespace MipsISA
 {

src/arch/power/PowerInterrupts.py

@@ -0,0 +1,33 @@
+# Copyright (c) 2011 Google
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Gabe Black
+
+from m5.SimObject import SimObject
+
+class PowerInterrupts(SimObject):
+    type = 'PowerInterrupts'
+    cxx_class = 'PowerISA::Interrupts'

src/arch/power/SConscript

@@ -40,11 +40,14 @@ if env['TARGET_ISA'] == 'power':
     Source('insts/floating.cc')
     Source('insts/condition.cc')
     Source('insts/static_inst.cc')
+    Source('interrupts.cc')
     Source('pagetable.cc')
     Source('tlb.cc')
     Source('utility.cc')
 
+    SimObject('PowerInterrupts.py')
     SimObject('PowerTLB.py')
+
     DebugFlag('Power')
 
     if not env['FULL_SYSTEM']:

src/arch/power/interrupts.cc

@@ -0,0 +1,37 @@
+/*
+ * Copyright (c) 2011 Google
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Gabe Black
+ */
+
+#include "arch/power/interrupts.hh"
+
+PowerISA::Interrupts *
+PowerInterruptsParams::create()
+{
+    return new PowerISA::Interrupts(this);
+}

src/arch/power/interrupts.hh

@@ -0,0 +1,105 @@
+/*
+ * Copyright (c) 2011 Google
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Gabe Black
+ */
+
+#ifndef __ARCH_POWER_INTERRUPT_HH__
+#define __ARCH_POWER_INTERRUPT_HH__
+
+#include "base/misc.hh"
+#include "params/PowerInterrupts.hh"
+#include "sim/sim_object.hh"
+
+class ThreadContext;
+
+namespace PowerISA {
+
+class Interrupts : public SimObject
+{
+  private:
+    BaseCPU * cpu;
+
+  public:
+    typedef PowerInterruptsParams Params;
+
+    const Params *
+    params() const
+    {
+        return dynamic_cast<const Params *>(_params);
+    }
+
+    Interrupts(Params * p) : SimObject(p), cpu(NULL)
+    {}
+
+    void
+    setCPU(BaseCPU * _cpu)
+    {
+        cpu = _cpu;
+    }
+
+    void
+    post(int int_num, int index)
+    {
+        panic("Interrupts::post not implemented.\n");
+    }
+
+    void
+    clear(int int_num, int index)
+    {
+        panic("Interrupts::clear not implemented.\n");
+    }
+
+    void
+    clearAll()
+    {
+        panic("Interrupts::clearAll not implemented.\n");
+    }
+
+    bool
+    checkInterrupts(ThreadContext *tc) const
+    {
+        panic("Interrupts::checkInterrupts not implemented.\n");
+    }
+
+    Fault
+    getInterrupt(ThreadContext *tc)
+    {
+        panic("Interrupts::getInterrupt not implemented.\n");
+    }
+
+    void
+    updateIntrInfo(ThreadContext *tc)
+    {
+        panic("Interrupts::updateIntrInfo not implemented.\n");
+    }
+};
+
+} // namespace PowerISA
+
+#endif // __ARCH_POWER_INTERRUPT_HH__
+

src/arch/sparc/SConscript

@@ -34,6 +34,7 @@ Import('*')
 if env['TARGET_ISA'] == 'sparc':
     Source('asi.cc')
     Source('faults.cc')
+    Source('interrupts.cc')
     Source('isa.cc')
     Source('nativetrace.cc')
     Source('pagetable.cc')
@@ -41,17 +42,16 @@ if env['TARGET_ISA'] == 'sparc':
     Source('tlb.cc')
     Source('utility.cc')
 
+    SimObject('SparcInterrupts.py')
     SimObject('SparcNativeTrace.py')
-
     SimObject('SparcTLB.py')
+
     DebugFlag('Sparc', "Generic SPARC ISA stuff")
     DebugFlag('RegisterWindows', "Register window manipulation")
 
     if env['FULL_SYSTEM']:
         SimObject('SparcSystem.py')
-        SimObject('SparcInterrupts.py')
 
-        Source('interrupts.cc')
         Source('system.cc')
         Source('ua2005.cc')
         Source('vtophys.cc')

src/arch/x86/SConscript

@@ -53,6 +53,7 @@ if env['TARGET_ISA'] == 'x86':
     Source('insts/microop.cc')
     Source('insts/microregop.cc')
     Source('insts/static_inst.cc')
+    Source('interrupts.cc')
     Source('isa.cc')
     Source('nativetrace.cc')
     Source('pagetable.cc')
@@ -63,23 +64,22 @@ if env['TARGET_ISA'] == 'x86':
     Source('types.cc')
     Source('utility.cc')
 
+    SimObject('X86LocalApic.py')
     SimObject('X86NativeTrace.py')
     SimObject('X86TLB.py')
 
     DebugFlag('Faults', "Trace all faults/exceptions/traps")
+    DebugFlag('LocalApic', "Local APIC debugging")
     DebugFlag('Predecoder', "Predecoder debug output")
     DebugFlag('X86', "Generic X86 ISA debugging")
 
     if env['FULL_SYSTEM']:
-        DebugFlag('LocalApic', "Local APIC debugging")
         DebugFlag('PageTableWalker', \
                   "Page table walker state machine debugging")
 
-        SimObject('X86LocalApic.py')
         SimObject('X86System.py')
 
         # Full-system sources
-        Source('interrupts.cc')
         Source('linux/system.cc')
         Source('pagetable_walker.cc')
         Source('system.cc')

src/arch/x86/interrupts.cc

@@ -273,8 +273,10 @@ X86ISA::Interrupts::requestInterrupt(uint8_t vector,
             pendingUnmaskableInt = pendingStartup = true;
             startupVector = vector;
         }
-    } 
+    }
+#if FULL_SYSTEM //XXX CPU has no wakeup method in SE mode.
     cpu->wakeup();
+#endif
 }
 
 

src/cpu/BaseCPU.py

@@ -43,28 +43,22 @@ default_tracer = ExeTracer()
 
 if buildEnv['TARGET_ISA'] == 'alpha':
     from AlphaTLB import AlphaDTB, AlphaITB
-    if buildEnv['FULL_SYSTEM']:
+    from AlphaInterrupts import AlphaInterrupts
-        from AlphaInterrupts import AlphaInterrupts
 elif buildEnv['TARGET_ISA'] == 'sparc':
     from SparcTLB import SparcTLB
-    if buildEnv['FULL_SYSTEM']:
+    from SparcInterrupts import SparcInterrupts
-        from SparcInterrupts import SparcInterrupts
 elif buildEnv['TARGET_ISA'] == 'x86':
     from X86TLB import X86TLB
-    if buildEnv['FULL_SYSTEM']:
+    from X86LocalApic import X86LocalApic
-        from X86LocalApic import X86LocalApic
 elif buildEnv['TARGET_ISA'] == 'mips':
     from MipsTLB import MipsTLB
-    if buildEnv['FULL_SYSTEM']:
+    from MipsInterrupts import MipsInterrupts
-        from MipsInterrupts import MipsInterrupts
 elif buildEnv['TARGET_ISA'] == 'arm':
     from ArmTLB import ArmTLB
-    if buildEnv['FULL_SYSTEM']:
+    from ArmInterrupts import ArmInterrupts
-        from ArmInterrupts import ArmInterrupts
 elif buildEnv['TARGET_ISA'] == 'power':
     from PowerTLB import PowerTLB
-    if buildEnv['FULL_SYSTEM']:
+    from PowerInterrupts import PowerInterrupts
-        from PowerInterrupts import PowerInterrupts
 
 class BaseCPU(MemObject):
     type = 'BaseCPU'
@@ -93,41 +87,34 @@ class BaseCPU(MemObject):
     if buildEnv['TARGET_ISA'] == 'sparc':
         dtb = Param.SparcTLB(SparcTLB(), "Data TLB")
         itb = Param.SparcTLB(SparcTLB(), "Instruction TLB")
-        if buildEnv['FULL_SYSTEM']:
+        interrupts = Param.SparcInterrupts(
-            interrupts = Param.SparcInterrupts(
                 SparcInterrupts(), "Interrupt Controller")
     elif buildEnv['TARGET_ISA'] == 'alpha':
         dtb = Param.AlphaTLB(AlphaDTB(), "Data TLB")
         itb = Param.AlphaTLB(AlphaITB(), "Instruction TLB")
-        if buildEnv['FULL_SYSTEM']:
+        interrupts = Param.AlphaInterrupts(
-            interrupts = Param.AlphaInterrupts(
                 AlphaInterrupts(), "Interrupt Controller")
     elif buildEnv['TARGET_ISA'] == 'x86':
         dtb = Param.X86TLB(X86TLB(), "Data TLB")
         itb = Param.X86TLB(X86TLB(), "Instruction TLB")
-        if buildEnv['FULL_SYSTEM']:
+        _localApic = X86LocalApic(pio_addr=0x2000000000000000)
-            _localApic = X86LocalApic(pio_addr=0x2000000000000000)
+        interrupts = Param.X86LocalApic(_localApic, "Interrupt Controller")
-            interrupts = \
-                Param.X86LocalApic(_localApic, "Interrupt Controller")
     elif buildEnv['TARGET_ISA'] == 'mips':
         dtb = Param.MipsTLB(MipsTLB(), "Data TLB")
         itb = Param.MipsTLB(MipsTLB(), "Instruction TLB")
-        if buildEnv['FULL_SYSTEM']:
+        interrupts = Param.MipsInterrupts(
-            interrupts = Param.MipsInterrupts(
+                MipsInterrupts(), "Interrupt Controller")
-                    MipsInterrupts(), "Interrupt Controller")
     elif buildEnv['TARGET_ISA'] == 'arm':
         dtb = Param.ArmTLB(ArmTLB(), "Data TLB")
         itb = Param.ArmTLB(ArmTLB(), "Instruction TLB")
-        if buildEnv['FULL_SYSTEM']:
+        interrupts = Param.ArmInterrupts(
-            interrupts = Param.ArmInterrupts(
+                ArmInterrupts(), "Interrupt Controller")
-                    ArmInterrupts(), "Interrupt Controller")
     elif buildEnv['TARGET_ISA'] == 'power':
         UnifiedTLB = Param.Bool(True, "Is this a Unified TLB?")
         dtb = Param.PowerTLB(PowerTLB(), "Data TLB")
         itb = Param.PowerTLB(PowerTLB(), "Instruction TLB")
-        if buildEnv['FULL_SYSTEM']:
+        interrupts = Param.PowerInterrupts(
-            interrupts = Param.PowerInterrupts(
+                PowerInterrupts(), "Interrupt Controller")
-                    PowerInterrupts(), "Interrupt Controller")
     else:
         print "Don't know what TLB to use for ISA %s" % \
             buildEnv['TARGET_ISA']
@@ -157,7 +144,7 @@ class BaseCPU(MemObject):
         _cached_ports = ["itb.walker.port", "dtb.walker.port"]
 
     _uncached_ports = []
-    if buildEnv['TARGET_ISA'] == 'x86' and buildEnv['FULL_SYSTEM']:
+    if buildEnv['TARGET_ISA'] == 'x86':
         _uncached_ports = ["interrupts.pio", "interrupts.int_port"]
 
     def connectCachedPorts(self, bus):

src/cpu/base.cc

@@ -100,18 +100,11 @@ CPUProgressEvent::description() const
     return "CPU Progress";
 }
 
-#if FULL_SYSTEM
 BaseCPU::BaseCPU(Params *p)
     : MemObject(p), clock(p->clock), instCnt(0), _cpuId(p->cpu_id),
       interrupts(p->interrupts),
       numThreads(p->numThreads), system(p->system),
       phase(p->phase)
-#else
-BaseCPU::BaseCPU(Params *p)
-    : MemObject(p), clock(p->clock), _cpuId(p->cpu_id),
-      numThreads(p->numThreads), system(p->system),
-      phase(p->phase)
-#endif
 {
 //    currentTick = curTick();
 
@@ -202,9 +195,9 @@ BaseCPU::BaseCPU(Params *p)
             schedule(event, p->function_trace_start);
         }
     }
-#if FULL_SYSTEM
     interrupts->setCPU(this);
 
+#if FULL_SYSTEM
     profileEvent = NULL;
     if (params()->profile)
         profileEvent = new ProfileEvent(this, params()->profile);
@@ -395,10 +388,10 @@ BaseCPU::takeOverFrom(BaseCPU *oldCPU, Port *ic, Port *dc)
         }
     }
 
-#if FULL_SYSTEM
     interrupts = oldCPU->interrupts;
     interrupts->setCPU(this);
 
+#if FULL_SYSTEM
     for (ThreadID i = 0; i < size; ++i)
         threadContexts[i]->profileClear();
 
@@ -440,6 +433,8 @@ BaseCPU::ProfileEvent::process()
     cpu->schedule(this, curTick() + interval);
 }
 
+#endif // FULL_SYSTEM
+
 void
 BaseCPU::serialize(std::ostream &os)
 {
@@ -454,8 +449,6 @@ BaseCPU::unserialize(Checkpoint *cp, const std::string &section)
     interrupts->unserialize(cp, section);
 }
 
-#endif // FULL_SYSTEM
-
 void
 BaseCPU::traceFunctionsInternal(Addr pc)
 {

src/cpu/base.hh

@@ -36,6 +36,7 @@
 
 #include <vector>
 
+#include "arch/interrupts.hh"
 #include "arch/isa_traits.hh"
 #include "arch/microcode_rom.hh"
 #include "base/statistics.hh"
@@ -45,10 +46,6 @@
 #include "sim/eventq.hh"
 #include "sim/insttracer.hh"
 
-#if FULL_SYSTEM
-#include "arch/interrupts.hh"
-#endif
-
 class BaseCPUParams;
 class BranchPred;
 class CheckerCPU;
@@ -125,7 +122,6 @@ class BaseCPU : public MemObject
 
     TheISA::MicrocodeRom microcodeRom;
 
-#if FULL_SYSTEM
   protected:
     TheISA::Interrupts *interrupts;
 
@@ -136,13 +132,17 @@ class BaseCPU : public MemObject
         return interrupts;
     }
 
+#if FULL_SYSTEM
     virtual void wakeup() = 0;
+#endif
 
     void
     postInterrupt(int int_num, int index)
     {
         interrupts->post(int_num, index);
+#if FULL_SYSTEM
         wakeup();
+#endif
     }
 
     void
@@ -174,7 +174,6 @@ class BaseCPU : public MemObject
         void process();
     };
     ProfileEvent *profileEvent;
-#endif
 
   protected:
     std::vector<ThreadContext *> threadContexts;
@@ -257,7 +256,6 @@ class BaseCPU : public MemObject
 
     Tick phase;
 
-#if FULL_SYSTEM
     /**
      * Serialize this object to the given output stream.
      * @param os The stream to serialize to.
@@ -271,8 +269,6 @@ class BaseCPU : public MemObject
      */
     virtual void unserialize(Checkpoint *cp, const std::string &section);
 
-#endif
-
     /**
      * Return pointer to CPU's branch predictor (NULL if none).
      * @return Branch predictor pointer.