tests: Create base classes to encapsulate common test configurations
Most of the test cases currently contain a large amount of duplicated
boiler plate code. This changeset introduces a set of classes that
encapsulates most of the functionality when setting up a test
configuration.
The following base classes are introduced:
* BaseSystem - Basic system configuration that can be used for both
SE and FS simulation.
* BaseFSSystem - Basic FS configuration uni-processor and multi-processor
configurations.
* BaseFSSystemUniprocessor - Basic FS configuration for uni-processor
configurations. This is provided as a way
to make existing test cases backwards
compatible.
Architecture specific implementations are provided for ARM, Alpha, and
X86.
This commit is contained in:
Andreas Sandberg
parent
9a645d6e9b
commit
f32f372455
21 changed files with 702 additions and 600 deletions
93
tests/configs/alpha_generic.py
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93
tests/configs/alpha_generic.py
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# Copyright (c) 2012 ARM Limited
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# All rights reserved.
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#
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# The license below extends only to copyright in the software and shall
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# not be construed as granting a license to any other intellectual
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# property including but not limited to intellectual property relating
|
||||
# to a hardware implementation of the functionality of the software
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# licensed hereunder. You may use the software subject to the license
|
||||
# terms below provided that you ensure that this notice is replicated
|
||||
# unmodified and in its entirety in all distributions of the software,
|
||||
# modified or unmodified, in source code or in binary form.
|
||||
#
|
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# Redistribution and use in source and binary forms, with or without
|
||||
# modification, are permitted provided that the following conditions are
|
||||
# met: redistributions of source code must retain the above copyright
|
||||
# notice, this list of conditions and the following disclaimer;
|
||||
# redistributions in binary form must reproduce the above copyright
|
||||
# notice, this list of conditions and the following disclaimer in the
|
||||
# documentation and/or other materials provided with the distribution;
|
||||
# neither the name of the copyright holders nor the names of its
|
||||
# contributors may be used to endorse or promote products derived from
|
||||
# this software without specific prior written permission.
|
||||
#
|
||||
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
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# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
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# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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#
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# Authors: Andreas Sandberg
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from abc import ABCMeta, abstractmethod
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import m5
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from m5.objects import *
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from m5.proxy import *
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m5.util.addToPath('../configs/common')
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import FSConfig
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from Caches import *
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from base_config import *
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class LinuxAlphaSystemBuilder(object):
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"""Mix-in that implements create_system.
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This mix-in is intended as a convenient way of adding an
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Alpha-specific create_system method to a class deriving from one of
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the generic base systems.
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"""
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def __init__(self):
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"""
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Arguments:
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machine_type -- String describing the platform to simulate
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"""
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pass
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def create_system(self):
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system = FSConfig.makeLinuxAlphaSystem(self.mem_mode)
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self.init_system(system)
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return system
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class LinuxAlphaFSSystem(LinuxAlphaSystemBuilder,
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BaseFSSystem):
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"""Basic Alpha full system builder."""
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def __init__(self, **kwargs):
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"""Initialize an Alpha system that supports full system simulation.
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Note: Keyword arguments that are not listed below will be
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passed to the BaseFSSystem.
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Keyword Arguments:
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-
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"""
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BaseSystem.__init__(self, **kwargs)
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LinuxAlphaSystemBuilder.__init__(self)
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class LinuxAlphaFSSystemUniprocessor(LinuxAlphaSystemBuilder,
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BaseFSSystemUniprocessor):
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"""Basic Alpha full system builder for uniprocessor systems.
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Note: This class is a specialization of the AlphaFSSystem and is
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only really needed to provide backwards compatibility for existing
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test cases.
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"""
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def __init__(self, **kwargs):
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BaseFSSystemUniprocessor.__init__(self, **kwargs)
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LinuxAlphaSystemBuilder.__init__(self)
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95
tests/configs/arm_generic.py
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95
tests/configs/arm_generic.py
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# Copyright (c) 2012 ARM Limited
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# All rights reserved.
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#
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# The license below extends only to copyright in the software and shall
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# not be construed as granting a license to any other intellectual
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# property including but not limited to intellectual property relating
|
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# to a hardware implementation of the functionality of the software
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# licensed hereunder. You may use the software subject to the license
|
||||
# terms below provided that you ensure that this notice is replicated
|
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# unmodified and in its entirety in all distributions of the software,
|
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# modified or unmodified, in source code or in binary form.
|
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#
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# Redistribution and use in source and binary forms, with or without
|
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# modification, are permitted provided that the following conditions are
|
||||
# met: redistributions of source code must retain the above copyright
|
||||
# notice, this list of conditions and the following disclaimer;
|
||||
# redistributions in binary form must reproduce the above copyright
|
||||
# notice, this list of conditions and the following disclaimer in the
|
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# documentation and/or other materials provided with the distribution;
|
||||
# neither the name of the copyright holders nor the names of its
|
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# contributors may be used to endorse or promote products derived from
|
||||
# this software without specific prior written permission.
|
||||
#
|
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# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
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# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
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# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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#
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# Authors: Andreas Sandberg
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from abc import ABCMeta, abstractmethod
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import m5
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from m5.objects import *
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from m5.proxy import *
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m5.util.addToPath('../configs/common')
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import FSConfig
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from Caches import *
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from base_config import *
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class LinuxArmSystemBuilder(object):
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"""Mix-in that implements create_system.
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This mix-in is intended as a convenient way of adding an
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ARM-specific create_system method to a class deriving from one of
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the generic base systems.
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"""
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def __init__(self, machine_type):
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"""
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Arguments:
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machine_type -- String describing the platform to simulate
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"""
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self.machine_type = machine_type
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def create_system(self):
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system = FSConfig.makeArmSystem(self.mem_mode,
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self.machine_type,
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None, False)
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self.init_system(system)
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return system
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class LinuxArmFSSystem(LinuxArmSystemBuilder,
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BaseFSSystem):
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"""Basic ARM full system builder."""
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def __init__(self, machine_type='RealView_PBX', **kwargs):
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"""Initialize an ARM system that supports full system simulation.
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Note: Keyword arguments that are not listed below will be
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passed to the BaseFSSystem.
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Keyword Arguments:
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machine_type -- String describing the platform to simulate
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"""
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BaseSystem.__init__(self, **kwargs)
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LinuxArmSystemBuilder.__init__(self, machine_type)
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class LinuxArmFSSystemUniprocessor(LinuxArmSystemBuilder,
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BaseFSSystemUniprocessor):
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"""Basic ARM full system builder for uniprocessor systems.
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Note: This class is a specialization of the ArmFSSystem and is
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only really needed to provide backwards compatibility for existing
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test cases.
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"""
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def __init__(self, machine_type='RealView_PBX', **kwargs):
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BaseFSSystemUniprocessor.__init__(self, **kwargs)
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LinuxArmSystemBuilder.__init__(self, machine_type)
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175
tests/configs/base_config.py
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175
tests/configs/base_config.py
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@ -0,0 +1,175 @@
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# Copyright (c) 2012 ARM Limited
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# All rights reserved.
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#
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# The license below extends only to copyright in the software and shall
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# not be construed as granting a license to any other intellectual
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# property including but not limited to intellectual property relating
|
||||
# to a hardware implementation of the functionality of the software
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# licensed hereunder. You may use the software subject to the license
|
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# terms below provided that you ensure that this notice is replicated
|
||||
# unmodified and in its entirety in all distributions of the software,
|
||||
# modified or unmodified, in source code or in binary form.
|
||||
#
|
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# Redistribution and use in source and binary forms, with or without
|
||||
# modification, are permitted provided that the following conditions are
|
||||
# met: redistributions of source code must retain the above copyright
|
||||
# notice, this list of conditions and the following disclaimer;
|
||||
# redistributions in binary form must reproduce the above copyright
|
||||
# notice, this list of conditions and the following disclaimer in the
|
||||
# documentation and/or other materials provided with the distribution;
|
||||
# neither the name of the copyright holders nor the names of its
|
||||
# contributors may be used to endorse or promote products derived from
|
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# this software without specific prior written permission.
|
||||
#
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# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
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# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
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# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
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# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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#
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# Authors: Andreas Sandberg
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from abc import ABCMeta, abstractmethod
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import m5
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from m5.objects import *
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from m5.proxy import *
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m5.util.addToPath('../configs/common')
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import FSConfig
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from Caches import *
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class BaseSystem(object):
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"""Base system builder.
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This class provides some basic functionality for creating an ARM
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system with the usual peripherals (caches, GIC, etc.). It allows
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customization by defining separate methods for different parts of
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the initialization process.
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"""
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__metaclass__ = ABCMeta
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def __init__(self, mem_mode='timing', cpu_class=TimingSimpleCPU,
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num_cpus=1, checker=False):
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"""Initialize a simple ARM system.
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Keyword Arguments:
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mem_mode -- String describing the memory mode (timing or atomic)
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cpu_class -- CPU class to use
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num_cpus -- Number of CPUs to instantiate
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checker -- Set to True to add checker CPUs
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"""
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self.mem_mode = mem_mode
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self.cpu_class = cpu_class
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self.num_cpus = num_cpus
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self.checker = checker
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def create_cpus(self):
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"""Return a list of CPU objects to add to a system."""
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cpus = [ self.cpu_class(cpu_id=i, clock='2GHz')
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for i in range(self.num_cpus) ]
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if self.checker:
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for c in cpus:
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c.addCheckerCpu()
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return cpus
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def create_caches_private(self, cpu):
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"""Add private caches to a CPU.
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Arguments:
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cpu -- CPU instance to work on.
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"""
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cpu.addPrivateSplitL1Caches(L1Cache(size='32kB', assoc=1),
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L1Cache(size='32kB', assoc=4))
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def create_caches_shared(self, system):
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"""Add shared caches to a system.
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Arguments:
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system -- System to work on.
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Returns:
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A bus that CPUs should use to connect to the shared cache.
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"""
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system.toL2Bus = CoherentBus(clock='2GHz')
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system.l2c = L2Cache(clock='2GHz', size='4MB', assoc=8)
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system.l2c.cpu_side = system.toL2Bus.master
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system.l2c.mem_side = system.membus.slave
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return system.toL2Bus
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def init_cpu(self, system, cpu):
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"""Initialize a CPU.
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Arguments:
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system -- System to work on.
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cpu -- CPU to initialize.
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"""
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cpu.createInterruptController()
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def init_system(self, system):
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"""Initialize a system.
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Arguments:
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system -- System to initialize.
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"""
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system.cpu = self.create_cpus()
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sha_bus = self.create_caches_shared(system)
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for cpu in system.cpu:
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self.create_caches_private(cpu)
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self.init_cpu(system, cpu)
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cpu.connectAllPorts(sha_bus if sha_bus != None else system.membus,
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system.membus)
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@abstractmethod
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def create_system(self):
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"""Create an return an initialized system."""
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pass
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@abstractmethod
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def create_root(self):
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"""Create and return a simulation root using the system
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defined by this class."""
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pass
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class BaseFSSystem(BaseSystem):
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"""Basic full system builder."""
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def __init__(self, **kwargs):
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BaseSystem.__init__(self, **kwargs)
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def init_system(self, system):
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BaseSystem.init_system(self, system)
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#create the iocache
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system.iocache = IOCache(clock='1GHz', addr_ranges=[system.physmem.range])
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system.iocache.cpu_side = system.iobus.master
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system.iocache.mem_side = system.membus.slave
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def create_root(self):
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system = self.create_system()
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m5.ticks.setGlobalFrequency('1THz')
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return Root(full_system=True, system=system)
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class BaseFSSystemUniprocessor(BaseFSSystem):
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"""Basic full system builder for uniprocessor systems.
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Note: This class is only really needed to provide backwards
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compatibility in existing test cases.
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"""
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def __init__(self, **kwargs):
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BaseFSSystem.__init__(self, **kwargs)
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def create_caches_private(self, cpu):
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cpu.addTwoLevelCacheHierarchy(L1Cache(size='32kB', assoc=1),
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L1Cache(size='32kB', assoc=4),
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L2Cache(size='4MB', assoc=8))
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def create_caches_shared(self, system):
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return None
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@ -1,6 +1,15 @@
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# Copyright (c) 2006-2007 The Regents of The University of Michigan
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# Copyright (c) 2012 ARM Limited
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# All rights reserved.
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#
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# The license below extends only to copyright in the software and shall
|
||||
# not be construed as granting a license to any other intellectual
|
||||
# property including but not limited to intellectual property relating
|
||||
# to a hardware implementation of the functionality of the software
|
||||
# licensed hereunder. You may use the software subject to the license
|
||||
# terms below provided that you ensure that this notice is replicated
|
||||
# unmodified and in its entirety in all distributions of the software,
|
||||
# modified or unmodified, in source code or in binary form.
|
||||
#
|
||||
# Redistribution and use in source and binary forms, with or without
|
||||
# modification, are permitted provided that the following conditions are
|
||||
# met: redistributions of source code must retain the above copyright
|
||||
|
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@ -24,44 +33,10 @@
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# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
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#
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# Authors: Steve Reinhardt
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# Authors: Andreas Sandberg
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import m5
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from m5.objects import *
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m5.util.addToPath('../configs/common')
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from Benchmarks import SysConfig
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import FSConfig
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from Caches import *
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mem_size = '128MB'
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#cpu
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cpu = DerivO3CPU(cpu_id=0)
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#the system
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mdesc = SysConfig(disk = 'linux-x86.img')
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system = FSConfig.makeLinuxX86System('timing', mdesc=mdesc)
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system.kernel = FSConfig.binary('x86_64-vmlinux-2.6.22.9')
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system.cpu = cpu
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#create the iocache
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system.iocache = IOCache(clock = '1GHz', addr_ranges = [AddrRange(mem_size)])
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system.iocache.cpu_side = system.iobus.master
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system.iocache.mem_side = system.membus.slave
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#connect up the cpu and caches
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cpu.addTwoLevelCacheHierarchy(L1Cache(size = '32kB', assoc = 1),
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L1Cache(size = '32kB', assoc = 4),
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L2Cache(size = '4MB', assoc = 8),
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PageTableWalkerCache(),
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PageTableWalkerCache())
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# create the interrupt controller
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cpu.createInterruptController()
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# connect cpu and caches to the rest of the system
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cpu.connectAllPorts(system.membus)
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# set the cpu clock along with the caches and l1-l2 bus
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cpu.clock = '2GHz'
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root = Root(full_system=True, system=system)
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m5.ticks.setGlobalFrequency('1THz')
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from x86_generic import *
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root = LinuxX86FSSystemUniprocessor(mem_mode='timing',
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cpu_class=DerivO3CPU).create_root()
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@ -1,6 +1,15 @@
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# Copyright (c) 2006-2007 The Regents of The University of Michigan
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# Copyright (c) 2012 ARM Limited
|
||||
# All rights reserved.
|
||||
#
|
||||
# The license below extends only to copyright in the software and shall
|
||||
# not be construed as granting a license to any other intellectual
|
||||
# property including but not limited to intellectual property relating
|
||||
# to a hardware implementation of the functionality of the software
|
||||
# licensed hereunder. You may use the software subject to the license
|
||||
# terms below provided that you ensure that this notice is replicated
|
||||
# unmodified and in its entirety in all distributions of the software,
|
||||
# modified or unmodified, in source code or in binary form.
|
||||
#
|
||||
# Redistribution and use in source and binary forms, with or without
|
||||
# modification, are permitted provided that the following conditions are
|
||||
# met: redistributions of source code must retain the above copyright
|
||||
|
|
@ -24,44 +33,10 @@
|
|||
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
#
|
||||
# Authors: Steve Reinhardt
|
||||
# Authors: Andreas Sandberg
|
||||
|
||||
import m5
|
||||
from m5.objects import *
|
||||
m5.util.addToPath('../configs/common')
|
||||
from Benchmarks import SysConfig
|
||||
import FSConfig
|
||||
from Caches import *
|
||||
|
||||
mem_size = '128MB'
|
||||
|
||||
#cpu
|
||||
cpu = AtomicSimpleCPU(cpu_id=0)
|
||||
#the system
|
||||
mdesc = SysConfig(disk = 'linux-x86.img')
|
||||
system = FSConfig.makeLinuxX86System('atomic', mdesc=mdesc)
|
||||
system.kernel = FSConfig.binary('x86_64-vmlinux-2.6.22.9')
|
||||
|
||||
system.cpu = cpu
|
||||
|
||||
#create the iocache
|
||||
system.iocache = IOCache(clock = '1GHz', addr_ranges = [AddrRange(mem_size)])
|
||||
system.iocache.cpu_side = system.iobus.master
|
||||
system.iocache.mem_side = system.membus.slave
|
||||
|
||||
#connect up the cpu and caches
|
||||
cpu.addTwoLevelCacheHierarchy(L1Cache(size = '32kB', assoc = 1),
|
||||
L1Cache(size = '32kB', assoc = 4),
|
||||
L2Cache(size = '4MB', assoc = 8),
|
||||
PageTableWalkerCache(),
|
||||
PageTableWalkerCache())
|
||||
# create the interrupt controller
|
||||
cpu.createInterruptController()
|
||||
# connect cpu and caches to the rest of the system
|
||||
cpu.connectAllPorts(system.membus)
|
||||
# set the cpu clock along with the caches and l1-l2 bus
|
||||
cpu.clock = '2GHz'
|
||||
|
||||
root = Root(full_system=True, system=system)
|
||||
m5.ticks.setGlobalFrequency('1THz')
|
||||
from x86_generic import *
|
||||
|
||||
root = LinuxX86FSSystemUniprocessor(mem_mode='atomic',
|
||||
cpu_class=AtomicSimpleCPU).create_root()
|
||||
|
|
|
|||
|
|
@ -1,6 +1,15 @@
|
|||
# Copyright (c) 2006-2007 The Regents of The University of Michigan
|
||||
# Copyright (c) 2012 ARM Limited
|
||||
# All rights reserved.
|
||||
#
|
||||
# The license below extends only to copyright in the software and shall
|
||||
# not be construed as granting a license to any other intellectual
|
||||
# property including but not limited to intellectual property relating
|
||||
# to a hardware implementation of the functionality of the software
|
||||
# licensed hereunder. You may use the software subject to the license
|
||||
# terms below provided that you ensure that this notice is replicated
|
||||
# unmodified and in its entirety in all distributions of the software,
|
||||
# modified or unmodified, in source code or in binary form.
|
||||
#
|
||||
# Redistribution and use in source and binary forms, with or without
|
||||
# modification, are permitted provided that the following conditions are
|
||||
# met: redistributions of source code must retain the above copyright
|
||||
|
|
@ -24,44 +33,11 @@
|
|||
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
#
|
||||
# Authors: Steve Reinhardt
|
||||
# Authors: Andreas Sandberg
|
||||
|
||||
import m5
|
||||
from m5.objects import *
|
||||
m5.util.addToPath('../configs/common')
|
||||
from Benchmarks import SysConfig
|
||||
import FSConfig
|
||||
from Caches import *
|
||||
from x86_generic import *
|
||||
|
||||
mem_size = '128MB'
|
||||
|
||||
#cpu
|
||||
cpu = TimingSimpleCPU(cpu_id=0)
|
||||
#the system
|
||||
mdesc = SysConfig(disk = 'linux-x86.img')
|
||||
system = FSConfig.makeLinuxX86System('timing', mdesc = mdesc)
|
||||
system.kernel = FSConfig.binary('x86_64-vmlinux-2.6.22.9')
|
||||
|
||||
system.cpu = cpu
|
||||
|
||||
#create the iocache
|
||||
system.iocache = IOCache(clock = '1GHz', addr_ranges = [AddrRange(mem_size)])
|
||||
system.iocache.cpu_side = system.iobus.master
|
||||
system.iocache.mem_side = system.membus.slave
|
||||
|
||||
#connect up the cpu and caches
|
||||
cpu.addTwoLevelCacheHierarchy(L1Cache(size = '32kB', assoc = 1),
|
||||
L1Cache(size = '32kB', assoc = 4),
|
||||
L2Cache(size = '4MB', assoc = 8),
|
||||
PageTableWalkerCache(),
|
||||
PageTableWalkerCache())
|
||||
# create the interrupt controller
|
||||
cpu.createInterruptController()
|
||||
# connect cpu and caches to the rest of the system
|
||||
cpu.connectAllPorts(system.membus)
|
||||
# set the cpu clock along with the caches and l1-l2 bus
|
||||
cpu.clock = '2GHz'
|
||||
|
||||
root = Root(full_system=True, system=system)
|
||||
m5.ticks.setGlobalFrequency('1THz')
|
||||
root = LinuxX86FSSystemUniprocessor(mem_mode='timing',
|
||||
cpu_class=TimingSimpleCPU).create_root()
|
||||
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
# Copyright (c) 2011 ARM Limited
|
||||
# All rights reserved
|
||||
# Copyright (c) 2012 ARM Limited
|
||||
# All rights reserved.
|
||||
#
|
||||
# The license below extends only to copyright in the software and shall
|
||||
# not be construed as granting a license to any other intellectual
|
||||
|
|
@ -33,39 +33,11 @@
|
|||
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
#
|
||||
# Authors: Geoffrey Blake
|
||||
# Authors: Andreas Sandberg
|
||||
|
||||
import m5
|
||||
from m5.objects import *
|
||||
m5.util.addToPath('../configs/common')
|
||||
import FSConfig
|
||||
from Caches import *
|
||||
|
||||
#cpu
|
||||
cpu = DerivO3CPU(cpu_id=0)
|
||||
#the system
|
||||
system = FSConfig.makeArmSystem('timing', "RealView_PBX", None, False)
|
||||
|
||||
system.cpu = cpu
|
||||
#connect up the checker
|
||||
cpu.addCheckerCpu()
|
||||
|
||||
#create the iocache
|
||||
system.iocache = IOCache(clock = '1GHz', addr_ranges = [AddrRange('256MB')])
|
||||
system.iocache.cpu_side = system.iobus.master
|
||||
system.iocache.mem_side = system.membus.slave
|
||||
|
||||
#connect up the cpu and caches
|
||||
cpu.addTwoLevelCacheHierarchy(L1Cache(size = '32kB', assoc = 1),
|
||||
L1Cache(size = '32kB', assoc = 4),
|
||||
L2Cache(size = '4MB', assoc = 8))
|
||||
# create the interrupt controller
|
||||
cpu.createInterruptController()
|
||||
# connect cpu and caches to the rest of the system
|
||||
cpu.connectAllPorts(system.membus)
|
||||
# set the cpu clock along with the caches and l1-l2 bus
|
||||
cpu.clock = '2GHz'
|
||||
|
||||
root = Root(full_system=True, system=system)
|
||||
m5.ticks.setGlobalFrequency('1THz')
|
||||
from arm_generic import *
|
||||
|
||||
root = LinuxArmFSSystemUniprocessor(mem_mode='timing',
|
||||
cpu_class=DerivO3CPU,
|
||||
checker=True).create_root()
|
||||
|
|
|
|||
|
|
@ -1,6 +1,15 @@
|
|||
# Copyright (c) 2006-2007 The Regents of The University of Michigan
|
||||
# Copyright (c) 2012 ARM Limited
|
||||
# All rights reserved.
|
||||
#
|
||||
# The license below extends only to copyright in the software and shall
|
||||
# not be construed as granting a license to any other intellectual
|
||||
# property including but not limited to intellectual property relating
|
||||
# to a hardware implementation of the functionality of the software
|
||||
# licensed hereunder. You may use the software subject to the license
|
||||
# terms below provided that you ensure that this notice is replicated
|
||||
# unmodified and in its entirety in all distributions of the software,
|
||||
# modified or unmodified, in source code or in binary form.
|
||||
#
|
||||
# Redistribution and use in source and binary forms, with or without
|
||||
# modification, are permitted provided that the following conditions are
|
||||
# met: redistributions of source code must retain the above copyright
|
||||
|
|
@ -24,43 +33,10 @@
|
|||
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
#
|
||||
# Authors: Steve Reinhardt
|
||||
# Authors: Andreas Sandberg
|
||||
|
||||
import m5
|
||||
from m5.objects import *
|
||||
m5.util.addToPath('../configs/common')
|
||||
import FSConfig
|
||||
from Benchmarks import *
|
||||
from Caches import *
|
||||
|
||||
#cpu
|
||||
cpus = [DerivO3CPU(cpu_id=i) for i in xrange(2) ]
|
||||
#the system
|
||||
system = FSConfig.makeArmSystem('timing', "RealView_PBX", None, False)
|
||||
system.iocache = IOCache(clock = '1GHz', addr_ranges = [AddrRange('256MB')])
|
||||
system.iocache.cpu_side = system.iobus.master
|
||||
system.iocache.mem_side = system.membus.slave
|
||||
|
||||
system.cpu = cpus
|
||||
#create the l1/l2 bus
|
||||
system.toL2Bus = CoherentBus(clock = '2GHz')
|
||||
|
||||
#connect up the l2 cache
|
||||
system.l2c = L2Cache(clock = '2GHz', size='4MB', assoc=8)
|
||||
system.l2c.cpu_side = system.toL2Bus.master
|
||||
system.l2c.mem_side = system.membus.slave
|
||||
|
||||
#connect up the cpu and l1s
|
||||
for c in cpus:
|
||||
c.addPrivateSplitL1Caches(L1Cache(size = '32kB', assoc = 1),
|
||||
L1Cache(size = '32kB', assoc = 4))
|
||||
# create the interrupt controller
|
||||
c.createInterruptController()
|
||||
# connect cpu level-1 caches to shared level-2 cache
|
||||
c.connectAllPorts(system.toL2Bus, system.membus)
|
||||
c.clock = '2GHz'
|
||||
|
||||
|
||||
root = Root(full_system=True, system=system)
|
||||
m5.ticks.setGlobalFrequency('1THz')
|
||||
from arm_generic import *
|
||||
|
||||
root = LinuxArmFSSystem(mem_mode='timing', cpu_class=DerivO3CPU,
|
||||
num_cpus=2).create_root()
|
||||
|
|
|
|||
|
|
@ -1,6 +1,15 @@
|
|||
# Copyright (c) 2006-2007 The Regents of The University of Michigan
|
||||
# Copyright (c) 2012 ARM Limited
|
||||
# All rights reserved.
|
||||
#
|
||||
# The license below extends only to copyright in the software and shall
|
||||
# not be construed as granting a license to any other intellectual
|
||||
# property including but not limited to intellectual property relating
|
||||
# to a hardware implementation of the functionality of the software
|
||||
# licensed hereunder. You may use the software subject to the license
|
||||
# terms below provided that you ensure that this notice is replicated
|
||||
# unmodified and in its entirety in all distributions of the software,
|
||||
# modified or unmodified, in source code or in binary form.
|
||||
#
|
||||
# Redistribution and use in source and binary forms, with or without
|
||||
# modification, are permitted provided that the following conditions are
|
||||
# met: redistributions of source code must retain the above copyright
|
||||
|
|
@ -24,37 +33,10 @@
|
|||
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
#
|
||||
# Authors: Steve Reinhardt
|
||||
# Authors: Andreas Sandberg
|
||||
|
||||
import m5
|
||||
from m5.objects import *
|
||||
m5.util.addToPath('../configs/common')
|
||||
import FSConfig
|
||||
from Caches import *
|
||||
|
||||
#cpu
|
||||
cpu = DerivO3CPU(cpu_id=0)
|
||||
#the system
|
||||
system = FSConfig.makeArmSystem('timing', "RealView_PBX", None, False)
|
||||
|
||||
system.cpu = cpu
|
||||
|
||||
#create the iocache
|
||||
system.iocache = IOCache(clock = '1GHz', addr_ranges = [AddrRange('256MB')])
|
||||
system.iocache.cpu_side = system.iobus.master
|
||||
system.iocache.mem_side = system.membus.slave
|
||||
|
||||
#connect up the cpu and caches
|
||||
cpu.addTwoLevelCacheHierarchy(L1Cache(size = '32kB', assoc = 1),
|
||||
L1Cache(size = '32kB', assoc = 4),
|
||||
L2Cache(size = '4MB', assoc = 8))
|
||||
# create the interrupt controller
|
||||
cpu.createInterruptController()
|
||||
# connect cpu and caches to the rest of the system
|
||||
cpu.connectAllPorts(system.membus)
|
||||
# set the cpu clock along with the caches and l1-l2 bus
|
||||
cpu.clock = '2GHz'
|
||||
|
||||
root = Root(full_system=True, system=system)
|
||||
m5.ticks.setGlobalFrequency('1THz')
|
||||
from arm_generic import *
|
||||
|
||||
root = LinuxArmFSSystemUniprocessor(mem_mode='timing',
|
||||
cpu_class=DerivO3CPU).create_root()
|
||||
|
|
|
|||
|
|
@ -1,6 +1,15 @@
|
|||
# Copyright (c) 2006-2007 The Regents of The University of Michigan
|
||||
# Copyright (c) 2012 ARM Limited
|
||||
# All rights reserved.
|
||||
#
|
||||
# The license below extends only to copyright in the software and shall
|
||||
# not be construed as granting a license to any other intellectual
|
||||
# property including but not limited to intellectual property relating
|
||||
# to a hardware implementation of the functionality of the software
|
||||
# licensed hereunder. You may use the software subject to the license
|
||||
# terms below provided that you ensure that this notice is replicated
|
||||
# unmodified and in its entirety in all distributions of the software,
|
||||
# modified or unmodified, in source code or in binary form.
|
||||
#
|
||||
# Redistribution and use in source and binary forms, with or without
|
||||
# modification, are permitted provided that the following conditions are
|
||||
# met: redistributions of source code must retain the above copyright
|
||||
|
|
@ -24,43 +33,10 @@
|
|||
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
#
|
||||
# Authors: Steve Reinhardt
|
||||
# Authors: Andreas Sandberg
|
||||
|
||||
import m5
|
||||
from m5.objects import *
|
||||
m5.util.addToPath('../configs/common')
|
||||
import FSConfig
|
||||
from Benchmarks import *
|
||||
from Caches import *
|
||||
|
||||
#cpu
|
||||
cpus = [AtomicSimpleCPU(cpu_id=i) for i in xrange(2) ]
|
||||
#the system
|
||||
system = FSConfig.makeArmSystem('atomic', "RealView_PBX", None, False)
|
||||
system.iocache = IOCache(clock = '1GHz', addr_ranges = [AddrRange('256MB')])
|
||||
system.iocache.cpu_side = system.iobus.master
|
||||
system.iocache.mem_side = system.membus.slave
|
||||
|
||||
system.cpu = cpus
|
||||
#create the l1/l2 bus
|
||||
system.toL2Bus = CoherentBus(clock = '2GHz')
|
||||
|
||||
#connect up the l2 cache
|
||||
system.l2c = L2Cache(clock = '2GHz', size='4MB', assoc=8)
|
||||
system.l2c.cpu_side = system.toL2Bus.master
|
||||
system.l2c.mem_side = system.membus.slave
|
||||
|
||||
#connect up the cpu and l1s
|
||||
for c in cpus:
|
||||
c.addPrivateSplitL1Caches(L1Cache(size = '32kB', assoc = 1),
|
||||
L1Cache(size = '32kB', assoc = 4))
|
||||
# create the interrupt controller
|
||||
c.createInterruptController()
|
||||
# connect cpu level-1 caches to shared level-2 cache
|
||||
c.connectAllPorts(system.toL2Bus, system.membus)
|
||||
c.clock = '2GHz'
|
||||
|
||||
|
||||
root = Root(full_system=True, system=system)
|
||||
m5.ticks.setGlobalFrequency('1THz')
|
||||
from arm_generic import *
|
||||
|
||||
root = LinuxArmFSSystem(mem_mode='atomic', cpu_class=AtomicSimpleCPU,
|
||||
num_cpus=2).create_root()
|
||||
|
|
|
|||
|
|
@ -1,6 +1,15 @@
|
|||
# Copyright (c) 2006-2007 The Regents of The University of Michigan
|
||||
# Copyright (c) 2012 ARM Limited
|
||||
# All rights reserved.
|
||||
#
|
||||
# The license below extends only to copyright in the software and shall
|
||||
# not be construed as granting a license to any other intellectual
|
||||
# property including but not limited to intellectual property relating
|
||||
# to a hardware implementation of the functionality of the software
|
||||
# licensed hereunder. You may use the software subject to the license
|
||||
# terms below provided that you ensure that this notice is replicated
|
||||
# unmodified and in its entirety in all distributions of the software,
|
||||
# modified or unmodified, in source code or in binary form.
|
||||
#
|
||||
# Redistribution and use in source and binary forms, with or without
|
||||
# modification, are permitted provided that the following conditions are
|
||||
# met: redistributions of source code must retain the above copyright
|
||||
|
|
@ -24,37 +33,11 @@
|
|||
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
#
|
||||
# Authors: Steve Reinhardt
|
||||
# Authors: Andreas Sandberg
|
||||
|
||||
import m5
|
||||
from m5.objects import *
|
||||
m5.util.addToPath('../configs/common')
|
||||
import FSConfig
|
||||
from Caches import *
|
||||
from arm_generic import *
|
||||
|
||||
#cpu
|
||||
cpu = AtomicSimpleCPU(cpu_id=0)
|
||||
#the system
|
||||
system = FSConfig.makeArmSystem('atomic', "RealView_PBX", None, False)
|
||||
|
||||
system.cpu = cpu
|
||||
|
||||
#create the iocache
|
||||
system.iocache = IOCache(clock = '1GHz', addr_ranges = [AddrRange('256MB')])
|
||||
system.iocache.cpu_side = system.iobus.master
|
||||
system.iocache.mem_side = system.membus.slave
|
||||
|
||||
#connect up the cpu and caches
|
||||
cpu.addTwoLevelCacheHierarchy(L1Cache(size = '32kB', assoc = 1),
|
||||
L1Cache(size = '32kB', assoc = 4),
|
||||
L2Cache(size = '4MB', assoc = 8))
|
||||
# create the interrupt controller
|
||||
cpu.createInterruptController()
|
||||
# connect cpu and caches to the rest of the system
|
||||
cpu.connectAllPorts(system.membus)
|
||||
# set the cpu clock along with the caches and l1-l2 bus
|
||||
cpu.clock = '2GHz'
|
||||
|
||||
root = Root(full_system=True, system=system)
|
||||
m5.ticks.setGlobalFrequency('1THz')
|
||||
root = LinuxArmFSSystemUniprocessor(mem_mode='atomic',
|
||||
cpu_class=AtomicSimpleCPU).create_root()
|
||||
|
||||
|
|
|
|||
|
|
@ -1,6 +1,15 @@
|
|||
# Copyright (c) 2006-2007 The Regents of The University of Michigan
|
||||
# Copyright (c) 2012 ARM Limited
|
||||
# All rights reserved.
|
||||
#
|
||||
# The license below extends only to copyright in the software and shall
|
||||
# not be construed as granting a license to any other intellectual
|
||||
# property including but not limited to intellectual property relating
|
||||
# to a hardware implementation of the functionality of the software
|
||||
# licensed hereunder. You may use the software subject to the license
|
||||
# terms below provided that you ensure that this notice is replicated
|
||||
# unmodified and in its entirety in all distributions of the software,
|
||||
# modified or unmodified, in source code or in binary form.
|
||||
#
|
||||
# Redistribution and use in source and binary forms, with or without
|
||||
# modification, are permitted provided that the following conditions are
|
||||
# met: redistributions of source code must retain the above copyright
|
||||
|
|
@ -24,43 +33,10 @@
|
|||
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
#
|
||||
# Authors: Steve Reinhardt
|
||||
# Authors: Andreas Sandberg
|
||||
|
||||
import m5
|
||||
from m5.objects import *
|
||||
m5.util.addToPath('../configs/common')
|
||||
import FSConfig
|
||||
from Benchmarks import *
|
||||
from Caches import *
|
||||
|
||||
#cpu
|
||||
cpus = [TimingSimpleCPU(cpu_id=i) for i in xrange(2) ]
|
||||
#the system
|
||||
system = FSConfig.makeArmSystem('timing', "RealView_PBX", None, False)
|
||||
system.iocache = IOCache(clock = '1GHz', addr_ranges = [AddrRange('256MB')])
|
||||
system.iocache.cpu_side = system.iobus.master
|
||||
system.iocache.mem_side = system.membus.slave
|
||||
|
||||
system.cpu = cpus
|
||||
#create the l1/l2 bus
|
||||
system.toL2Bus = CoherentBus(clock = '2GHz')
|
||||
|
||||
#connect up the l2 cache
|
||||
system.l2c = L2Cache(clock = '2GHz', size='4MB', assoc=8)
|
||||
system.l2c.cpu_side = system.toL2Bus.master
|
||||
system.l2c.mem_side = system.membus.slave
|
||||
|
||||
#connect up the cpu and l1s
|
||||
for c in cpus:
|
||||
c.addPrivateSplitL1Caches(L1Cache(size = '32kB', assoc = 1),
|
||||
L1Cache(size = '32kB', assoc = 4))
|
||||
# create the interrupt controller
|
||||
c.createInterruptController()
|
||||
# connect cpu level-1 caches to shared level-2 cache
|
||||
c.connectAllPorts(system.toL2Bus, system.membus)
|
||||
c.clock = '2GHz'
|
||||
|
||||
|
||||
root = Root(full_system=True, system=system)
|
||||
m5.ticks.setGlobalFrequency('1THz')
|
||||
from arm_generic import *
|
||||
|
||||
root = LinuxArmFSSystem(mem_mode='timing', cpu_class=TimingSimpleCPU,
|
||||
num_cpus=2).create_root()
|
||||
|
|
|
|||
|
|
@ -1,6 +1,15 @@
|
|||
# Copyright (c) 2006-2007 The Regents of The University of Michigan
|
||||
# Copyright (c) 2012 ARM Limited
|
||||
# All rights reserved.
|
||||
#
|
||||
# The license below extends only to copyright in the software and shall
|
||||
# not be construed as granting a license to any other intellectual
|
||||
# property including but not limited to intellectual property relating
|
||||
# to a hardware implementation of the functionality of the software
|
||||
# licensed hereunder. You may use the software subject to the license
|
||||
# terms below provided that you ensure that this notice is replicated
|
||||
# unmodified and in its entirety in all distributions of the software,
|
||||
# modified or unmodified, in source code or in binary form.
|
||||
#
|
||||
# Redistribution and use in source and binary forms, with or without
|
||||
# modification, are permitted provided that the following conditions are
|
||||
# met: redistributions of source code must retain the above copyright
|
||||
|
|
@ -24,37 +33,10 @@
|
|||
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
#
|
||||
# Authors: Steve Reinhardt
|
||||
# Authors: Andreas Sandberg
|
||||
|
||||
import m5
|
||||
from m5.objects import *
|
||||
m5.util.addToPath('../configs/common')
|
||||
import FSConfig
|
||||
from Caches import *
|
||||
|
||||
#cpu
|
||||
cpu = TimingSimpleCPU(cpu_id=0)
|
||||
#the system
|
||||
system = FSConfig.makeArmSystem('timing', "RealView_PBX", None, False)
|
||||
|
||||
system.cpu = cpu
|
||||
|
||||
#create the iocache
|
||||
system.iocache = IOCache(clock = '1GHz', addr_ranges = [AddrRange('256MB')])
|
||||
system.iocache.cpu_side = system.iobus.master
|
||||
system.iocache.mem_side = system.membus.slave
|
||||
|
||||
#connect up the cpu and caches
|
||||
cpu.addTwoLevelCacheHierarchy(L1Cache(size = '32kB', assoc = 1),
|
||||
L1Cache(size = '32kB', assoc = 4),
|
||||
L2Cache(size = '4MB', assoc = 8))
|
||||
# create the interrupt controller
|
||||
cpu.createInterruptController()
|
||||
# connect cpu and caches to the rest of the system
|
||||
cpu.connectAllPorts(system.membus)
|
||||
# set the cpu clock along with the caches and l1-l2 bus
|
||||
cpu.clock = '2GHz'
|
||||
|
||||
root = Root(full_system=True, system=system)
|
||||
m5.ticks.setGlobalFrequency('1THz')
|
||||
from arm_generic import *
|
||||
|
||||
root = LinuxArmFSSystemUniprocessor(mem_mode='timing',
|
||||
cpu_class=TimingSimpleCPU).create_root()
|
||||
|
|
|
|||
|
|
@ -1,6 +1,15 @@
|
|||
# Copyright (c) 2006-2007 The Regents of The University of Michigan
|
||||
# Copyright (c) 2012 ARM Limited
|
||||
# All rights reserved.
|
||||
#
|
||||
# The license below extends only to copyright in the software and shall
|
||||
# not be construed as granting a license to any other intellectual
|
||||
# property including but not limited to intellectual property relating
|
||||
# to a hardware implementation of the functionality of the software
|
||||
# licensed hereunder. You may use the software subject to the license
|
||||
# terms below provided that you ensure that this notice is replicated
|
||||
# unmodified and in its entirety in all distributions of the software,
|
||||
# modified or unmodified, in source code or in binary form.
|
||||
#
|
||||
# Redistribution and use in source and binary forms, with or without
|
||||
# modification, are permitted provided that the following conditions are
|
||||
# met: redistributions of source code must retain the above copyright
|
||||
|
|
@ -24,40 +33,10 @@
|
|||
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
#
|
||||
# Authors: Steve Reinhardt
|
||||
# Authors: Andreas Sandberg
|
||||
|
||||
import m5
|
||||
from m5.objects import *
|
||||
m5.util.addToPath('../configs/common')
|
||||
import FSConfig
|
||||
from Caches import *
|
||||
|
||||
#cpu
|
||||
cpu = InOrderCPU(cpu_id=0)
|
||||
cpu.stageWidth = 4
|
||||
cpu.fetchBuffSize = 1
|
||||
|
||||
#the system
|
||||
system = FSConfig.makeLinuxAlphaSystem('timing')
|
||||
|
||||
system.cpu = cpu
|
||||
|
||||
#create the iocache
|
||||
system.iocache = IOCache(clock = '1GHz', addr_ranges = [AddrRange('8GB')])
|
||||
system.iocache.cpu_side = system.iobus.master
|
||||
system.iocache.mem_side = system.membus.slave
|
||||
|
||||
#connect up the cpu and caches
|
||||
cpu.addTwoLevelCacheHierarchy(L1Cache(size = '32kB', assoc = 1),
|
||||
L1Cache(size = '32kB', assoc = 4),
|
||||
L2Cache(size = '4MB', assoc = 8))
|
||||
# create the interrupt controller
|
||||
cpu.createInterruptController()
|
||||
# connect cpu and caches to the rest of the system
|
||||
cpu.connectAllPorts(system.membus)
|
||||
# set the cpu clock along with the caches and l1-l2 bus
|
||||
cpu.clock = '2GHz'
|
||||
|
||||
root = Root(full_system=True, system=system)
|
||||
m5.ticks.setGlobalFrequency('1THz')
|
||||
from alpha_generic import *
|
||||
|
||||
root = LinuxAlphaFSSystemUniprocessor(mem_mode='timing',
|
||||
cpu_class=InOrderCPU).create_root()
|
||||
|
|
|
|||
|
|
@ -1,6 +1,15 @@
|
|||
# Copyright (c) 2006-2007 The Regents of The University of Michigan
|
||||
# Copyright (c) 2012 ARM Limited
|
||||
# All rights reserved.
|
||||
#
|
||||
# The license below extends only to copyright in the software and shall
|
||||
# not be construed as granting a license to any other intellectual
|
||||
# property including but not limited to intellectual property relating
|
||||
# to a hardware implementation of the functionality of the software
|
||||
# licensed hereunder. You may use the software subject to the license
|
||||
# terms below provided that you ensure that this notice is replicated
|
||||
# unmodified and in its entirety in all distributions of the software,
|
||||
# modified or unmodified, in source code or in binary form.
|
||||
#
|
||||
# Redistribution and use in source and binary forms, with or without
|
||||
# modification, are permitted provided that the following conditions are
|
||||
# met: redistributions of source code must retain the above copyright
|
||||
|
|
@ -24,42 +33,10 @@
|
|||
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
#
|
||||
# Authors: Steve Reinhardt
|
||||
# Authors: Andreas Sandberg
|
||||
|
||||
import m5
|
||||
from m5.objects import *
|
||||
m5.util.addToPath('../configs/common')
|
||||
import FSConfig
|
||||
from Caches import *
|
||||
|
||||
#cpu
|
||||
cpus = [ DerivO3CPU(cpu_id=i) for i in xrange(2) ]
|
||||
#the system
|
||||
system = FSConfig.makeLinuxAlphaSystem('timing')
|
||||
|
||||
system.cpu = cpus
|
||||
#create the l1/l2 bus
|
||||
system.toL2Bus = CoherentBus(clock = '2GHz')
|
||||
system.iocache = IOCache(clock = '1GHz', addr_ranges = [AddrRange('8GB')])
|
||||
system.iocache.cpu_side = system.iobus.master
|
||||
system.iocache.mem_side = system.membus.slave
|
||||
|
||||
|
||||
#connect up the l2 cache
|
||||
system.l2c = L2Cache(clock = '2GHz', size='4MB', assoc=8)
|
||||
system.l2c.cpu_side = system.toL2Bus.master
|
||||
system.l2c.mem_side = system.membus.slave
|
||||
|
||||
#connect up the cpu and l1s
|
||||
for c in cpus:
|
||||
c.addPrivateSplitL1Caches(L1Cache(size = '32kB', assoc = 1),
|
||||
L1Cache(size = '32kB', assoc = 4))
|
||||
# create the interrupt controller
|
||||
c.createInterruptController()
|
||||
# connect cpu level-1 caches to shared level-2 cache
|
||||
c.connectAllPorts(system.toL2Bus, system.membus)
|
||||
c.clock = '2GHz'
|
||||
|
||||
root = Root(full_system=True, system=system)
|
||||
m5.ticks.setGlobalFrequency('1THz')
|
||||
from alpha_generic import *
|
||||
|
||||
root = LinuxAlphaFSSystem(mem_mode='timing', cpu_class=DerivO3CPU,
|
||||
num_cpus=2).create_root()
|
||||
|
|
|
|||
|
|
@ -1,6 +1,15 @@
|
|||
# Copyright (c) 2006-2007 The Regents of The University of Michigan
|
||||
# Copyright (c) 2012 ARM Limited
|
||||
# All rights reserved.
|
||||
#
|
||||
# The license below extends only to copyright in the software and shall
|
||||
# not be construed as granting a license to any other intellectual
|
||||
# property including but not limited to intellectual property relating
|
||||
# to a hardware implementation of the functionality of the software
|
||||
# licensed hereunder. You may use the software subject to the license
|
||||
# terms below provided that you ensure that this notice is replicated
|
||||
# unmodified and in its entirety in all distributions of the software,
|
||||
# modified or unmodified, in source code or in binary form.
|
||||
#
|
||||
# Redistribution and use in source and binary forms, with or without
|
||||
# modification, are permitted provided that the following conditions are
|
||||
# met: redistributions of source code must retain the above copyright
|
||||
|
|
@ -24,37 +33,10 @@
|
|||
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
#
|
||||
# Authors: Steve Reinhardt
|
||||
# Authors: Andreas Sandberg
|
||||
|
||||
import m5
|
||||
from m5.objects import *
|
||||
m5.util.addToPath('../configs/common')
|
||||
import FSConfig
|
||||
from Caches import *
|
||||
|
||||
#cpu
|
||||
cpu = DerivO3CPU(cpu_id=0)
|
||||
#the system
|
||||
system = FSConfig.makeLinuxAlphaSystem('timing')
|
||||
|
||||
system.cpu = cpu
|
||||
|
||||
#create the iocache
|
||||
system.iocache = IOCache(clock = '1GHz', addr_ranges = [AddrRange('8GB')])
|
||||
system.iocache.cpu_side = system.iobus.master
|
||||
system.iocache.mem_side = system.membus.slave
|
||||
|
||||
#connect up the cpu and caches
|
||||
cpu.addTwoLevelCacheHierarchy(L1Cache(size = '32kB', assoc = 1),
|
||||
L1Cache(size = '32kB', assoc = 4),
|
||||
L2Cache(size = '4MB', assoc = 8))
|
||||
# create the interrupt controller
|
||||
cpu.createInterruptController()
|
||||
# connect cpu and caches to the rest of the system
|
||||
cpu.connectAllPorts(system.membus)
|
||||
# set the cpu clock along with the caches and l1-l2 bus
|
||||
cpu.clock = '2GHz'
|
||||
|
||||
root = Root(full_system=True, system=system)
|
||||
m5.ticks.setGlobalFrequency('1THz')
|
||||
from alpha_generic import *
|
||||
|
||||
root = LinuxAlphaFSSystemUniprocessor(mem_mode='timing',
|
||||
cpu_class=DerivO3CPU).create_root()
|
||||
|
|
|
|||
|
|
@ -1,6 +1,15 @@
|
|||
# Copyright (c) 2006-2007 The Regents of The University of Michigan
|
||||
# Copyright (c) 2012 ARM Limited
|
||||
# All rights reserved.
|
||||
#
|
||||
# The license below extends only to copyright in the software and shall
|
||||
# not be construed as granting a license to any other intellectual
|
||||
# property including but not limited to intellectual property relating
|
||||
# to a hardware implementation of the functionality of the software
|
||||
# licensed hereunder. You may use the software subject to the license
|
||||
# terms below provided that you ensure that this notice is replicated
|
||||
# unmodified and in its entirety in all distributions of the software,
|
||||
# modified or unmodified, in source code or in binary form.
|
||||
#
|
||||
# Redistribution and use in source and binary forms, with or without
|
||||
# modification, are permitted provided that the following conditions are
|
||||
# met: redistributions of source code must retain the above copyright
|
||||
|
|
@ -24,40 +33,10 @@
|
|||
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
#
|
||||
# Authors: Steve Reinhardt
|
||||
# Authors: Andreas Sandberg
|
||||
|
||||
import m5
|
||||
from m5.objects import *
|
||||
m5.util.addToPath('../configs/common')
|
||||
import FSConfig
|
||||
from Caches import *
|
||||
from alpha_generic import *
|
||||
|
||||
#cpu
|
||||
cpus = [ AtomicSimpleCPU(cpu_id=i) for i in xrange(2) ]
|
||||
#the system
|
||||
system = FSConfig.makeLinuxAlphaSystem('atomic')
|
||||
system.iocache = IOCache(clock = '1GHz', addr_ranges = [AddrRange('8GB')])
|
||||
system.iocache.cpu_side = system.iobus.master
|
||||
system.iocache.mem_side = system.membus.slave
|
||||
|
||||
system.cpu = cpus
|
||||
#create the l1/l2 bus
|
||||
system.toL2Bus = CoherentBus(clock = '2GHz')
|
||||
|
||||
#connect up the l2 cache
|
||||
system.l2c = L2Cache(clock = '2GHz', size='4MB', assoc=8)
|
||||
system.l2c.cpu_side = system.toL2Bus.master
|
||||
system.l2c.mem_side = system.membus.slave
|
||||
|
||||
#connect up the cpu and l1s
|
||||
for c in cpus:
|
||||
c.addPrivateSplitL1Caches(L1Cache(size = '32kB', assoc = 1),
|
||||
L1Cache(size = '32kB', assoc = 4))
|
||||
# create the interrupt controller
|
||||
c.createInterruptController()
|
||||
# connect cpu level-1 caches to shared level-2 cache
|
||||
c.connectAllPorts(system.toL2Bus, system.membus)
|
||||
c.clock = '2GHz'
|
||||
|
||||
root = Root(full_system=True, system=system)
|
||||
m5.ticks.setGlobalFrequency('1THz')
|
||||
root = LinuxAlphaFSSystem(mem_mode='atomic', cpu_class=AtomicSimpleCPU,
|
||||
num_cpus=2).create_root()
|
||||
|
|
|
|||
|
|
@ -1,6 +1,15 @@
|
|||
# Copyright (c) 2006-2007 The Regents of The University of Michigan
|
||||
# Copyright (c) 2012 ARM Limited
|
||||
# All rights reserved.
|
||||
#
|
||||
# The license below extends only to copyright in the software and shall
|
||||
# not be construed as granting a license to any other intellectual
|
||||
# property including but not limited to intellectual property relating
|
||||
# to a hardware implementation of the functionality of the software
|
||||
# licensed hereunder. You may use the software subject to the license
|
||||
# terms below provided that you ensure that this notice is replicated
|
||||
# unmodified and in its entirety in all distributions of the software,
|
||||
# modified or unmodified, in source code or in binary form.
|
||||
#
|
||||
# Redistribution and use in source and binary forms, with or without
|
||||
# modification, are permitted provided that the following conditions are
|
||||
# met: redistributions of source code must retain the above copyright
|
||||
|
|
@ -24,37 +33,10 @@
|
|||
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
#
|
||||
# Authors: Steve Reinhardt
|
||||
# Authors: Andreas Sandberg
|
||||
|
||||
import m5
|
||||
from m5.objects import *
|
||||
m5.util.addToPath('../configs/common')
|
||||
import FSConfig
|
||||
from Caches import *
|
||||
|
||||
#cpu
|
||||
cpu = AtomicSimpleCPU(cpu_id=0)
|
||||
#the system
|
||||
system = FSConfig.makeLinuxAlphaSystem('atomic')
|
||||
|
||||
system.cpu = cpu
|
||||
|
||||
#create the iocache
|
||||
system.iocache = IOCache(clock = '1GHz', addr_ranges = [AddrRange('8GB')])
|
||||
system.iocache.cpu_side = system.iobus.master
|
||||
system.iocache.mem_side = system.membus.slave
|
||||
|
||||
#connect up the cpu and caches
|
||||
cpu.addTwoLevelCacheHierarchy(L1Cache(size = '32kB', assoc = 1),
|
||||
L1Cache(size = '32kB', assoc = 4),
|
||||
L2Cache(size = '4MB', assoc = 8))
|
||||
# create the interrupt controller
|
||||
cpu.createInterruptController()
|
||||
# connect cpu and caches to the rest of the system
|
||||
cpu.connectAllPorts(system.membus)
|
||||
# set the cpu clock along with the caches and l1-l2 bus
|
||||
cpu.clock = '2GHz'
|
||||
|
||||
root = Root(full_system=True, system=system)
|
||||
m5.ticks.setGlobalFrequency('1THz')
|
||||
from alpha_generic import *
|
||||
|
||||
root = LinuxAlphaFSSystemUniprocessor(mem_mode='atomic',
|
||||
cpu_class=AtomicSimpleCPU).create_root()
|
||||
|
|
|
|||
|
|
@ -1,6 +1,15 @@
|
|||
# Copyright (c) 2006-2007 The Regents of The University of Michigan
|
||||
# Copyright (c) 2012 ARM Limited
|
||||
# All rights reserved.
|
||||
#
|
||||
# The license below extends only to copyright in the software and shall
|
||||
# not be construed as granting a license to any other intellectual
|
||||
# property including but not limited to intellectual property relating
|
||||
# to a hardware implementation of the functionality of the software
|
||||
# licensed hereunder. You may use the software subject to the license
|
||||
# terms below provided that you ensure that this notice is replicated
|
||||
# unmodified and in its entirety in all distributions of the software,
|
||||
# modified or unmodified, in source code or in binary form.
|
||||
#
|
||||
# Redistribution and use in source and binary forms, with or without
|
||||
# modification, are permitted provided that the following conditions are
|
||||
# met: redistributions of source code must retain the above copyright
|
||||
|
|
@ -24,42 +33,10 @@
|
|||
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
#
|
||||
# Authors: Steve Reinhardt
|
||||
# Authors: Andreas Sandberg
|
||||
|
||||
import m5
|
||||
from m5.objects import *
|
||||
m5.util.addToPath('../configs/common')
|
||||
import FSConfig
|
||||
from Caches import *
|
||||
|
||||
#cpu
|
||||
cpus = [ TimingSimpleCPU(cpu_id=i) for i in xrange(2) ]
|
||||
#the system
|
||||
system = FSConfig.makeLinuxAlphaSystem('timing')
|
||||
system.iocache = IOCache(clock = '1GHz', addr_ranges = [AddrRange('8GB')])
|
||||
system.iocache.cpu_side = system.iobus.master
|
||||
system.iocache.mem_side = system.membus.slave
|
||||
|
||||
system.cpu = cpus
|
||||
#create the l1/l2 bus
|
||||
system.toL2Bus = CoherentBus(clock = '2GHz')
|
||||
|
||||
#connect up the l2 cache
|
||||
system.l2c = L2Cache(clock = '2GHz', size='4MB', assoc=8)
|
||||
system.l2c.cpu_side = system.toL2Bus.master
|
||||
system.l2c.mem_side = system.membus.slave
|
||||
|
||||
#connect up the cpu and l1s
|
||||
for c in cpus:
|
||||
c.addPrivateSplitL1Caches(L1Cache(size = '32kB', assoc = 1),
|
||||
L1Cache(size = '32kB', assoc = 4))
|
||||
# create the interrupt controller
|
||||
c.createInterruptController()
|
||||
# connect cpu level-1 caches to shared level-2 cache
|
||||
c.connectAllPorts(system.toL2Bus, system.membus)
|
||||
c.clock = '2GHz'
|
||||
|
||||
root = Root(full_system=True, system=system)
|
||||
m5.ticks.setGlobalFrequency('1THz')
|
||||
|
||||
from alpha_generic import *
|
||||
|
||||
root = LinuxAlphaFSSystem(mem_mode='timing', cpu_class=TimingSimpleCPU,
|
||||
num_cpus=2).create_root()
|
||||
|
|
|
|||
|
|
@ -1,6 +1,15 @@
|
|||
# Copyright (c) 2006-2007 The Regents of The University of Michigan
|
||||
# Copyright (c) 2012 ARM Limited
|
||||
# All rights reserved.
|
||||
#
|
||||
# The license below extends only to copyright in the software and shall
|
||||
# not be construed as granting a license to any other intellectual
|
||||
# property including but not limited to intellectual property relating
|
||||
# to a hardware implementation of the functionality of the software
|
||||
# licensed hereunder. You may use the software subject to the license
|
||||
# terms below provided that you ensure that this notice is replicated
|
||||
# unmodified and in its entirety in all distributions of the software,
|
||||
# modified or unmodified, in source code or in binary form.
|
||||
#
|
||||
# Redistribution and use in source and binary forms, with or without
|
||||
# modification, are permitted provided that the following conditions are
|
||||
# met: redistributions of source code must retain the above copyright
|
||||
|
|
@ -24,37 +33,10 @@
|
|||
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
#
|
||||
# Authors: Steve Reinhardt
|
||||
# Authors: Andreas Sandberg
|
||||
|
||||
import m5
|
||||
from m5.objects import *
|
||||
m5.util.addToPath('../configs/common')
|
||||
import FSConfig
|
||||
from Caches import *
|
||||
|
||||
#cpu
|
||||
cpu = TimingSimpleCPU(cpu_id=0)
|
||||
#the system
|
||||
system = FSConfig.makeLinuxAlphaSystem('timing')
|
||||
|
||||
system.cpu = cpu
|
||||
|
||||
#create the iocache
|
||||
system.iocache = IOCache(clock = '1GHz', addr_ranges = [AddrRange('8GB')])
|
||||
system.iocache.cpu_side = system.iobus.master
|
||||
system.iocache.mem_side = system.membus.slave
|
||||
|
||||
#connect up the cpu and caches
|
||||
cpu.addTwoLevelCacheHierarchy(L1Cache(size = '32kB', assoc = 1),
|
||||
L1Cache(size = '32kB', assoc = 4),
|
||||
L2Cache(size = '4MB', assoc = 8))
|
||||
# create the interrupt controller
|
||||
cpu.createInterruptController()
|
||||
# connect cpu and caches to the rest of the system
|
||||
cpu.connectAllPorts(system.membus)
|
||||
# set the cpu clock along with the caches and l1-l2 bus
|
||||
cpu.clock = '2GHz'
|
||||
|
||||
root = Root(full_system=True, system=system)
|
||||
m5.ticks.setGlobalFrequency('1THz')
|
||||
from alpha_generic import *
|
||||
|
||||
root = LinuxAlphaFSSystemUniprocessor(mem_mode='timing',
|
||||
cpu_class=TimingSimpleCPU).create_root()
|
||||
|
|
|
|||
108
tests/configs/x86_generic.py
Normal file
108
tests/configs/x86_generic.py
Normal file
|
|
@ -0,0 +1,108 @@
|
|||
# Copyright (c) 2012 ARM Limited
|
||||
# All rights reserved.
|
||||
#
|
||||
# The license below extends only to copyright in the software and shall
|
||||
# not be construed as granting a license to any other intellectual
|
||||
# property including but not limited to intellectual property relating
|
||||
# to a hardware implementation of the functionality of the software
|
||||
# licensed hereunder. You may use the software subject to the license
|
||||
# terms below provided that you ensure that this notice is replicated
|
||||
# unmodified and in its entirety in all distributions of the software,
|
||||
# modified or unmodified, in source code or in binary form.
|
||||
#
|
||||
# Redistribution and use in source and binary forms, with or without
|
||||
# modification, are permitted provided that the following conditions are
|
||||
# met: redistributions of source code must retain the above copyright
|
||||
# notice, this list of conditions and the following disclaimer;
|
||||
# redistributions in binary form must reproduce the above copyright
|
||||
# notice, this list of conditions and the following disclaimer in the
|
||||
# documentation and/or other materials provided with the distribution;
|
||||
# neither the name of the copyright holders nor the names of its
|
||||
# contributors may be used to endorse or promote products derived from
|
||||
# this software without specific prior written permission.
|
||||
#
|
||||
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
#
|
||||
# Authors: Andreas Sandberg
|
||||
|
||||
from abc import ABCMeta, abstractmethod
|
||||
import m5
|
||||
from m5.objects import *
|
||||
from m5.proxy import *
|
||||
m5.util.addToPath('../configs/common')
|
||||
from Benchmarks import SysConfig
|
||||
import FSConfig
|
||||
from Caches import *
|
||||
from base_config import *
|
||||
|
||||
class LinuxX86SystemBuilder(object):
|
||||
"""Mix-in that implements create_system.
|
||||
|
||||
This mix-in is intended as a convenient way of adding an
|
||||
X86-specific create_system method to a class deriving from one of
|
||||
the generic base systems.
|
||||
"""
|
||||
def __init__(self):
|
||||
pass
|
||||
|
||||
def create_system(self):
|
||||
mdesc = SysConfig(disk = 'linux-x86.img')
|
||||
system = FSConfig.makeLinuxX86System(self.mem_mode,
|
||||
numCPUs=self.num_cpus,
|
||||
mdesc=mdesc)
|
||||
system.kernel = FSConfig.binary('x86_64-vmlinux-2.6.22.9')
|
||||
|
||||
self.init_system(system)
|
||||
return system
|
||||
|
||||
class LinuxX86FSSystem(LinuxX86SystemBuilder,
|
||||
BaseFSSystem):
|
||||
"""Basic X86 full system builder."""
|
||||
|
||||
def __init__(self, **kwargs):
|
||||
"""Initialize an X86 system that supports full system simulation.
|
||||
|
||||
Note: Keyword arguments that are not listed below will be
|
||||
passed to the BaseFSSystem.
|
||||
|
||||
Keyword Arguments:
|
||||
machine_type -- String describing the platform to simulate
|
||||
"""
|
||||
BaseSystem.__init__(self, **kwargs)
|
||||
LinuxX86SystemBuilder.__init__(self)
|
||||
|
||||
def create_caches_private(self, cpu):
|
||||
cpu.addPrivateSplitL1Caches(L1Cache(size='32kB', assoc=1),
|
||||
L1Cache(size='32kB', assoc=4),
|
||||
PageTableWalkerCache(),
|
||||
PageTableWalkerCache())
|
||||
|
||||
class LinuxX86FSSystemUniprocessor(LinuxX86SystemBuilder,
|
||||
BaseFSSystemUniprocessor):
|
||||
"""Basic X86 full system builder for uniprocessor systems.
|
||||
|
||||
Note: This class is a specialization of the X86FSSystem and is
|
||||
only really needed to provide backwards compatibility for existing
|
||||
test cases.
|
||||
"""
|
||||
|
||||
def __init__(self, **kwargs):
|
||||
BaseFSSystemUniprocessor.__init__(self, **kwargs)
|
||||
LinuxX86SystemBuilder.__init__(self)
|
||||
|
||||
def create_caches_private(self, cpu):
|
||||
cpu.addTwoLevelCacheHierarchy(L1Cache(size='32kB', assoc=1),
|
||||
L1Cache(size='32kB', assoc=4),
|
||||
L2Cache(size='4MB', assoc=8),
|
||||
PageTableWalkerCache(),
|
||||
PageTableWalkerCache())
|
||||
Loading…
Reference in a new issue