Initial changes to get O3 working with SPARC
src/arch/sparc/process.cc: MachineBytes doesn't exist any more. src/arch/sparc/regfile.cc: Add in the miscRegFile for good measure. src/cpu/o3/isa_specific.hh: Add in a section for SPARC src/cpu/o3/sparc/cpu.cc: src/cpu/o3/sparc/cpu.hh: src/cpu/o3/sparc/cpu_builder.cc: src/cpu/o3/sparc/cpu_impl.hh: src/cpu/o3/sparc/dyn_inst.cc: src/cpu/o3/sparc/dyn_inst.hh: src/cpu/o3/sparc/dyn_inst_impl.hh: src/cpu/o3/sparc/impl.hh: src/cpu/o3/sparc/params.hh: src/cpu/o3/sparc/thread_context.cc: src/cpu/o3/sparc/thread_context.hh: Sparc version of this file. --HG-- extra : convert_revision : 34bb5218f802d0a1328132a518cdd769fb59b6a4
This commit is contained in:
parent
5f446e36b6
commit
f2daf210f1
14 changed files with 1728 additions and 2 deletions
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@ -32,6 +32,7 @@
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#include "arch/sparc/asi.hh"
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#include "arch/sparc/asi.hh"
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#include "arch/sparc/isa_traits.hh"
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#include "arch/sparc/isa_traits.hh"
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#include "arch/sparc/process.hh"
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#include "arch/sparc/process.hh"
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#include "arch/sparc/types.hh"
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#include "base/loader/object_file.hh"
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#include "base/loader/object_file.hh"
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#include "base/loader/elf_object.hh"
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#include "base/loader/elf_object.hh"
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#include "base/misc.hh"
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#include "base/misc.hh"
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@ -77,7 +78,7 @@ SparcLiveProcess::SparcLiveProcess(const std::string &nm, ObjectFile *objFile,
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void
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void
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SparcLiveProcess::startup()
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SparcLiveProcess::startup()
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{
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{
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argsInit(MachineBytes, VMPageSize);
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argsInit(sizeof(IntReg), VMPageSize);
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//From the SPARC ABI
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//From the SPARC ABI
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@ -70,8 +70,9 @@ void RegFile::setNextNPC(Addr val)
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void RegFile::clear()
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void RegFile::clear()
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{
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{
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intRegFile.clear();
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floatRegFile.clear();
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floatRegFile.clear();
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intRegFile.clear();
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miscRegFile.clear();
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}
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}
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MiscReg RegFile::readMiscReg(int miscReg)
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MiscReg RegFile::readMiscReg(int miscReg)
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@ -40,6 +40,11 @@
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#include "cpu/o3/mips/impl.hh"
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#include "cpu/o3/mips/impl.hh"
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#include "cpu/o3/mips/params.hh"
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#include "cpu/o3/mips/params.hh"
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#include "cpu/o3/mips/dyn_inst.hh"
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#include "cpu/o3/mips/dyn_inst.hh"
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#elif THE_ISA == SPARC_ISA
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#include "cpu/o3/sparc/cpu.hh"
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#include "cpu/o3/sparc/impl.hh"
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#include "cpu/o3/sparc/params.hh"
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#include "cpu/o3/sparc/dyn_inst.hh"
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#else
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#else
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#error "ISA-specific header files O3CPU not defined ISA"
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#error "ISA-specific header files O3CPU not defined ISA"
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#endif
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#endif
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38
src/cpu/o3/sparc/cpu.cc
Normal file
38
src/cpu/o3/sparc/cpu.cc
Normal file
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@ -0,0 +1,38 @@
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/*
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* Copyright (c) 2004-2005 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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|
* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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|
* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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|
*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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|
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Gabe Black
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*/
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#include "cpu/o3/sparc/impl.hh"
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#include "cpu/o3/sparc/cpu_impl.hh"
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#include "cpu/o3/sparc/dyn_inst.hh"
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// Force instantiation of SparcO3CPU for all the implementations that are
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// needed. Consider merging this and sparc_dyn_inst.cc, and maybe all
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// classes that depend on a certain impl, into one file (sparc_impl.cc?).
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template class SparcO3CPU<SparcSimpleImpl>;
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207
src/cpu/o3/sparc/cpu.hh
Normal file
207
src/cpu/o3/sparc/cpu.hh
Normal file
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@ -0,0 +1,207 @@
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/*
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* Copyright (c) 2004-2006 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Kevin Lim
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*/
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#ifndef __CPU_O3_SPARC_CPU_HH__
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#define __CPU_O3_SPARC_CPU_HH__
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#include "arch/sparc/regfile.hh"
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#include "arch/sparc/types.hh"
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#include "cpu/thread_context.hh"
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#include "cpu/o3/cpu.hh"
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#include "sim/byteswap.hh"
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namespace TheISA
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{
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class ITB;
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class DTB;
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}
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class EndQuiesceEvent;
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namespace Kernel {
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class Statistics;
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};
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class TranslatingPort;
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/**
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* SparcO3CPU class. Derives from the FullO3CPU class, and
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* implements all ISA and implementation specific functions of the
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* CPU. This is the CPU class that is used for the SimObjects, and is
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* what is given to the DynInsts. Most of its state exists in the
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* FullO3CPU; the state is has is mainly for ISA specific
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* functionality.
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*/
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template <class Impl>
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class SparcO3CPU : public FullO3CPU<Impl>
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{
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protected:
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typedef TheISA::IntReg IntReg;
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typedef TheISA::FloatReg FloatReg;
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typedef TheISA::FloatRegBits FloatRegBits;
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typedef TheISA::MiscReg MiscReg;
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typedef TheISA::RegFile RegFile;
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typedef TheISA::MiscRegFile MiscRegFile;
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public:
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typedef O3ThreadState<Impl> ImplState;
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typedef O3ThreadState<Impl> Thread;
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typedef typename Impl::Params Params;
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/** Constructs an AlphaO3CPU with the given parameters. */
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SparcO3CPU(Params *params);
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#if FULL_SYSTEM
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/** ITB pointer. */
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SparcISA::ITB *itb;
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/** DTB pointer. */
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SparcISA::DTB *dtb;
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#endif
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/** Registers statistics. */
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void regStats();
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#if FULL_SYSTEM
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/** Translates instruction requestion. */
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Fault translateInstReq(RequestPtr &req, Thread *thread)
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{
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return itb->translate(req, thread->getTC());
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}
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/** Translates data read request. */
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Fault translateDataReadReq(RequestPtr &req, Thread *thread)
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{
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return dtb->translate(req, thread->getTC(), false);
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}
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/** Translates data write request. */
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Fault translateDataWriteReq(RequestPtr &req, Thread *thread)
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{
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return dtb->translate(req, thread->getTC(), true);
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}
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#else
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/** Translates instruction requestion in syscall emulation mode. */
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Fault translateInstReq(RequestPtr &req, Thread *thread)
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{
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return thread->getProcessPtr()->pTable->translate(req);
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}
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/** Translates data read request in syscall emulation mode. */
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Fault translateDataReadReq(RequestPtr &req, Thread *thread)
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{
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return thread->getProcessPtr()->pTable->translate(req);
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}
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/** Translates data write request in syscall emulation mode. */
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Fault translateDataWriteReq(RequestPtr &req, Thread *thread)
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{
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return thread->getProcessPtr()->pTable->translate(req);
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}
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#endif
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/** Reads a miscellaneous register. */
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MiscReg readMiscReg(int misc_reg, unsigned tid);
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/** Reads a misc. register, including any side effects the read
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* might have as defined by the architecture.
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*/
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MiscReg readMiscRegWithEffect(int misc_reg, unsigned tid);
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/** Sets a miscellaneous register. */
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void setMiscReg(int misc_reg, const MiscReg &val, unsigned tid);
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/** Sets a misc. register, including any side effects the write
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* might have as defined by the architecture.
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*/
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void setMiscRegWithEffect(int misc_reg, const MiscReg &val, unsigned tid);
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/** Initiates a squash of all in-flight instructions for a given
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* thread. The source of the squash is an external update of
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* state through the TC.
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*/
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void squashFromTC(unsigned tid);
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#if FULL_SYSTEM
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/** Posts an interrupt. */
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void post_interrupt(int int_num, int index);
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/** HW return from error interrupt. */
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Fault hwrei(unsigned tid);
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bool simPalCheck(int palFunc, unsigned tid);
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/** Returns the Fault for any valid interrupt. */
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Fault getInterrupts();
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/** Processes any an interrupt fault. */
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void processInterrupts(Fault interrupt);
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/** Halts the CPU. */
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void halt() { panic("Halt not implemented!\n"); }
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#endif
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/** Traps to handle given fault. */
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void trap(Fault fault, unsigned tid);
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#if !FULL_SYSTEM
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/** Executes a syscall.
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* @todo: Determine if this needs to be virtual.
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*/
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void syscall(int64_t callnum, int tid);
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/** Gets a syscall argument. */
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IntReg getSyscallArg(int i, int tid);
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/** Used to shift args for indirect syscall. */
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void setSyscallArg(int i, IntReg val, int tid);
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/** Sets the return value of a syscall. */
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void setSyscallReturn(SyscallReturn return_value, int tid);
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#endif
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/** CPU read function, forwards read to LSQ. */
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template <class T>
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Fault read(RequestPtr &req, T &data, int load_idx)
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{
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return this->iew.ldstQueue.read(req, data, load_idx);
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}
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/** CPU write function, forwards write to LSQ. */
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template <class T>
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Fault write(RequestPtr &req, T &data, int store_idx)
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{
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return this->iew.ldstQueue.write(req, data, store_idx);
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}
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Addr lockAddr;
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/** Temporary fix for the lock flag, works in the UP case. */
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bool lockFlag;
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};
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#endif // __CPU_O3_ALPHA_CPU_HH__
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433
src/cpu/o3/sparc/cpu_builder.cc
Normal file
433
src/cpu/o3/sparc/cpu_builder.cc
Normal file
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@ -0,0 +1,433 @@
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/*
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* Copyright (c) 2004-2006 The Regents of The University of Michigan
|
||||||
|
* All rights reserved.
|
||||||
|
*
|
||||||
|
* Redistribution and use in source and binary forms, with or without
|
||||||
|
* modification, are permitted provided that the following conditions are
|
||||||
|
* met: redistributions of source code must retain the above copyright
|
||||||
|
* notice, this list of conditions and the following disclaimer;
|
||||||
|
* redistributions in binary form must reproduce the above copyright
|
||||||
|
* notice, this list of conditions and the following disclaimer in the
|
||||||
|
* documentation and/or other materials provided with the distribution;
|
||||||
|
* neither the name of the copyright holders nor the names of its
|
||||||
|
* contributors may be used to endorse or promote products derived from
|
||||||
|
* this software without specific prior written permission.
|
||||||
|
*
|
||||||
|
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||||
|
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||||
|
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||||
|
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||||
|
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||||
|
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||||
|
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||||
|
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||||
|
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||||
|
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||||
|
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||||
|
*
|
||||||
|
* Authors: Gabe Black
|
||||||
|
*/
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#include <string>
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#include "cpu/base.hh"
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#include "cpu/o3/sparc/cpu.hh"
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#include "cpu/o3/sparc/impl.hh"
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#include "cpu/o3/sparc/params.hh"
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#include "cpu/o3/fu_pool.hh"
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#include "sim/builder.hh"
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class DerivO3CPU : public SparcO3CPU<SparcSimpleImpl>
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{
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public:
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DerivO3CPU(SparcSimpleParams *p)
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: SparcO3CPU<SparcSimpleImpl>(p)
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{ }
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};
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BEGIN_DECLARE_SIM_OBJECT_PARAMS(DerivO3CPU)
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Param<int> clock;
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Param<int> phase;
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Param<int> numThreads;
|
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Param<int> activity;
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#if FULL_SYSTEM
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SimObjectParam<System *> system;
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Param<int> cpu_id;
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SimObjectParam<AlphaISA::ITB *> itb;
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SimObjectParam<AlphaISA::DTB *> dtb;
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Param<Tick> profile;
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Param<bool> do_quiesce;
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Param<bool> do_checkpoint_insts;
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Param<bool> do_statistics_insts;
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#else
|
||||||
|
SimObjectVectorParam<Process *> workload;
|
||||||
|
#endif // FULL_SYSTEM
|
||||||
|
|
||||||
|
SimObjectParam<BaseCPU *> checker;
|
||||||
|
|
||||||
|
Param<Counter> max_insts_any_thread;
|
||||||
|
Param<Counter> max_insts_all_threads;
|
||||||
|
Param<Counter> max_loads_any_thread;
|
||||||
|
Param<Counter> max_loads_all_threads;
|
||||||
|
Param<Tick> progress_interval;
|
||||||
|
|
||||||
|
Param<unsigned> cachePorts;
|
||||||
|
|
||||||
|
Param<unsigned> decodeToFetchDelay;
|
||||||
|
Param<unsigned> renameToFetchDelay;
|
||||||
|
Param<unsigned> iewToFetchDelay;
|
||||||
|
Param<unsigned> commitToFetchDelay;
|
||||||
|
Param<unsigned> fetchWidth;
|
||||||
|
|
||||||
|
Param<unsigned> renameToDecodeDelay;
|
||||||
|
Param<unsigned> iewToDecodeDelay;
|
||||||
|
Param<unsigned> commitToDecodeDelay;
|
||||||
|
Param<unsigned> fetchToDecodeDelay;
|
||||||
|
Param<unsigned> decodeWidth;
|
||||||
|
|
||||||
|
Param<unsigned> iewToRenameDelay;
|
||||||
|
Param<unsigned> commitToRenameDelay;
|
||||||
|
Param<unsigned> decodeToRenameDelay;
|
||||||
|
Param<unsigned> renameWidth;
|
||||||
|
|
||||||
|
Param<unsigned> commitToIEWDelay;
|
||||||
|
Param<unsigned> renameToIEWDelay;
|
||||||
|
Param<unsigned> issueToExecuteDelay;
|
||||||
|
Param<unsigned> dispatchWidth;
|
||||||
|
Param<unsigned> issueWidth;
|
||||||
|
Param<unsigned> wbWidth;
|
||||||
|
Param<unsigned> wbDepth;
|
||||||
|
SimObjectParam<FUPool *> fuPool;
|
||||||
|
|
||||||
|
Param<unsigned> iewToCommitDelay;
|
||||||
|
Param<unsigned> renameToROBDelay;
|
||||||
|
Param<unsigned> commitWidth;
|
||||||
|
Param<unsigned> squashWidth;
|
||||||
|
Param<Tick> trapLatency;
|
||||||
|
|
||||||
|
Param<unsigned> backComSize;
|
||||||
|
Param<unsigned> forwardComSize;
|
||||||
|
|
||||||
|
Param<std::string> predType;
|
||||||
|
Param<unsigned> localPredictorSize;
|
||||||
|
Param<unsigned> localCtrBits;
|
||||||
|
Param<unsigned> localHistoryTableSize;
|
||||||
|
Param<unsigned> localHistoryBits;
|
||||||
|
Param<unsigned> globalPredictorSize;
|
||||||
|
Param<unsigned> globalCtrBits;
|
||||||
|
Param<unsigned> globalHistoryBits;
|
||||||
|
Param<unsigned> choicePredictorSize;
|
||||||
|
Param<unsigned> choiceCtrBits;
|
||||||
|
|
||||||
|
Param<unsigned> BTBEntries;
|
||||||
|
Param<unsigned> BTBTagSize;
|
||||||
|
|
||||||
|
Param<unsigned> RASSize;
|
||||||
|
|
||||||
|
Param<unsigned> LQEntries;
|
||||||
|
Param<unsigned> SQEntries;
|
||||||
|
Param<unsigned> LFSTSize;
|
||||||
|
Param<unsigned> SSITSize;
|
||||||
|
|
||||||
|
Param<unsigned> numPhysIntRegs;
|
||||||
|
Param<unsigned> numPhysFloatRegs;
|
||||||
|
Param<unsigned> numIQEntries;
|
||||||
|
Param<unsigned> numROBEntries;
|
||||||
|
|
||||||
|
Param<unsigned> smtNumFetchingThreads;
|
||||||
|
Param<std::string> smtFetchPolicy;
|
||||||
|
Param<std::string> smtLSQPolicy;
|
||||||
|
Param<unsigned> smtLSQThreshold;
|
||||||
|
Param<std::string> smtIQPolicy;
|
||||||
|
Param<unsigned> smtIQThreshold;
|
||||||
|
Param<std::string> smtROBPolicy;
|
||||||
|
Param<unsigned> smtROBThreshold;
|
||||||
|
Param<std::string> smtCommitPolicy;
|
||||||
|
|
||||||
|
Param<unsigned> instShiftAmt;
|
||||||
|
|
||||||
|
Param<bool> defer_registration;
|
||||||
|
|
||||||
|
Param<bool> function_trace;
|
||||||
|
Param<Tick> function_trace_start;
|
||||||
|
|
||||||
|
END_DECLARE_SIM_OBJECT_PARAMS(DerivO3CPU)
|
||||||
|
|
||||||
|
BEGIN_INIT_SIM_OBJECT_PARAMS(DerivO3CPU)
|
||||||
|
|
||||||
|
INIT_PARAM(clock, "clock speed"),
|
||||||
|
INIT_PARAM_DFLT(phase, "clock phase", 0),
|
||||||
|
INIT_PARAM(numThreads, "number of HW thread contexts"),
|
||||||
|
INIT_PARAM_DFLT(activity, "Initial activity count", 0),
|
||||||
|
|
||||||
|
#if FULL_SYSTEM
|
||||||
|
INIT_PARAM(system, "System object"),
|
||||||
|
INIT_PARAM(cpu_id, "processor ID"),
|
||||||
|
INIT_PARAM(itb, "Instruction translation buffer"),
|
||||||
|
INIT_PARAM(dtb, "Data translation buffer"),
|
||||||
|
INIT_PARAM(profile, ""),
|
||||||
|
|
||||||
|
INIT_PARAM(do_quiesce, ""),
|
||||||
|
INIT_PARAM(do_checkpoint_insts, ""),
|
||||||
|
INIT_PARAM(do_statistics_insts, ""),
|
||||||
|
#else
|
||||||
|
INIT_PARAM(workload, "Processes to run"),
|
||||||
|
#endif // FULL_SYSTEM
|
||||||
|
|
||||||
|
INIT_PARAM_DFLT(checker, "Checker CPU", NULL),
|
||||||
|
|
||||||
|
INIT_PARAM_DFLT(max_insts_any_thread,
|
||||||
|
"Terminate when any thread reaches this inst count",
|
||||||
|
0),
|
||||||
|
INIT_PARAM_DFLT(max_insts_all_threads,
|
||||||
|
"Terminate when all threads have reached"
|
||||||
|
"this inst count",
|
||||||
|
0),
|
||||||
|
INIT_PARAM_DFLT(max_loads_any_thread,
|
||||||
|
"Terminate when any thread reaches this load count",
|
||||||
|
0),
|
||||||
|
INIT_PARAM_DFLT(max_loads_all_threads,
|
||||||
|
"Terminate when all threads have reached this load"
|
||||||
|
"count",
|
||||||
|
0),
|
||||||
|
INIT_PARAM_DFLT(progress_interval, "Progress interval", 0),
|
||||||
|
|
||||||
|
INIT_PARAM_DFLT(cachePorts, "Cache Ports", 200),
|
||||||
|
|
||||||
|
INIT_PARAM(decodeToFetchDelay, "Decode to fetch delay"),
|
||||||
|
INIT_PARAM(renameToFetchDelay, "Rename to fetch delay"),
|
||||||
|
INIT_PARAM(iewToFetchDelay, "Issue/Execute/Writeback to fetch"
|
||||||
|
"delay"),
|
||||||
|
INIT_PARAM(commitToFetchDelay, "Commit to fetch delay"),
|
||||||
|
INIT_PARAM(fetchWidth, "Fetch width"),
|
||||||
|
INIT_PARAM(renameToDecodeDelay, "Rename to decode delay"),
|
||||||
|
INIT_PARAM(iewToDecodeDelay, "Issue/Execute/Writeback to decode"
|
||||||
|
"delay"),
|
||||||
|
INIT_PARAM(commitToDecodeDelay, "Commit to decode delay"),
|
||||||
|
INIT_PARAM(fetchToDecodeDelay, "Fetch to decode delay"),
|
||||||
|
INIT_PARAM(decodeWidth, "Decode width"),
|
||||||
|
|
||||||
|
INIT_PARAM(iewToRenameDelay, "Issue/Execute/Writeback to rename"
|
||||||
|
"delay"),
|
||||||
|
INIT_PARAM(commitToRenameDelay, "Commit to rename delay"),
|
||||||
|
INIT_PARAM(decodeToRenameDelay, "Decode to rename delay"),
|
||||||
|
INIT_PARAM(renameWidth, "Rename width"),
|
||||||
|
|
||||||
|
INIT_PARAM(commitToIEWDelay, "Commit to "
|
||||||
|
"Issue/Execute/Writeback delay"),
|
||||||
|
INIT_PARAM(renameToIEWDelay, "Rename to "
|
||||||
|
"Issue/Execute/Writeback delay"),
|
||||||
|
INIT_PARAM(issueToExecuteDelay, "Issue to execute delay (internal"
|
||||||
|
"to the IEW stage)"),
|
||||||
|
INIT_PARAM(dispatchWidth, "Dispatch width"),
|
||||||
|
INIT_PARAM(issueWidth, "Issue width"),
|
||||||
|
INIT_PARAM(wbWidth, "Writeback width"),
|
||||||
|
INIT_PARAM(wbDepth, "Writeback depth (number of cycles it can buffer)"),
|
||||||
|
INIT_PARAM_DFLT(fuPool, "Functional unit pool", NULL),
|
||||||
|
|
||||||
|
INIT_PARAM(iewToCommitDelay, "Issue/Execute/Writeback to commit "
|
||||||
|
"delay"),
|
||||||
|
INIT_PARAM(renameToROBDelay, "Rename to reorder buffer delay"),
|
||||||
|
INIT_PARAM(commitWidth, "Commit width"),
|
||||||
|
INIT_PARAM(squashWidth, "Squash width"),
|
||||||
|
INIT_PARAM_DFLT(trapLatency, "Number of cycles before the trap is handled", 6),
|
||||||
|
|
||||||
|
INIT_PARAM(backComSize, "Time buffer size for backwards communication"),
|
||||||
|
INIT_PARAM(forwardComSize, "Time buffer size for forward communication"),
|
||||||
|
|
||||||
|
INIT_PARAM(predType, "Type of branch predictor ('local', 'tournament')"),
|
||||||
|
INIT_PARAM(localPredictorSize, "Size of local predictor"),
|
||||||
|
INIT_PARAM(localCtrBits, "Bits per counter"),
|
||||||
|
INIT_PARAM(localHistoryTableSize, "Size of local history table"),
|
||||||
|
INIT_PARAM(localHistoryBits, "Bits for the local history"),
|
||||||
|
INIT_PARAM(globalPredictorSize, "Size of global predictor"),
|
||||||
|
INIT_PARAM(globalCtrBits, "Bits per counter"),
|
||||||
|
INIT_PARAM(globalHistoryBits, "Bits of history"),
|
||||||
|
INIT_PARAM(choicePredictorSize, "Size of choice predictor"),
|
||||||
|
INIT_PARAM(choiceCtrBits, "Bits of choice counters"),
|
||||||
|
|
||||||
|
INIT_PARAM(BTBEntries, "Number of BTB entries"),
|
||||||
|
INIT_PARAM(BTBTagSize, "Size of the BTB tags, in bits"),
|
||||||
|
|
||||||
|
INIT_PARAM(RASSize, "RAS size"),
|
||||||
|
|
||||||
|
INIT_PARAM(LQEntries, "Number of load queue entries"),
|
||||||
|
INIT_PARAM(SQEntries, "Number of store queue entries"),
|
||||||
|
INIT_PARAM(LFSTSize, "Last fetched store table size"),
|
||||||
|
INIT_PARAM(SSITSize, "Store set ID table size"),
|
||||||
|
|
||||||
|
INIT_PARAM(numPhysIntRegs, "Number of physical integer registers"),
|
||||||
|
INIT_PARAM(numPhysFloatRegs, "Number of physical floating point "
|
||||||
|
"registers"),
|
||||||
|
INIT_PARAM(numIQEntries, "Number of instruction queue entries"),
|
||||||
|
INIT_PARAM(numROBEntries, "Number of reorder buffer entries"),
|
||||||
|
|
||||||
|
INIT_PARAM_DFLT(smtNumFetchingThreads, "SMT Number of Fetching Threads", 1),
|
||||||
|
INIT_PARAM_DFLT(smtFetchPolicy, "SMT Fetch Policy", "SingleThread"),
|
||||||
|
INIT_PARAM_DFLT(smtLSQPolicy, "SMT LSQ Sharing Policy", "Partitioned"),
|
||||||
|
INIT_PARAM_DFLT(smtLSQThreshold,"SMT LSQ Threshold", 100),
|
||||||
|
INIT_PARAM_DFLT(smtIQPolicy, "SMT IQ Policy", "Partitioned"),
|
||||||
|
INIT_PARAM_DFLT(smtIQThreshold, "SMT IQ Threshold", 100),
|
||||||
|
INIT_PARAM_DFLT(smtROBPolicy, "SMT ROB Sharing Policy", "Partitioned"),
|
||||||
|
INIT_PARAM_DFLT(smtROBThreshold,"SMT ROB Threshold", 100),
|
||||||
|
INIT_PARAM_DFLT(smtCommitPolicy,"SMT Commit Fetch Policy", "RoundRobin"),
|
||||||
|
|
||||||
|
INIT_PARAM(instShiftAmt, "Number of bits to shift instructions by"),
|
||||||
|
INIT_PARAM(defer_registration, "defer system registration (for sampling)"),
|
||||||
|
|
||||||
|
INIT_PARAM(function_trace, "Enable function trace"),
|
||||||
|
INIT_PARAM(function_trace_start, "Cycle to start function trace")
|
||||||
|
|
||||||
|
END_INIT_SIM_OBJECT_PARAMS(DerivO3CPU)
|
||||||
|
|
||||||
|
CREATE_SIM_OBJECT(DerivO3CPU)
|
||||||
|
{
|
||||||
|
DerivO3CPU *cpu;
|
||||||
|
|
||||||
|
#if FULL_SYSTEM
|
||||||
|
// Full-system only supports a single thread for the moment.
|
||||||
|
int actual_num_threads = 1;
|
||||||
|
#else
|
||||||
|
// In non-full-system mode, we infer the number of threads from
|
||||||
|
// the workload if it's not explicitly specified.
|
||||||
|
int actual_num_threads =
|
||||||
|
(numThreads.isValid() && numThreads >= workload.size()) ?
|
||||||
|
numThreads : workload.size();
|
||||||
|
|
||||||
|
if (workload.size() == 0) {
|
||||||
|
fatal("Must specify at least one workload!");
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
SparcSimpleParams *params = new SparcSimpleParams;
|
||||||
|
|
||||||
|
params->clock = clock;
|
||||||
|
|
||||||
|
params->name = getInstanceName();
|
||||||
|
params->numberOfThreads = actual_num_threads;
|
||||||
|
params->activity = activity;
|
||||||
|
|
||||||
|
#if FULL_SYSTEM
|
||||||
|
params->system = system;
|
||||||
|
params->cpu_id = cpu_id;
|
||||||
|
params->itb = itb;
|
||||||
|
params->dtb = dtb;
|
||||||
|
params->profile = profile;
|
||||||
|
|
||||||
|
params->do_quiesce = do_quiesce;
|
||||||
|
params->do_checkpoint_insts = do_checkpoint_insts;
|
||||||
|
params->do_statistics_insts = do_statistics_insts;
|
||||||
|
#else
|
||||||
|
params->workload = workload;
|
||||||
|
#endif // FULL_SYSTEM
|
||||||
|
|
||||||
|
params->checker = checker;
|
||||||
|
|
||||||
|
params->max_insts_any_thread = max_insts_any_thread;
|
||||||
|
params->max_insts_all_threads = max_insts_all_threads;
|
||||||
|
params->max_loads_any_thread = max_loads_any_thread;
|
||||||
|
params->max_loads_all_threads = max_loads_all_threads;
|
||||||
|
params->progress_interval = progress_interval;
|
||||||
|
|
||||||
|
//
|
||||||
|
// Caches
|
||||||
|
//
|
||||||
|
params->cachePorts = cachePorts;
|
||||||
|
|
||||||
|
params->decodeToFetchDelay = decodeToFetchDelay;
|
||||||
|
params->renameToFetchDelay = renameToFetchDelay;
|
||||||
|
params->iewToFetchDelay = iewToFetchDelay;
|
||||||
|
params->commitToFetchDelay = commitToFetchDelay;
|
||||||
|
params->fetchWidth = fetchWidth;
|
||||||
|
|
||||||
|
params->renameToDecodeDelay = renameToDecodeDelay;
|
||||||
|
params->iewToDecodeDelay = iewToDecodeDelay;
|
||||||
|
params->commitToDecodeDelay = commitToDecodeDelay;
|
||||||
|
params->fetchToDecodeDelay = fetchToDecodeDelay;
|
||||||
|
params->decodeWidth = decodeWidth;
|
||||||
|
|
||||||
|
params->iewToRenameDelay = iewToRenameDelay;
|
||||||
|
params->commitToRenameDelay = commitToRenameDelay;
|
||||||
|
params->decodeToRenameDelay = decodeToRenameDelay;
|
||||||
|
params->renameWidth = renameWidth;
|
||||||
|
|
||||||
|
params->commitToIEWDelay = commitToIEWDelay;
|
||||||
|
params->renameToIEWDelay = renameToIEWDelay;
|
||||||
|
params->issueToExecuteDelay = issueToExecuteDelay;
|
||||||
|
params->dispatchWidth = dispatchWidth;
|
||||||
|
params->issueWidth = issueWidth;
|
||||||
|
params->wbWidth = wbWidth;
|
||||||
|
params->wbDepth = wbDepth;
|
||||||
|
params->fuPool = fuPool;
|
||||||
|
|
||||||
|
params->iewToCommitDelay = iewToCommitDelay;
|
||||||
|
params->renameToROBDelay = renameToROBDelay;
|
||||||
|
params->commitWidth = commitWidth;
|
||||||
|
params->squashWidth = squashWidth;
|
||||||
|
params->trapLatency = trapLatency;
|
||||||
|
|
||||||
|
params->backComSize = backComSize;
|
||||||
|
params->forwardComSize = forwardComSize;
|
||||||
|
|
||||||
|
params->predType = predType;
|
||||||
|
params->localPredictorSize = localPredictorSize;
|
||||||
|
params->localCtrBits = localCtrBits;
|
||||||
|
params->localHistoryTableSize = localHistoryTableSize;
|
||||||
|
params->localHistoryBits = localHistoryBits;
|
||||||
|
params->globalPredictorSize = globalPredictorSize;
|
||||||
|
params->globalCtrBits = globalCtrBits;
|
||||||
|
params->globalHistoryBits = globalHistoryBits;
|
||||||
|
params->choicePredictorSize = choicePredictorSize;
|
||||||
|
params->choiceCtrBits = choiceCtrBits;
|
||||||
|
|
||||||
|
params->BTBEntries = BTBEntries;
|
||||||
|
params->BTBTagSize = BTBTagSize;
|
||||||
|
|
||||||
|
params->RASSize = RASSize;
|
||||||
|
|
||||||
|
params->LQEntries = LQEntries;
|
||||||
|
params->SQEntries = SQEntries;
|
||||||
|
|
||||||
|
params->SSITSize = SSITSize;
|
||||||
|
params->LFSTSize = LFSTSize;
|
||||||
|
|
||||||
|
params->numPhysIntRegs = numPhysIntRegs;
|
||||||
|
params->numPhysFloatRegs = numPhysFloatRegs;
|
||||||
|
params->numIQEntries = numIQEntries;
|
||||||
|
params->numROBEntries = numROBEntries;
|
||||||
|
|
||||||
|
params->smtNumFetchingThreads = smtNumFetchingThreads;
|
||||||
|
|
||||||
|
// Default smtFetchPolicy to "RoundRobin", if necessary.
|
||||||
|
std::string round_robin_policy = "RoundRobin";
|
||||||
|
std::string single_thread = "SingleThread";
|
||||||
|
|
||||||
|
if (actual_num_threads > 1 && single_thread.compare(smtFetchPolicy) == 0)
|
||||||
|
params->smtFetchPolicy = round_robin_policy;
|
||||||
|
else
|
||||||
|
params->smtFetchPolicy = smtFetchPolicy;
|
||||||
|
|
||||||
|
params->smtIQPolicy = smtIQPolicy;
|
||||||
|
params->smtLSQPolicy = smtLSQPolicy;
|
||||||
|
params->smtLSQThreshold = smtLSQThreshold;
|
||||||
|
params->smtROBPolicy = smtROBPolicy;
|
||||||
|
params->smtROBThreshold = smtROBThreshold;
|
||||||
|
params->smtCommitPolicy = smtCommitPolicy;
|
||||||
|
|
||||||
|
params->instShiftAmt = 2;
|
||||||
|
|
||||||
|
params->deferRegistration = defer_registration;
|
||||||
|
|
||||||
|
params->functionTrace = function_trace;
|
||||||
|
params->functionTraceStart = function_trace_start;
|
||||||
|
|
||||||
|
cpu = new DerivO3CPU(params);
|
||||||
|
|
||||||
|
return cpu;
|
||||||
|
}
|
||||||
|
|
||||||
|
REGISTER_SIM_OBJECT("DerivO3CPU", DerivO3CPU)
|
||||||
|
|
319
src/cpu/o3/sparc/cpu_impl.hh
Normal file
319
src/cpu/o3/sparc/cpu_impl.hh
Normal file
|
@ -0,0 +1,319 @@
|
||||||
|
/*
|
||||||
|
* Copyright (c) 2004-2006 The Regents of The University of Michigan
|
||||||
|
* All rights reserved.
|
||||||
|
*
|
||||||
|
* Redistribution and use in source and binary forms, with or without
|
||||||
|
* modification, are permitted provided that the following conditions are
|
||||||
|
* met: redistributions of source code must retain the above copyright
|
||||||
|
* notice, this list of conditions and the following disclaimer;
|
||||||
|
* redistributions in binary form must reproduce the above copyright
|
||||||
|
* notice, this list of conditions and the following disclaimer in the
|
||||||
|
* documentation and/or other materials provided with the distribution;
|
||||||
|
* neither the name of the copyright holders nor the names of its
|
||||||
|
* contributors may be used to endorse or promote products derived from
|
||||||
|
* this software without specific prior written permission.
|
||||||
|
*
|
||||||
|
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||||
|
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||||
|
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||||
|
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||||
|
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||||
|
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||||
|
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||||
|
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||||
|
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||||
|
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||||
|
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||||
|
*
|
||||||
|
* Authors: Gabe Black
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include "config/use_checker.hh"
|
||||||
|
|
||||||
|
#include "arch/sparc/faults.hh"
|
||||||
|
#include "arch/sparc/isa_traits.hh"
|
||||||
|
#include "arch/sparc/miscregfile.hh"
|
||||||
|
#include "base/cprintf.hh"
|
||||||
|
#include "base/statistics.hh"
|
||||||
|
#include "base/timebuf.hh"
|
||||||
|
#include "cpu/checker/thread_context.hh"
|
||||||
|
#include "sim/sim_events.hh"
|
||||||
|
#include "sim/stats.hh"
|
||||||
|
|
||||||
|
#include "cpu/o3/sparc/cpu.hh"
|
||||||
|
#include "cpu/o3/sparc/params.hh"
|
||||||
|
#include "cpu/o3/sparc/thread_context.hh"
|
||||||
|
#include "cpu/o3/comm.hh"
|
||||||
|
#include "cpu/o3/thread_state.hh"
|
||||||
|
|
||||||
|
#if FULL_SYSTEM
|
||||||
|
#include "arch/sparc/isa_traits.hh"
|
||||||
|
#include "arch/sparc/kernel_stats.hh"
|
||||||
|
#include "cpu/quiesce_event.hh"
|
||||||
|
#include "sim/sim_exit.hh"
|
||||||
|
#include "sim/system.hh"
|
||||||
|
#endif
|
||||||
|
|
||||||
|
template <class Impl>
|
||||||
|
SparcO3CPU<Impl>::SparcO3CPU(Params *params)
|
||||||
|
#if FULL_SYSTEM
|
||||||
|
: FullO3CPU<Impl>(params), itb(params->itb), dtb(params->dtb)
|
||||||
|
#else
|
||||||
|
: FullO3CPU<Impl>(params)
|
||||||
|
#endif
|
||||||
|
{
|
||||||
|
DPRINTF(O3CPU, "Creating SparcO3CPU object.\n");
|
||||||
|
|
||||||
|
// Setup any thread state.
|
||||||
|
this->thread.resize(this->numThreads);
|
||||||
|
|
||||||
|
for (int i = 0; i < this->numThreads; ++i) {
|
||||||
|
#if FULL_SYSTEM
|
||||||
|
// SMT is not supported in FS mode yet.
|
||||||
|
assert(this->numThreads == 1);
|
||||||
|
this->thread[i] = new Thread(this, 0);
|
||||||
|
this->thread[i]->setStatus(ThreadContext::Suspended);
|
||||||
|
#else
|
||||||
|
if (i < params->workload.size()) {
|
||||||
|
DPRINTF(O3CPU, "Workload[%i] process is %#x",
|
||||||
|
i, this->thread[i]);
|
||||||
|
this->thread[i] = new Thread(this, i, params->workload[i], i);
|
||||||
|
|
||||||
|
this->thread[i]->setStatus(ThreadContext::Suspended);
|
||||||
|
|
||||||
|
//usedTids[i] = true;
|
||||||
|
//threadMap[i] = i;
|
||||||
|
} else {
|
||||||
|
//Allocate Empty thread so M5 can use later
|
||||||
|
//when scheduling threads to CPU
|
||||||
|
Process* dummy_proc = NULL;
|
||||||
|
|
||||||
|
this->thread[i] = new Thread(this, i, dummy_proc, i);
|
||||||
|
//usedTids[i] = false;
|
||||||
|
}
|
||||||
|
#endif // !FULL_SYSTEM
|
||||||
|
|
||||||
|
ThreadContext *tc;
|
||||||
|
|
||||||
|
// Setup the TC that will serve as the interface to the threads/CPU.
|
||||||
|
SparcTC<Impl> *sparc_tc = new SparcTC<Impl>;
|
||||||
|
|
||||||
|
tc = sparc_tc;
|
||||||
|
|
||||||
|
// If we're using a checker, then the TC should be the
|
||||||
|
// CheckerThreadContext.
|
||||||
|
#if USE_CHECKER
|
||||||
|
if (params->checker) {
|
||||||
|
tc = new CheckerThreadContext<SparcTC<Impl> >(
|
||||||
|
sparc_tc, this->checker);
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
sparc_tc->cpu = this;
|
||||||
|
sparc_tc->thread = this->thread[i];
|
||||||
|
|
||||||
|
#if FULL_SYSTEM
|
||||||
|
// Setup quiesce event.
|
||||||
|
this->thread[i]->quiesceEvent = new EndQuiesceEvent(tc);
|
||||||
|
#endif
|
||||||
|
// Give the thread the TC.
|
||||||
|
this->thread[i]->tc = tc;
|
||||||
|
|
||||||
|
// Add the TC to the CPU's list of TC's.
|
||||||
|
this->threadContexts.push_back(tc);
|
||||||
|
}
|
||||||
|
|
||||||
|
for (int i=0; i < this->numThreads; i++) {
|
||||||
|
this->thread[i]->setFuncExeInst(0);
|
||||||
|
}
|
||||||
|
|
||||||
|
// Sets CPU pointers. These must be set at this level because the CPU
|
||||||
|
// pointers are defined to be the highest level of CPU class.
|
||||||
|
this->fetch.setCPU(this);
|
||||||
|
this->decode.setCPU(this);
|
||||||
|
this->rename.setCPU(this);
|
||||||
|
this->iew.setCPU(this);
|
||||||
|
this->commit.setCPU(this);
|
||||||
|
|
||||||
|
this->rob.setCPU(this);
|
||||||
|
this->regFile.setCPU(this);
|
||||||
|
|
||||||
|
lockAddr = 0;
|
||||||
|
lockFlag = false;
|
||||||
|
}
|
||||||
|
|
||||||
|
template <class Impl>
|
||||||
|
void
|
||||||
|
SparcO3CPU<Impl>::regStats()
|
||||||
|
{
|
||||||
|
// Register stats for everything that has stats.
|
||||||
|
this->fullCPURegStats();
|
||||||
|
this->fetch.regStats();
|
||||||
|
this->decode.regStats();
|
||||||
|
this->rename.regStats();
|
||||||
|
this->iew.regStats();
|
||||||
|
this->commit.regStats();
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
template <class Impl>
|
||||||
|
TheISA::MiscReg
|
||||||
|
SparcO3CPU<Impl>::readMiscReg(int misc_reg, unsigned tid)
|
||||||
|
{
|
||||||
|
return this->regFile.readMiscReg(misc_reg, tid);
|
||||||
|
}
|
||||||
|
|
||||||
|
template <class Impl>
|
||||||
|
TheISA::MiscReg
|
||||||
|
SparcO3CPU<Impl>::readMiscRegWithEffect(int misc_reg, unsigned tid)
|
||||||
|
{
|
||||||
|
return this->regFile.readMiscRegWithEffect(misc_reg, tid);
|
||||||
|
}
|
||||||
|
|
||||||
|
template <class Impl>
|
||||||
|
void
|
||||||
|
SparcO3CPU<Impl>::setMiscReg(int misc_reg, const MiscReg &val, unsigned tid)
|
||||||
|
{
|
||||||
|
this->regFile.setMiscReg(misc_reg, val, tid);
|
||||||
|
}
|
||||||
|
|
||||||
|
template <class Impl>
|
||||||
|
void
|
||||||
|
SparcO3CPU<Impl>::setMiscRegWithEffect(int misc_reg, const MiscReg &val,
|
||||||
|
unsigned tid)
|
||||||
|
{
|
||||||
|
this->regFile.setMiscRegWithEffect(misc_reg, val, tid);
|
||||||
|
}
|
||||||
|
|
||||||
|
template <class Impl>
|
||||||
|
void
|
||||||
|
SparcO3CPU<Impl>::squashFromTC(unsigned tid)
|
||||||
|
{
|
||||||
|
this->thread[tid]->inSyscall = true;
|
||||||
|
this->commit.generateTCEvent(tid);
|
||||||
|
}
|
||||||
|
|
||||||
|
#if FULL_SYSTEM
|
||||||
|
|
||||||
|
template <class Impl>
|
||||||
|
void
|
||||||
|
SparcO3CPU<Impl>::post_interrupt(int int_num, int index)
|
||||||
|
{
|
||||||
|
BaseCPU::post_interrupt(int_num, index);
|
||||||
|
|
||||||
|
if (this->thread[0]->status() == ThreadContext::Suspended) {
|
||||||
|
DPRINTF(IPI,"Suspended Processor awoke\n");
|
||||||
|
this->threadContexts[0]->activate();
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
template <class Impl>
|
||||||
|
Fault
|
||||||
|
SparcO3CPU<Impl>::hwrei(unsigned tid)
|
||||||
|
{
|
||||||
|
panic("This doesn't make sense for SPARC\n");
|
||||||
|
return NoFault;
|
||||||
|
}
|
||||||
|
|
||||||
|
template <class Impl>
|
||||||
|
bool
|
||||||
|
SparcO3CPU<Impl>::simPalCheck(int palFunc, unsigned tid)
|
||||||
|
{
|
||||||
|
panic("This doesn't make sense for SPARC\n");
|
||||||
|
return true;
|
||||||
|
}
|
||||||
|
|
||||||
|
template <class Impl>
|
||||||
|
Fault
|
||||||
|
SparcO3CPU<Impl>::getInterrupts()
|
||||||
|
{
|
||||||
|
// Check if there are any outstanding interrupts
|
||||||
|
return this->interrupts.getInterrupt(this->threadContexts[0]);
|
||||||
|
}
|
||||||
|
|
||||||
|
template <class Impl>
|
||||||
|
void
|
||||||
|
SparcO3CPU<Impl>::processInterrupts(Fault interrupt)
|
||||||
|
{
|
||||||
|
// Check for interrupts here. For now can copy the code that
|
||||||
|
// exists within isa_fullsys_traits.hh. Also assume that thread 0
|
||||||
|
// is the one that handles the interrupts.
|
||||||
|
// @todo: Possibly consolidate the interrupt checking code.
|
||||||
|
// @todo: Allow other threads to handle interrupts.
|
||||||
|
|
||||||
|
assert(interrupt != NoFault);
|
||||||
|
this->interrupts.updateIntrInfo(this->threadContexts[0]);
|
||||||
|
|
||||||
|
DPRINTF(O3CPU, "Interrupt %s being handled\n", interrupt->name());
|
||||||
|
this->checkInterrupts = false;
|
||||||
|
this->trap(interrupt, 0);
|
||||||
|
}
|
||||||
|
|
||||||
|
#endif // FULL_SYSTEM
|
||||||
|
|
||||||
|
template <class Impl>
|
||||||
|
void
|
||||||
|
SparcO3CPU<Impl>::trap(Fault fault, unsigned tid)
|
||||||
|
{
|
||||||
|
// Pass the thread's TC into the invoke method.
|
||||||
|
fault->invoke(this->threadContexts[tid]);
|
||||||
|
}
|
||||||
|
|
||||||
|
#if !FULL_SYSTEM
|
||||||
|
|
||||||
|
template <class Impl>
|
||||||
|
void
|
||||||
|
SparcO3CPU<Impl>::syscall(int64_t callnum, int tid)
|
||||||
|
{
|
||||||
|
DPRINTF(O3CPU, "[tid:%i] Executing syscall().\n\n", tid);
|
||||||
|
|
||||||
|
DPRINTF(Activity,"Activity: syscall() called.\n");
|
||||||
|
|
||||||
|
// Temporarily increase this by one to account for the syscall
|
||||||
|
// instruction.
|
||||||
|
++(this->thread[tid]->funcExeInst);
|
||||||
|
|
||||||
|
// Execute the actual syscall.
|
||||||
|
this->thread[tid]->syscall(callnum);
|
||||||
|
|
||||||
|
// Decrease funcExeInst by one as the normal commit will handle
|
||||||
|
// incrementing it.
|
||||||
|
--(this->thread[tid]->funcExeInst);
|
||||||
|
}
|
||||||
|
|
||||||
|
template <class Impl>
|
||||||
|
TheISA::IntReg
|
||||||
|
SparcO3CPU<Impl>::getSyscallArg(int i, int tid)
|
||||||
|
{
|
||||||
|
return this->readArchIntReg(SparcISA::ArgumentReg0 + i, tid);
|
||||||
|
}
|
||||||
|
|
||||||
|
template <class Impl>
|
||||||
|
void
|
||||||
|
SparcO3CPU<Impl>::setSyscallArg(int i, IntReg val, int tid)
|
||||||
|
{
|
||||||
|
this->setArchIntReg(SparcISA::ArgumentReg0 + i, val, tid);
|
||||||
|
}
|
||||||
|
|
||||||
|
template <class Impl>
|
||||||
|
void
|
||||||
|
SparcO3CPU<Impl>::setSyscallReturn(SyscallReturn return_value, int tid)
|
||||||
|
{
|
||||||
|
// check for error condition. SPARC syscall convention is to
|
||||||
|
// indicate success/failure in reg the carry bit of the ccr
|
||||||
|
// and put the return value itself in the standard return value reg ().
|
||||||
|
if (return_value.successful()) {
|
||||||
|
// no error, clear XCC.C
|
||||||
|
this->setMiscReg(SparcISA::MISCREG_CCR,
|
||||||
|
this->readMiscReg(SparcISA::MISCREG_CCR, tid) & 0xEE, tid);
|
||||||
|
this->setArchIntReg(SparcISA::ReturnValueReg,
|
||||||
|
return_value.value(), tid);
|
||||||
|
} else {
|
||||||
|
// got an error, set XCC.C
|
||||||
|
this->setMiscReg(SparcISA::MISCREG_CCR,
|
||||||
|
this->readMiscReg(SparcISA::MISCREG_CCR, tid) | 0x11, tid);
|
||||||
|
this->setArchIntReg(SparcISA::ReturnValueReg,
|
||||||
|
return_value.value(), tid);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
#endif
|
36
src/cpu/o3/sparc/dyn_inst.cc
Normal file
36
src/cpu/o3/sparc/dyn_inst.cc
Normal file
|
@ -0,0 +1,36 @@
|
||||||
|
/*
|
||||||
|
* Copyright (c) 2004-2005 The Regents of The University of Michigan
|
||||||
|
* All rights reserved.
|
||||||
|
*
|
||||||
|
* Redistribution and use in source and binary forms, with or without
|
||||||
|
* modification, are permitted provided that the following conditions are
|
||||||
|
* met: redistributions of source code must retain the above copyright
|
||||||
|
* notice, this list of conditions and the following disclaimer;
|
||||||
|
* redistributions in binary form must reproduce the above copyright
|
||||||
|
* notice, this list of conditions and the following disclaimer in the
|
||||||
|
* documentation and/or other materials provided with the distribution;
|
||||||
|
* neither the name of the copyright holders nor the names of its
|
||||||
|
* contributors may be used to endorse or promote products derived from
|
||||||
|
* this software without specific prior written permission.
|
||||||
|
*
|
||||||
|
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||||
|
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||||
|
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||||
|
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||||
|
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||||
|
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||||
|
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||||
|
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||||
|
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||||
|
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||||
|
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||||
|
*
|
||||||
|
* Authors: Gabe Black
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include "cpu/o3/sparc/dyn_inst_impl.hh"
|
||||||
|
#include "cpu/o3/sparc/impl.hh"
|
||||||
|
|
||||||
|
// Force instantiation of SparcDynInst for all the implementations that
|
||||||
|
// are needed.
|
||||||
|
template class SparcDynInst<SparcSimpleImpl>;
|
273
src/cpu/o3/sparc/dyn_inst.hh
Normal file
273
src/cpu/o3/sparc/dyn_inst.hh
Normal file
|
@ -0,0 +1,273 @@
|
||||||
|
/*
|
||||||
|
* Copyright (c) 2004-2006 The Regents of The University of Michigan
|
||||||
|
* All rights reserved.
|
||||||
|
*
|
||||||
|
* Redistribution and use in source and binary forms, with or without
|
||||||
|
* modification, are permitted provided that the following conditions are
|
||||||
|
* met: redistributions of source code must retain the above copyright
|
||||||
|
* notice, this list of conditions and the following disclaimer;
|
||||||
|
* redistributions in binary form must reproduce the above copyright
|
||||||
|
* notice, this list of conditions and the following disclaimer in the
|
||||||
|
* documentation and/or other materials provided with the distribution;
|
||||||
|
* neither the name of the copyright holders nor the names of its
|
||||||
|
* contributors may be used to endorse or promote products derived from
|
||||||
|
* this software without specific prior written permission.
|
||||||
|
*
|
||||||
|
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||||
|
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||||
|
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||||
|
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||||
|
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||||
|
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||||
|
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||||
|
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||||
|
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||||
|
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||||
|
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||||
|
*
|
||||||
|
* Authors: Gabe Black
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef __CPU_O3_SPARC_DYN_INST_HH__
|
||||||
|
#define __CPU_O3_SPARC_DYN_INST_HH__
|
||||||
|
|
||||||
|
#include "arch/sparc/isa_traits.hh"
|
||||||
|
#include "cpu/base_dyn_inst.hh"
|
||||||
|
#include "cpu/inst_seq.hh"
|
||||||
|
#include "cpu/o3/sparc/cpu.hh"
|
||||||
|
#include "cpu/o3/sparc/impl.hh"
|
||||||
|
|
||||||
|
class Packet;
|
||||||
|
|
||||||
|
/**
|
||||||
|
* Mostly implementation & ISA specific SparcDynInst. As with most
|
||||||
|
* other classes in the new CPU model, it is templated on the Impl to
|
||||||
|
* allow for passing in of all types, such as the CPU type and the ISA
|
||||||
|
* type. The SparcDynInst serves as the primary interface to the CPU
|
||||||
|
* for instructions that are executing.
|
||||||
|
*/
|
||||||
|
template <class Impl>
|
||||||
|
class SparcDynInst : public BaseDynInst<Impl>
|
||||||
|
{
|
||||||
|
public:
|
||||||
|
/** Typedef for the CPU. */
|
||||||
|
typedef typename Impl::O3CPU O3CPU;
|
||||||
|
|
||||||
|
public:
|
||||||
|
/** BaseDynInst constructor given a binary instruction. */
|
||||||
|
SparcDynInst(TheISA::ExtMachInst inst, Addr PC,
|
||||||
|
Addr Pred_PC, InstSeqNum seq_num, O3CPU *cpu);
|
||||||
|
|
||||||
|
/** BaseDynInst constructor given a static inst pointer. */
|
||||||
|
SparcDynInst(StaticInstPtr &_staticInst);
|
||||||
|
|
||||||
|
/** Executes the instruction.*/
|
||||||
|
Fault execute();
|
||||||
|
|
||||||
|
/** Initiates the access. Only valid for memory operations. */
|
||||||
|
Fault initiateAcc();
|
||||||
|
|
||||||
|
/** Completes the access. Only valid for memory operations. */
|
||||||
|
Fault completeAcc(PacketPtr pkt);
|
||||||
|
|
||||||
|
private:
|
||||||
|
/** Initializes variables. */
|
||||||
|
void initVars();
|
||||||
|
|
||||||
|
public:
|
||||||
|
/** Reads a miscellaneous register. */
|
||||||
|
TheISA::MiscReg readMiscReg(int misc_reg)
|
||||||
|
{
|
||||||
|
return this->cpu->readMiscReg(misc_reg, this->threadNumber);
|
||||||
|
}
|
||||||
|
|
||||||
|
/** Reads a misc. register, including any side-effects the read
|
||||||
|
* might have as defined by the architecture.
|
||||||
|
*/
|
||||||
|
TheISA::MiscReg readMiscRegWithEffect(int misc_reg)
|
||||||
|
{
|
||||||
|
return this->cpu->readMiscRegWithEffect(misc_reg, this->threadNumber);
|
||||||
|
}
|
||||||
|
|
||||||
|
/** Sets a misc. register. */
|
||||||
|
void setMiscReg(int misc_reg, const TheISA::MiscReg &val)
|
||||||
|
{
|
||||||
|
this->instResult.integer = val;
|
||||||
|
return this->cpu->setMiscReg(misc_reg, val, this->threadNumber);
|
||||||
|
}
|
||||||
|
|
||||||
|
/** Sets a misc. register, including any side-effects the write
|
||||||
|
* might have as defined by the architecture.
|
||||||
|
*/
|
||||||
|
void setMiscRegWithEffect(int misc_reg, const TheISA::MiscReg &val)
|
||||||
|
{
|
||||||
|
return this->cpu->setMiscRegWithEffect(misc_reg, val,
|
||||||
|
this->threadNumber);
|
||||||
|
}
|
||||||
|
|
||||||
|
#if FULL_SYSTEM
|
||||||
|
/** Calls hardware return from error interrupt. */
|
||||||
|
Fault hwrei();
|
||||||
|
/** Traps to handle specified fault. */
|
||||||
|
void trap(Fault fault);
|
||||||
|
bool simPalCheck(int palFunc);
|
||||||
|
#else
|
||||||
|
/** Calls a syscall. */
|
||||||
|
void syscall(int64_t callnum);
|
||||||
|
#endif
|
||||||
|
|
||||||
|
private:
|
||||||
|
/** Physical register index of the destination registers of this
|
||||||
|
* instruction.
|
||||||
|
*/
|
||||||
|
PhysRegIndex _destRegIdx[TheISA::MaxInstDestRegs];
|
||||||
|
|
||||||
|
/** Physical register index of the source registers of this
|
||||||
|
* instruction.
|
||||||
|
*/
|
||||||
|
PhysRegIndex _srcRegIdx[TheISA::MaxInstSrcRegs];
|
||||||
|
|
||||||
|
/** Physical register index of the previous producers of the
|
||||||
|
* architected destinations.
|
||||||
|
*/
|
||||||
|
PhysRegIndex _prevDestRegIdx[TheISA::MaxInstDestRegs];
|
||||||
|
|
||||||
|
public:
|
||||||
|
|
||||||
|
// The register accessor methods provide the index of the
|
||||||
|
// instruction's operand (e.g., 0 or 1), not the architectural
|
||||||
|
// register index, to simplify the implementation of register
|
||||||
|
// renaming. We find the architectural register index by indexing
|
||||||
|
// into the instruction's own operand index table. Note that a
|
||||||
|
// raw pointer to the StaticInst is provided instead of a
|
||||||
|
// ref-counted StaticInstPtr to redice overhead. This is fine as
|
||||||
|
// long as these methods don't copy the pointer into any long-term
|
||||||
|
// storage (which is pretty hard to imagine they would have reason
|
||||||
|
// to do).
|
||||||
|
|
||||||
|
uint64_t readIntReg(const StaticInst *si, int idx)
|
||||||
|
{
|
||||||
|
return this->cpu->readIntReg(_srcRegIdx[idx]);
|
||||||
|
}
|
||||||
|
|
||||||
|
TheISA::FloatReg readFloatReg(const StaticInst *si, int idx, int width)
|
||||||
|
{
|
||||||
|
return this->cpu->readFloatReg(_srcRegIdx[idx], width);
|
||||||
|
}
|
||||||
|
|
||||||
|
TheISA::FloatReg readFloatReg(const StaticInst *si, int idx)
|
||||||
|
{
|
||||||
|
return this->cpu->readFloatReg(_srcRegIdx[idx]);
|
||||||
|
}
|
||||||
|
|
||||||
|
TheISA::FloatRegBits readFloatRegBits(const StaticInst *si,
|
||||||
|
int idx, int width)
|
||||||
|
{
|
||||||
|
return this->cpu->readFloatRegBits(_srcRegIdx[idx], width);
|
||||||
|
}
|
||||||
|
|
||||||
|
TheISA::FloatRegBits readFloatRegBits(const StaticInst *si, int idx)
|
||||||
|
{
|
||||||
|
return this->cpu->readFloatRegBits(_srcRegIdx[idx]);
|
||||||
|
}
|
||||||
|
|
||||||
|
/** @todo: Make results into arrays so they can handle multiple dest
|
||||||
|
* registers.
|
||||||
|
*/
|
||||||
|
void setIntReg(const StaticInst *si, int idx, uint64_t val)
|
||||||
|
{
|
||||||
|
this->cpu->setIntReg(_destRegIdx[idx], val);
|
||||||
|
BaseDynInst<Impl>::setIntReg(si, idx, val);
|
||||||
|
}
|
||||||
|
|
||||||
|
void setFloatReg(const StaticInst *si, int idx,
|
||||||
|
TheISA::FloatReg val, int width)
|
||||||
|
{
|
||||||
|
this->cpu->setFloatReg(_destRegIdx[idx], val, width);
|
||||||
|
BaseDynInst<Impl>::setFloatReg(si, idx, val, width);
|
||||||
|
}
|
||||||
|
|
||||||
|
void setFloatReg(const StaticInst *si, int idx, TheISA::FloatReg val)
|
||||||
|
{
|
||||||
|
this->cpu->setFloatReg(_destRegIdx[idx], val);
|
||||||
|
BaseDynInst<Impl>::setFloatReg(si, idx, val);
|
||||||
|
}
|
||||||
|
|
||||||
|
void setFloatRegBits(const StaticInst *si, int idx,
|
||||||
|
TheISA::FloatRegBits val, int width)
|
||||||
|
{
|
||||||
|
this->cpu->setFloatRegBits(_destRegIdx[idx], val, width);
|
||||||
|
BaseDynInst<Impl>::setFloatRegBits(si, idx, val);
|
||||||
|
}
|
||||||
|
|
||||||
|
void setFloatRegBits(const StaticInst *si,
|
||||||
|
int idx, TheISA::FloatRegBits val)
|
||||||
|
{
|
||||||
|
this->cpu->setFloatRegBits(_destRegIdx[idx], val);
|
||||||
|
BaseDynInst<Impl>::setFloatRegBits(si, idx, val);
|
||||||
|
}
|
||||||
|
|
||||||
|
/** Returns the physical register index of the i'th destination
|
||||||
|
* register.
|
||||||
|
*/
|
||||||
|
PhysRegIndex renamedDestRegIdx(int idx) const
|
||||||
|
{
|
||||||
|
return _destRegIdx[idx];
|
||||||
|
}
|
||||||
|
|
||||||
|
/** Returns the physical register index of the i'th source register. */
|
||||||
|
PhysRegIndex renamedSrcRegIdx(int idx) const
|
||||||
|
{
|
||||||
|
return _srcRegIdx[idx];
|
||||||
|
}
|
||||||
|
|
||||||
|
/** Returns the physical register index of the previous physical register
|
||||||
|
* that remapped to the same logical register index.
|
||||||
|
*/
|
||||||
|
PhysRegIndex prevDestRegIdx(int idx) const
|
||||||
|
{
|
||||||
|
return _prevDestRegIdx[idx];
|
||||||
|
}
|
||||||
|
|
||||||
|
/** Renames a destination register to a physical register. Also records
|
||||||
|
* the previous physical register that the logical register mapped to.
|
||||||
|
*/
|
||||||
|
void renameDestReg(int idx,
|
||||||
|
PhysRegIndex renamed_dest,
|
||||||
|
PhysRegIndex previous_rename)
|
||||||
|
{
|
||||||
|
_destRegIdx[idx] = renamed_dest;
|
||||||
|
_prevDestRegIdx[idx] = previous_rename;
|
||||||
|
}
|
||||||
|
|
||||||
|
/** Renames a source logical register to the physical register which
|
||||||
|
* has/will produce that logical register's result.
|
||||||
|
* @todo: add in whether or not the source register is ready.
|
||||||
|
*/
|
||||||
|
void renameSrcReg(int idx, PhysRegIndex renamed_src)
|
||||||
|
{
|
||||||
|
_srcRegIdx[idx] = renamed_src;
|
||||||
|
}
|
||||||
|
|
||||||
|
public:
|
||||||
|
/** Calculates EA part of a memory instruction. Currently unused,
|
||||||
|
* though it may be useful in the future if we want to split
|
||||||
|
* memory operations into EA calculation and memory access parts.
|
||||||
|
*/
|
||||||
|
Fault calcEA()
|
||||||
|
{
|
||||||
|
return this->staticInst->eaCompInst()->execute(this, this->traceData);
|
||||||
|
}
|
||||||
|
|
||||||
|
/** Does the memory access part of a memory instruction. Currently unused,
|
||||||
|
* though it may be useful in the future if we want to split
|
||||||
|
* memory operations into EA calculation and memory access parts.
|
||||||
|
*/
|
||||||
|
Fault memAccess()
|
||||||
|
{
|
||||||
|
return this->staticInst->memAccInst()->execute(this, this->traceData);
|
||||||
|
}
|
||||||
|
};
|
||||||
|
|
||||||
|
#endif // __CPU_O3_SPARC_DYN_INST_HH__
|
||||||
|
|
139
src/cpu/o3/sparc/dyn_inst_impl.hh
Normal file
139
src/cpu/o3/sparc/dyn_inst_impl.hh
Normal file
|
@ -0,0 +1,139 @@
|
||||||
|
/*
|
||||||
|
* Copyright (c) 2004-2006 The Regents of The University of Michigan
|
||||||
|
* All rights reserved.
|
||||||
|
*
|
||||||
|
* Redistribution and use in source and binary forms, with or without
|
||||||
|
* modification, are permitted provided that the following conditions are
|
||||||
|
* met: redistributions of source code must retain the above copyright
|
||||||
|
* notice, this list of conditions and the following disclaimer;
|
||||||
|
* redistributions in binary form must reproduce the above copyright
|
||||||
|
* notice, this list of conditions and the following disclaimer in the
|
||||||
|
* documentation and/or other materials provided with the distribution;
|
||||||
|
* neither the name of the copyright holders nor the names of its
|
||||||
|
* contributors may be used to endorse or promote products derived from
|
||||||
|
* this software without specific prior written permission.
|
||||||
|
*
|
||||||
|
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||||
|
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||||
|
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||||
|
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||||
|
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||||
|
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||||
|
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||||
|
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||||
|
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||||
|
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||||
|
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||||
|
*
|
||||||
|
* Authors: Gabe Black
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include "cpu/o3/sparc/dyn_inst.hh"
|
||||||
|
|
||||||
|
template <class Impl>
|
||||||
|
SparcDynInst<Impl>::SparcDynInst(TheISA::ExtMachInst inst, Addr PC,
|
||||||
|
Addr Pred_PC, InstSeqNum seq_num, O3CPU *cpu)
|
||||||
|
: BaseDynInst<Impl>(inst, PC, Pred_PC, seq_num, cpu)
|
||||||
|
{
|
||||||
|
initVars();
|
||||||
|
}
|
||||||
|
|
||||||
|
template <class Impl>
|
||||||
|
SparcDynInst<Impl>::SparcDynInst(StaticInstPtr &_staticInst)
|
||||||
|
: BaseDynInst<Impl>(_staticInst)
|
||||||
|
{
|
||||||
|
initVars();
|
||||||
|
}
|
||||||
|
|
||||||
|
template <class Impl>
|
||||||
|
void
|
||||||
|
SparcDynInst<Impl>::initVars()
|
||||||
|
{
|
||||||
|
// Make sure to have the renamed register entries set to the same
|
||||||
|
// as the normal register entries. It will allow the IQ to work
|
||||||
|
// without any modifications.
|
||||||
|
for (int i = 0; i < this->staticInst->numDestRegs(); i++) {
|
||||||
|
_destRegIdx[i] = this->staticInst->destRegIdx(i);
|
||||||
|
}
|
||||||
|
|
||||||
|
for (int i = 0; i < this->staticInst->numSrcRegs(); i++) {
|
||||||
|
_srcRegIdx[i] = this->staticInst->srcRegIdx(i);
|
||||||
|
this->_readySrcRegIdx[i] = 0;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
template <class Impl>
|
||||||
|
Fault
|
||||||
|
SparcDynInst<Impl>::execute()
|
||||||
|
{
|
||||||
|
// @todo: Pretty convoluted way to avoid squashing from happening
|
||||||
|
// when using the TC during an instruction's execution
|
||||||
|
// (specifically for instructions that have side-effects that use
|
||||||
|
// the TC). Fix this.
|
||||||
|
bool in_syscall = this->thread->inSyscall;
|
||||||
|
this->thread->inSyscall = true;
|
||||||
|
|
||||||
|
this->fault = this->staticInst->execute(this, this->traceData);
|
||||||
|
|
||||||
|
this->thread->inSyscall = in_syscall;
|
||||||
|
|
||||||
|
return this->fault;
|
||||||
|
}
|
||||||
|
|
||||||
|
template <class Impl>
|
||||||
|
Fault
|
||||||
|
SparcDynInst<Impl>::initiateAcc()
|
||||||
|
{
|
||||||
|
// @todo: Pretty convoluted way to avoid squashing from happening
|
||||||
|
// when using the TC during an instruction's execution
|
||||||
|
// (specifically for instructions that have side-effects that use
|
||||||
|
// the TC). Fix this.
|
||||||
|
bool in_syscall = this->thread->inSyscall;
|
||||||
|
this->thread->inSyscall = true;
|
||||||
|
|
||||||
|
this->fault = this->staticInst->initiateAcc(this, this->traceData);
|
||||||
|
|
||||||
|
this->thread->inSyscall = in_syscall;
|
||||||
|
|
||||||
|
return this->fault;
|
||||||
|
}
|
||||||
|
|
||||||
|
template <class Impl>
|
||||||
|
Fault
|
||||||
|
SparcDynInst<Impl>::completeAcc(PacketPtr pkt)
|
||||||
|
{
|
||||||
|
this->fault = this->staticInst->completeAcc(pkt, this, this->traceData);
|
||||||
|
|
||||||
|
return this->fault;
|
||||||
|
}
|
||||||
|
|
||||||
|
#if FULL_SYSTEM
|
||||||
|
template <class Impl>
|
||||||
|
Fault
|
||||||
|
SparcDynInst<Impl>::hwrei()
|
||||||
|
{
|
||||||
|
return NoFault;
|
||||||
|
}
|
||||||
|
|
||||||
|
template <class Impl>
|
||||||
|
void
|
||||||
|
SparcDynInst<Impl>::trap(Fault fault)
|
||||||
|
{
|
||||||
|
this->cpu->trap(fault, this->threadNumber);
|
||||||
|
}
|
||||||
|
|
||||||
|
template <class Impl>
|
||||||
|
bool
|
||||||
|
SparcDynInst<Impl>::simPalCheck(int palFunc)
|
||||||
|
{
|
||||||
|
return this->cpu->simPalCheck(palFunc, this->threadNumber);
|
||||||
|
}
|
||||||
|
#else
|
||||||
|
template <class Impl>
|
||||||
|
void
|
||||||
|
SparcDynInst<Impl>::syscall(int64_t callnum)
|
||||||
|
{
|
||||||
|
this->cpu->syscall(callnum, this->threadNumber);
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
92
src/cpu/o3/sparc/impl.hh
Normal file
92
src/cpu/o3/sparc/impl.hh
Normal file
|
@ -0,0 +1,92 @@
|
||||||
|
/*
|
||||||
|
* Copyright (c) 2004-2005 The Regents of The University of Michigan
|
||||||
|
* All rights reserved.
|
||||||
|
*
|
||||||
|
* Redistribution and use in source and binary forms, with or without
|
||||||
|
* modification, are permitted provided that the following conditions are
|
||||||
|
* met: redistributions of source code must retain the above copyright
|
||||||
|
* notice, this list of conditions and the following disclaimer;
|
||||||
|
* redistributions in binary form must reproduce the above copyright
|
||||||
|
* notice, this list of conditions and the following disclaimer in the
|
||||||
|
* documentation and/or other materials provided with the distribution;
|
||||||
|
* neither the name of the copyright holders nor the names of its
|
||||||
|
* contributors may be used to endorse or promote products derived from
|
||||||
|
* this software without specific prior written permission.
|
||||||
|
*
|
||||||
|
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||||
|
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||||
|
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||||
|
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||||
|
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||||
|
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||||
|
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||||
|
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||||
|
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||||
|
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||||
|
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||||
|
*
|
||||||
|
* Authors: Gabe Black
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef __CPU_O3_SPARC_IMPL_HH__
|
||||||
|
#define __CPU_O3_SPARC_IMPL_HH__
|
||||||
|
|
||||||
|
#include "arch/sparc/isa_traits.hh"
|
||||||
|
|
||||||
|
#include "cpu/o3/sparc/params.hh"
|
||||||
|
#include "cpu/o3/cpu_policy.hh"
|
||||||
|
|
||||||
|
|
||||||
|
// Forward declarations.
|
||||||
|
template <class Impl>
|
||||||
|
class SparcDynInst;
|
||||||
|
|
||||||
|
template <class Impl>
|
||||||
|
class SparcO3CPU;
|
||||||
|
|
||||||
|
/** Implementation specific struct that defines several key types to the
|
||||||
|
* CPU, the stages within the CPU, the time buffers, and the DynInst.
|
||||||
|
* The struct defines the ISA, the CPU policy, the specific DynInst, the
|
||||||
|
* specific O3CPU, and all of the structs from the time buffers to do
|
||||||
|
* communication.
|
||||||
|
* This is one of the key things that must be defined for each hardware
|
||||||
|
* specific CPU implementation.
|
||||||
|
*/
|
||||||
|
struct SparcSimpleImpl
|
||||||
|
{
|
||||||
|
/** The type of MachInst. */
|
||||||
|
typedef TheISA::MachInst MachInst;
|
||||||
|
|
||||||
|
/** The CPU policy to be used, which defines all of the CPU stages. */
|
||||||
|
typedef SimpleCPUPolicy<SparcSimpleImpl> CPUPol;
|
||||||
|
|
||||||
|
/** The DynInst type to be used. */
|
||||||
|
typedef SparcDynInst<SparcSimpleImpl> DynInst;
|
||||||
|
|
||||||
|
/** The refcounted DynInst pointer to be used. In most cases this is
|
||||||
|
* what should be used, and not DynInst *.
|
||||||
|
*/
|
||||||
|
typedef RefCountingPtr<DynInst> DynInstPtr;
|
||||||
|
|
||||||
|
/** The O3CPU type to be used. */
|
||||||
|
typedef SparcO3CPU<SparcSimpleImpl> O3CPU;
|
||||||
|
|
||||||
|
/** Same typedef, but for CPUType. BaseDynInst may not always use
|
||||||
|
* an O3 CPU, so it's clearer to call it CPUType instead in that
|
||||||
|
* case.
|
||||||
|
*/
|
||||||
|
typedef O3CPU CPUType;
|
||||||
|
|
||||||
|
/** The Params to be passed to each stage. */
|
||||||
|
typedef SparcSimpleParams Params;
|
||||||
|
|
||||||
|
enum {
|
||||||
|
MaxWidth = 8,
|
||||||
|
MaxThreads = 4
|
||||||
|
};
|
||||||
|
};
|
||||||
|
|
||||||
|
/** The O3Impl to be used. */
|
||||||
|
typedef SparcSimpleImpl O3CPUImpl;
|
||||||
|
|
||||||
|
#endif // __CPU_O3_SPARC_IMPL_HH__
|
63
src/cpu/o3/sparc/params.hh
Normal file
63
src/cpu/o3/sparc/params.hh
Normal file
|
@ -0,0 +1,63 @@
|
||||||
|
/*
|
||||||
|
* Copyright (c) 2004-2006 The Regents of The University of Michigan
|
||||||
|
* All rights reserved.
|
||||||
|
*
|
||||||
|
* Redistribution and use in source and binary forms, with or without
|
||||||
|
* modification, are permitted provided that the following conditions are
|
||||||
|
* met: redistributions of source code must retain the above copyright
|
||||||
|
* notice, this list of conditions and the following disclaimer;
|
||||||
|
* redistributions in binary form must reproduce the above copyright
|
||||||
|
* notice, this list of conditions and the following disclaimer in the
|
||||||
|
* documentation and/or other materials provided with the distribution;
|
||||||
|
* neither the name of the copyright holders nor the names of its
|
||||||
|
* contributors may be used to endorse or promote products derived from
|
||||||
|
* this software without specific prior written permission.
|
||||||
|
*
|
||||||
|
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||||
|
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||||
|
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||||
|
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||||
|
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||||
|
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||||
|
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||||
|
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||||
|
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||||
|
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||||
|
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||||
|
*
|
||||||
|
* Authors: Gabe Black
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef __CPU_O3_SPARC_PARAMS_HH__
|
||||||
|
#define __CPU_O3_SPARC_PARAMS_HH__
|
||||||
|
|
||||||
|
#include "cpu/o3/cpu.hh"
|
||||||
|
#include "cpu/o3/params.hh"
|
||||||
|
|
||||||
|
//Forward declarations
|
||||||
|
namespace SparcISA
|
||||||
|
{
|
||||||
|
class DTB;
|
||||||
|
class ITB;
|
||||||
|
}
|
||||||
|
class MemObject;
|
||||||
|
class Process;
|
||||||
|
class System;
|
||||||
|
|
||||||
|
/**
|
||||||
|
* This file defines the parameters that will be used for the AlphaO3CPU.
|
||||||
|
* This must be defined externally so that the Impl can have a params class
|
||||||
|
* defined that it can pass to all of the individual stages.
|
||||||
|
*/
|
||||||
|
|
||||||
|
class SparcSimpleParams : public O3Params
|
||||||
|
{
|
||||||
|
public:
|
||||||
|
|
||||||
|
#if FULL_SYSTEM
|
||||||
|
SparcISA::ITB *itb;
|
||||||
|
SparcISA::DTB *dtb;
|
||||||
|
#endif
|
||||||
|
};
|
||||||
|
|
||||||
|
#endif // __CPU_O3_SPARC_PARAMS_HH__
|
35
src/cpu/o3/sparc/thread_context.cc
Executable file
35
src/cpu/o3/sparc/thread_context.cc
Executable file
|
@ -0,0 +1,35 @@
|
||||||
|
/*
|
||||||
|
* Copyright (c) 2004-2006 The Regents of The University of Michigan
|
||||||
|
* All rights reserved.
|
||||||
|
*
|
||||||
|
* Redistribution and use in source and binary forms, with or without
|
||||||
|
* modification, are permitted provided that the following conditions are
|
||||||
|
* met: redistributions of source code must retain the above copyright
|
||||||
|
* notice, this list of conditions and the following disclaimer;
|
||||||
|
* redistributions in binary form must reproduce the above copyright
|
||||||
|
* notice, this list of conditions and the following disclaimer in the
|
||||||
|
* documentation and/or other materials provided with the distribution;
|
||||||
|
* neither the name of the copyright holders nor the names of its
|
||||||
|
* contributors may be used to endorse or promote products derived from
|
||||||
|
* this software without specific prior written permission.
|
||||||
|
*
|
||||||
|
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||||
|
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||||
|
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||||
|
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||||
|
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||||
|
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||||
|
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||||
|
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||||
|
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||||
|
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||||
|
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||||
|
*
|
||||||
|
* Authors: Gabe Black
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include "cpu/o3/thread_context.hh"
|
||||||
|
#include "cpu/o3/thread_context_impl.hh"
|
||||||
|
|
||||||
|
template class O3ThreadContext<SparcSimpleImpl>;
|
||||||
|
|
84
src/cpu/o3/sparc/thread_context.hh
Normal file
84
src/cpu/o3/sparc/thread_context.hh
Normal file
|
@ -0,0 +1,84 @@
|
||||||
|
/*
|
||||||
|
* Copyright (c) 2004-2006 The Regents of The University of Michigan
|
||||||
|
* All rights reserved.
|
||||||
|
*
|
||||||
|
* Redistribution and use in source and binary forms, with or without
|
||||||
|
* modification, are permitted provided that the following conditions are
|
||||||
|
* met: redistributions of source code must retain the above copyright
|
||||||
|
* notice, this list of conditions and the following disclaimer;
|
||||||
|
* redistributions in binary form must reproduce the above copyright
|
||||||
|
* notice, this list of conditions and the following disclaimer in the
|
||||||
|
* documentation and/or other materials provided with the distribution;
|
||||||
|
* neither the name of the copyright holders nor the names of its
|
||||||
|
* contributors may be used to endorse or promote products derived from
|
||||||
|
* this software without specific prior written permission.
|
||||||
|
*
|
||||||
|
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||||
|
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||||
|
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||||
|
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||||
|
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||||
|
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||||
|
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||||
|
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||||
|
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||||
|
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||||
|
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||||
|
*
|
||||||
|
* Authors: Gabe Black
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include "arch/sparc/types.hh"
|
||||||
|
#include "cpu/o3/thread_context.hh"
|
||||||
|
|
||||||
|
template <class Impl>
|
||||||
|
class SparcTC : public O3ThreadContext<Impl>
|
||||||
|
{
|
||||||
|
public:
|
||||||
|
#if FULL_SYSTEM
|
||||||
|
/** Returns a pointer to the ITB. */
|
||||||
|
virtual SparcISA::ITB *getITBPtr() { return this->cpu->itb; }
|
||||||
|
|
||||||
|
/** Returns a pointer to the DTB. */
|
||||||
|
virtual SparcISA::DTB *getDTBPtr() { return this->cpu->dtb; }
|
||||||
|
|
||||||
|
/** Returns pointer to the quiesce event. */
|
||||||
|
virtual EndQuiesceEvent *getQuiesceEvent()
|
||||||
|
{
|
||||||
|
return this->thread->quiesceEvent;
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
virtual uint64_t readNextNPC()
|
||||||
|
{
|
||||||
|
return this->cpu->readNextNPC(this->thread->readTid());
|
||||||
|
}
|
||||||
|
|
||||||
|
virtual void setNextNPC(uint64_t val)
|
||||||
|
{
|
||||||
|
this->cpu->setNextNPC(val, this->thread->readTid());
|
||||||
|
}
|
||||||
|
|
||||||
|
virtual void changeRegFileContext(TheISA::RegContextParam param,
|
||||||
|
TheISA::RegContextVal val)
|
||||||
|
{
|
||||||
|
panic("This doesn't make sense!\n");
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/** This function exits the thread context in the CPU and returns
|
||||||
|
* 1 if the CPU has no more active threads (meaning it's OK to exit);
|
||||||
|
* Used in syscall-emulation mode when a thread executes the 'exit'
|
||||||
|
* syscall.
|
||||||
|
*/
|
||||||
|
virtual int exit()
|
||||||
|
{
|
||||||
|
this->deallocate();
|
||||||
|
|
||||||
|
// If there are still threads executing in the system
|
||||||
|
if (this->cpu->numActiveThreads())
|
||||||
|
return 0; // don't exit simulation
|
||||||
|
else
|
||||||
|
return 1; // exit simulation
|
||||||
|
}
|
||||||
|
};
|
Loading…
Reference in a new issue