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ARM: Fix Uncachable TLB requests and decoding of xn bit

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This commit is contained in:
Gene Wu 2010-08-23 11:18:41 -05:00
parent 4b9de42439
commit f29e09746a
3 changed files with 11 additions and 3 deletions
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6
src/arch/arm/table_walker.cc
View file

@ -165,8 +165,12 @@ TableWalker::walk(RequestPtr _req, ThreadContext *_tc, uint8_t _cid, TLB::Mode _
assert(stateQueue.size() < 5);
currState = NULL;
} else {
Request::Flags flag = 0;
if (currState->sctlr.c == 0){
flag = Request::UNCACHEABLE;
}
port->dmaAction(MemCmd::ReadReq, l1desc_addr, sizeof(uint32_t),
NULL, (uint8_t*)&currState->l1Desc.data, (Tick)0);
NULL, (uint8_t*)&currState->l1Desc.data, (Tick)0, flag);
doL1Descriptor();
f = currState->fault;
}

4
src/arch/arm/table_walker.hh
View file

@ -107,13 +107,13 @@ class TableWalker : public MemObject
/** Is the translation global (no asid used)? */
bool global() const
{
return bits(data, 4);
return bits(data, 17);
}
/** Is the translation not allow execution? */
bool xn() const
{
return bits(data, 17);
return bits(data, 4);
}
/** Three bit access protection flags */

4
src/arch/arm/tlb.cc
View file

@ -363,6 +363,10 @@ TLB::translateFs(RequestPtr req, ThreadContext *tc, Mode mode,
req->setFlags(Request::UNCACHEABLE);
return NoFault;
}
if ((req->isInstFetch() && (!sctlr.i)) ||
((!req->isInstFetch()) && (!sctlr.c))){
req->setFlags(Request::UNCACHEABLE);
}
if (!is_fetch) {
assert(flags & MustBeOne);
if (sctlr.a || !(flags & AllowUnaligned)) {