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config: fs.py: move creating of test/drive systems to functions

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The code that creates test and drive systems is being moved to separate
functions so as to make the code more readable.  Ultimately the two
functions would be combined so that the replicated code is eliminated.
This commit is contained in:
Nilay Vaish 2014-03-20 09:14:08 -05:00
parent d5b5d89b34
commit f2059f8399
1 changed files with 151 additions and 140 deletions
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155
configs/example/fs.py
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@ -63,24 +63,6 @@ import MemConfig
from Caches import * from Caches import *
import Options import Options
parser = optparse.OptionParser()
Options.addCommonOptions(parser)
Options.addFSOptions(parser)
# Add the ruby specific and protocol specific options
if '--ruby' in sys.argv:
Ruby.define_options(parser)
(options, args) = parser.parse_args()
if args:
print "Error: script doesn't take any positional arguments"
sys.exit(1)
# driver system CPU is always simple... note this is an assignment of
# a class, not an instance.
DriveCPUClass = AtomicSimpleCPU
drive_mem_mode = 'atomic'
# Check if KVM support has been enabled, we might need to do VM # Check if KVM support has been enabled, we might need to do VM
# configuration if that's the case. # configuration if that's the case.
@ -89,88 +71,65 @@ def is_kvm_cpu(cpu_class):
return have_kvm_support and cpu_class != None and \ return have_kvm_support and cpu_class != None and \
issubclass(cpu_class, BaseKvmCPU) issubclass(cpu_class, BaseKvmCPU)
# system under test can be any CPU def build_test_system(np):
(TestCPUClass, test_mem_mode, FutureClass) = Simulation.setCPUClass(options) if buildEnv['TARGET_ISA'] == "alpha":
# Match the memories with the CPUs, the driver system always simple,
# and based on the options for the test system
DriveMemClass = SimpleMemory
TestMemClass = Simulation.setMemClass(options)
if options.benchmark:
try:
bm = Benchmarks[options.benchmark]
except KeyError:
print "Error benchmark %s has not been defined." % options.benchmark
print "Valid benchmarks are: %s" % DefinedBenchmarks
sys.exit(1)
else:
if options.dual:
bm = [SysConfig(disk=options.disk_image, mem=options.mem_size),
SysConfig(disk=options.disk_image, mem=options.mem_size)]
else:
bm = [SysConfig(disk=options.disk_image, mem=options.mem_size)]
np = options.num_cpus
if buildEnv['TARGET_ISA'] == "alpha":
test_sys = makeLinuxAlphaSystem(test_mem_mode, bm[0], options.ruby) test_sys = makeLinuxAlphaSystem(test_mem_mode, bm[0], options.ruby)
elif buildEnv['TARGET_ISA'] == "mips": elif buildEnv['TARGET_ISA'] == "mips":
test_sys = makeLinuxMipsSystem(test_mem_mode, bm[0]) test_sys = makeLinuxMipsSystem(test_mem_mode, bm[0])
elif buildEnv['TARGET_ISA'] == "sparc": elif buildEnv['TARGET_ISA'] == "sparc":
test_sys = makeSparcSystem(test_mem_mode, bm[0]) test_sys = makeSparcSystem(test_mem_mode, bm[0])
elif buildEnv['TARGET_ISA'] == "x86": elif buildEnv['TARGET_ISA'] == "x86":
test_sys = makeLinuxX86System(test_mem_mode, options.num_cpus, bm[0], test_sys = makeLinuxX86System(test_mem_mode, options.num_cpus, bm[0],
options.ruby) options.ruby)
elif buildEnv['TARGET_ISA'] == "arm": elif buildEnv['TARGET_ISA'] == "arm":
test_sys = makeArmSystem(test_mem_mode, options.machine_type, bm[0], test_sys = makeArmSystem(test_mem_mode, options.machine_type, bm[0],
options.dtb_filename, options.dtb_filename,
bare_metal=options.bare_metal) bare_metal=options.bare_metal)
if options.enable_context_switch_stats_dump: if options.enable_context_switch_stats_dump:
test_sys.enable_context_switch_stats_dump = True test_sys.enable_context_switch_stats_dump = True
else: else:
fatal("Incapable of building %s full system!", buildEnv['TARGET_ISA']) fatal("Incapable of building %s full system!", buildEnv['TARGET_ISA'])
# Set the cache line size for the entire system # Set the cache line size for the entire system
test_sys.cache_line_size = options.cacheline_size test_sys.cache_line_size = options.cacheline_size
# Create a top-level voltage domain # Create a top-level voltage domain
test_sys.voltage_domain = VoltageDomain(voltage = options.sys_voltage) test_sys.voltage_domain = VoltageDomain(voltage = options.sys_voltage)
# Create a source clock for the system and set the clock period # Create a source clock for the system and set the clock period
test_sys.clk_domain = SrcClockDomain(clock = options.sys_clock, test_sys.clk_domain = SrcClockDomain(clock = options.sys_clock,
voltage_domain = test_sys.voltage_domain) voltage_domain = test_sys.voltage_domain)
# Create a CPU voltage domain # Create a CPU voltage domain
test_sys.cpu_voltage_domain = VoltageDomain() test_sys.cpu_voltage_domain = VoltageDomain()
# Create a source clock for the CPUs and set the clock period # Create a source clock for the CPUs and set the clock period
test_sys.cpu_clk_domain = SrcClockDomain(clock = options.cpu_clock, test_sys.cpu_clk_domain = SrcClockDomain(clock = options.cpu_clock,
voltage_domain = voltage_domain =
test_sys.cpu_voltage_domain) test_sys.cpu_voltage_domain)
if options.kernel is not None: if options.kernel is not None:
test_sys.kernel = binary(options.kernel) test_sys.kernel = binary(options.kernel)
if options.script is not None: if options.script is not None:
test_sys.readfile = options.script test_sys.readfile = options.script
if options.lpae: if options.lpae:
test_sys.have_lpae = True test_sys.have_lpae = True
if options.virtualisation: if options.virtualisation:
test_sys.have_virtualization = True test_sys.have_virtualization = True
test_sys.init_param = options.init_param test_sys.init_param = options.init_param
# For now, assign all the CPUs to the same clock domain # For now, assign all the CPUs to the same clock domain
test_sys.cpu = [TestCPUClass(clk_domain=test_sys.cpu_clk_domain, cpu_id=i) test_sys.cpu = [TestCPUClass(clk_domain=test_sys.cpu_clk_domain, cpu_id=i)
for i in xrange(np)] for i in xrange(np)]
if is_kvm_cpu(TestCPUClass) or is_kvm_cpu(FutureClass): if is_kvm_cpu(TestCPUClass) or is_kvm_cpu(FutureClass):
test_sys.vm = KvmVM() test_sys.vm = KvmVM()
if options.ruby: if options.ruby:
# Check for timing mode because ruby does not support atomic accesses # Check for timing mode because ruby does not support atomic accesses
if not (options.cpu_type == "detailed" or options.cpu_type == "timing"): if not (options.cpu_type == "detailed" or options.cpu_type == "timing"):
print >> sys.stderr, "Ruby requires TimingSimpleCPU or O3CPU!!" print >> sys.stderr, "Ruby requires TimingSimpleCPU or O3CPU!!"
@ -203,13 +162,13 @@ if options.ruby:
test_sys.ruby._cpu_ruby_ports[i].access_phys_mem = True test_sys.ruby._cpu_ruby_ports[i].access_phys_mem = True
# Create the appropriate memory controllers and connect them to the # Create the appropriate memory controllers
# PIO bus # and connect them to the IO bus
test_sys.mem_ctrls = [TestMemClass(range = r) for r in test_sys.mem_ranges] test_sys.mem_ctrls = [TestMemClass(range = r) for r in test_sys.mem_ranges]
for i in xrange(len(test_sys.mem_ctrls)): for i in xrange(len(test_sys.mem_ctrls)):
test_sys.mem_ctrls[i].port = test_sys.iobus.master test_sys.mem_ctrls[i].port = test_sys.iobus.master
else: else:
if options.caches or options.l2cache: if options.caches or options.l2cache:
# By default the IOCache runs at the system clock # By default the IOCache runs at the system clock
test_sys.iocache = IOCache(addr_ranges = test_sys.mem_ranges) test_sys.iocache = IOCache(addr_ranges = test_sys.mem_ranges)
@ -237,7 +196,15 @@ else:
CacheConfig.config_cache(options, test_sys) CacheConfig.config_cache(options, test_sys)
MemConfig.config_mem(options, test_sys) MemConfig.config_mem(options, test_sys)
if len(bm) == 2: return test_sys
def build_drive_system(np):
# driver system CPU is always simple, so is the memory
# Note this is an assignment of a class, not an instance.
DriveCPUClass = AtomicSimpleCPU
drive_mem_mode = 'atomic'
DriveMemClass = SimpleMemory
if buildEnv['TARGET_ISA'] == 'alpha': if buildEnv['TARGET_ISA'] == 'alpha':
drive_sys = makeLinuxAlphaSystem(drive_mem_mode, bm[1]) drive_sys = makeLinuxAlphaSystem(drive_mem_mode, bm[1])
elif buildEnv['TARGET_ISA'] == 'mips': elif buildEnv['TARGET_ISA'] == 'mips':
@ -253,7 +220,8 @@ if len(bm) == 2:
drive_sys.voltage_domain = VoltageDomain(voltage = options.sys_voltage) drive_sys.voltage_domain = VoltageDomain(voltage = options.sys_voltage)
# Create a source clock for the system and set the clock period # Create a source clock for the system and set the clock period
drive_sys.clk_domain = SrcClockDomain(clock = options.sys_clock) drive_sys.clk_domain = SrcClockDomain(clock = options.sys_clock,
voltage_domain = drive_sys.voltage_domain)
# Create a CPU voltage domain # Create a CPU voltage domain
drive_sys.cpu_voltage_domain = VoltageDomain() drive_sys.cpu_voltage_domain = VoltageDomain()
@ -289,6 +257,49 @@ if len(bm) == 2:
drive_sys.mem_ctrls[i].port = drive_sys.membus.master drive_sys.mem_ctrls[i].port = drive_sys.membus.master
drive_sys.init_param = options.init_param drive_sys.init_param = options.init_param
return drive_sys
# Add options
parser = optparse.OptionParser()
Options.addCommonOptions(parser)
Options.addFSOptions(parser)
# Add the ruby specific and protocol specific options
if '--ruby' in sys.argv:
Ruby.define_options(parser)
(options, args) = parser.parse_args()
if args:
print "Error: script doesn't take any positional arguments"
sys.exit(1)
# system under test can be any CPU
(TestCPUClass, test_mem_mode, FutureClass) = Simulation.setCPUClass(options)
# Match the memories with the CPUs, based on the options for the test system
TestMemClass = Simulation.setMemClass(options)
if options.benchmark:
try:
bm = Benchmarks[options.benchmark]
except KeyError:
print "Error benchmark %s has not been defined." % options.benchmark
print "Valid benchmarks are: %s" % DefinedBenchmarks
sys.exit(1)
else:
if options.dual:
bm = [SysConfig(disk=options.disk_image, mem=options.mem_size),
SysConfig(disk=options.disk_image, mem=options.mem_size)]
else:
bm = [SysConfig(disk=options.disk_image, mem=options.mem_size)]
np = options.num_cpus
test_sys = build_test_system(np)
if len(bm) == 2:
drive_sys = build_drive_system(np)
root = makeDualRoot(True, test_sys, drive_sys, options.etherdump) root = makeDualRoot(True, test_sys, drive_sys, options.etherdump)
elif len(bm) == 1: elif len(bm) == 1:
root = Root(full_system=True, system=test_sys) root = Root(full_system=True, system=test_sys)