config: fs.py: move creating of test/drive systems to functions
The code that creates test and drive systems is being moved to separate functions so as to make the code more readable. Ultimately the two functions would be combined so that the replicated code is eliminated.
This commit is contained in:
Nilay Vaish
parent
d5b5d89b34
commit
f2059f8399
1 changed files with 151 additions and 140 deletions
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@ -63,24 +63,6 @@ import MemConfig
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from Caches import *
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import Options
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parser = optparse.OptionParser()
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Options.addCommonOptions(parser)
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Options.addFSOptions(parser)
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# Add the ruby specific and protocol specific options
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if '--ruby' in sys.argv:
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Ruby.define_options(parser)
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(options, args) = parser.parse_args()
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if args:
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print "Error: script doesn't take any positional arguments"
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sys.exit(1)
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# driver system CPU is always simple... note this is an assignment of
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# a class, not an instance.
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DriveCPUClass = AtomicSimpleCPU
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drive_mem_mode = 'atomic'
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# Check if KVM support has been enabled, we might need to do VM
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# configuration if that's the case.
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@ -89,155 +71,140 @@ def is_kvm_cpu(cpu_class):
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return have_kvm_support and cpu_class != None and \
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issubclass(cpu_class, BaseKvmCPU)
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# system under test can be any CPU
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(TestCPUClass, test_mem_mode, FutureClass) = Simulation.setCPUClass(options)
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# Match the memories with the CPUs, the driver system always simple,
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# and based on the options for the test system
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DriveMemClass = SimpleMemory
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TestMemClass = Simulation.setMemClass(options)
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if options.benchmark:
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try:
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bm = Benchmarks[options.benchmark]
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except KeyError:
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print "Error benchmark %s has not been defined." % options.benchmark
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print "Valid benchmarks are: %s" % DefinedBenchmarks
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sys.exit(1)
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else:
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if options.dual:
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bm = [SysConfig(disk=options.disk_image, mem=options.mem_size),
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SysConfig(disk=options.disk_image, mem=options.mem_size)]
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def build_test_system(np):
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if buildEnv['TARGET_ISA'] == "alpha":
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test_sys = makeLinuxAlphaSystem(test_mem_mode, bm[0], options.ruby)
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elif buildEnv['TARGET_ISA'] == "mips":
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test_sys = makeLinuxMipsSystem(test_mem_mode, bm[0])
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elif buildEnv['TARGET_ISA'] == "sparc":
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test_sys = makeSparcSystem(test_mem_mode, bm[0])
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elif buildEnv['TARGET_ISA'] == "x86":
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test_sys = makeLinuxX86System(test_mem_mode, options.num_cpus, bm[0],
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options.ruby)
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elif buildEnv['TARGET_ISA'] == "arm":
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test_sys = makeArmSystem(test_mem_mode, options.machine_type, bm[0],
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options.dtb_filename,
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bare_metal=options.bare_metal)
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if options.enable_context_switch_stats_dump:
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test_sys.enable_context_switch_stats_dump = True
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else:
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bm = [SysConfig(disk=options.disk_image, mem=options.mem_size)]
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fatal("Incapable of building %s full system!", buildEnv['TARGET_ISA'])
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np = options.num_cpus
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# Set the cache line size for the entire system
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test_sys.cache_line_size = options.cacheline_size
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if buildEnv['TARGET_ISA'] == "alpha":
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test_sys = makeLinuxAlphaSystem(test_mem_mode, bm[0], options.ruby)
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elif buildEnv['TARGET_ISA'] == "mips":
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test_sys = makeLinuxMipsSystem(test_mem_mode, bm[0])
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elif buildEnv['TARGET_ISA'] == "sparc":
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test_sys = makeSparcSystem(test_mem_mode, bm[0])
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elif buildEnv['TARGET_ISA'] == "x86":
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test_sys = makeLinuxX86System(test_mem_mode, options.num_cpus, bm[0],
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options.ruby)
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elif buildEnv['TARGET_ISA'] == "arm":
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test_sys = makeArmSystem(test_mem_mode, options.machine_type, bm[0],
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options.dtb_filename,
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bare_metal=options.bare_metal)
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if options.enable_context_switch_stats_dump:
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test_sys.enable_context_switch_stats_dump = True
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else:
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fatal("Incapable of building %s full system!", buildEnv['TARGET_ISA'])
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# Create a top-level voltage domain
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test_sys.voltage_domain = VoltageDomain(voltage = options.sys_voltage)
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# Set the cache line size for the entire system
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test_sys.cache_line_size = options.cacheline_size
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# Create a source clock for the system and set the clock period
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test_sys.clk_domain = SrcClockDomain(clock = options.sys_clock,
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voltage_domain = test_sys.voltage_domain)
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# Create a top-level voltage domain
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test_sys.voltage_domain = VoltageDomain(voltage = options.sys_voltage)
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# Create a CPU voltage domain
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test_sys.cpu_voltage_domain = VoltageDomain()
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# Create a source clock for the system and set the clock period
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test_sys.clk_domain = SrcClockDomain(clock = options.sys_clock,
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voltage_domain = test_sys.voltage_domain)
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# Create a source clock for the CPUs and set the clock period
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test_sys.cpu_clk_domain = SrcClockDomain(clock = options.cpu_clock,
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voltage_domain =
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test_sys.cpu_voltage_domain)
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# Create a CPU voltage domain
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test_sys.cpu_voltage_domain = VoltageDomain()
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if options.kernel is not None:
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test_sys.kernel = binary(options.kernel)
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# Create a source clock for the CPUs and set the clock period
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test_sys.cpu_clk_domain = SrcClockDomain(clock = options.cpu_clock,
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voltage_domain =
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test_sys.cpu_voltage_domain)
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if options.script is not None:
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test_sys.readfile = options.script
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if options.kernel is not None:
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test_sys.kernel = binary(options.kernel)
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if options.lpae:
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test_sys.have_lpae = True
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if options.script is not None:
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test_sys.readfile = options.script
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if options.virtualisation:
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test_sys.have_virtualization = True
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if options.lpae:
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test_sys.have_lpae = True
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test_sys.init_param = options.init_param
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if options.virtualisation:
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test_sys.have_virtualization = True
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# For now, assign all the CPUs to the same clock domain
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test_sys.cpu = [TestCPUClass(clk_domain=test_sys.cpu_clk_domain, cpu_id=i)
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for i in xrange(np)]
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test_sys.init_param = options.init_param
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if is_kvm_cpu(TestCPUClass) or is_kvm_cpu(FutureClass):
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test_sys.vm = KvmVM()
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# For now, assign all the CPUs to the same clock domain
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test_sys.cpu = [TestCPUClass(clk_domain=test_sys.cpu_clk_domain, cpu_id=i)
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for i in xrange(np)]
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if options.ruby:
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# Check for timing mode because ruby does not support atomic accesses
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if not (options.cpu_type == "detailed" or options.cpu_type == "timing"):
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print >> sys.stderr, "Ruby requires TimingSimpleCPU or O3CPU!!"
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sys.exit(1)
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if is_kvm_cpu(TestCPUClass) or is_kvm_cpu(FutureClass):
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test_sys.vm = KvmVM()
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Ruby.create_system(options, test_sys, test_sys.iobus, test_sys._dma_ports)
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if options.ruby:
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# Check for timing mode because ruby does not support atomic accesses
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if not (options.cpu_type == "detailed" or options.cpu_type == "timing"):
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print >> sys.stderr, "Ruby requires TimingSimpleCPU or O3CPU!!"
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sys.exit(1)
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# Create a seperate clock domain for Ruby
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test_sys.ruby.clk_domain = SrcClockDomain(clock = options.ruby_clock,
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voltage_domain = test_sys.voltage_domain)
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Ruby.create_system(options, test_sys, test_sys.iobus, test_sys._dma_ports)
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for (i, cpu) in enumerate(test_sys.cpu):
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#
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# Tie the cpu ports to the correct ruby system ports
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#
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cpu.clk_domain = test_sys.cpu_clk_domain
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cpu.createThreads()
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cpu.createInterruptController()
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# Create a seperate clock domain for Ruby
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test_sys.ruby.clk_domain = SrcClockDomain(clock = options.ruby_clock,
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voltage_domain = test_sys.voltage_domain)
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cpu.icache_port = test_sys.ruby._cpu_ruby_ports[i].slave
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cpu.dcache_port = test_sys.ruby._cpu_ruby_ports[i].slave
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for (i, cpu) in enumerate(test_sys.cpu):
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#
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# Tie the cpu ports to the correct ruby system ports
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#
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cpu.clk_domain = test_sys.cpu_clk_domain
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cpu.createThreads()
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cpu.createInterruptController()
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if buildEnv['TARGET_ISA'] == "x86":
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cpu.itb.walker.port = test_sys.ruby._cpu_ruby_ports[i].slave
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cpu.dtb.walker.port = test_sys.ruby._cpu_ruby_ports[i].slave
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cpu.icache_port = test_sys.ruby._cpu_ruby_ports[i].slave
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cpu.dcache_port = test_sys.ruby._cpu_ruby_ports[i].slave
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cpu.interrupts.pio = test_sys.ruby._cpu_ruby_ports[i].master
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cpu.interrupts.int_master = test_sys.ruby._cpu_ruby_ports[i].slave
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cpu.interrupts.int_slave = test_sys.ruby._cpu_ruby_ports[i].master
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if buildEnv['TARGET_ISA'] == "x86":
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cpu.itb.walker.port = test_sys.ruby._cpu_ruby_ports[i].slave
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cpu.dtb.walker.port = test_sys.ruby._cpu_ruby_ports[i].slave
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test_sys.ruby._cpu_ruby_ports[i].access_phys_mem = True
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cpu.interrupts.pio = test_sys.ruby._cpu_ruby_ports[i].master
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cpu.interrupts.int_master = test_sys.ruby._cpu_ruby_ports[i].slave
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cpu.interrupts.int_slave = test_sys.ruby._cpu_ruby_ports[i].master
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# Create the appropriate memory controllers
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# and connect them to the IO bus
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test_sys.mem_ctrls = [TestMemClass(range = r) for r in test_sys.mem_ranges]
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for i in xrange(len(test_sys.mem_ctrls)):
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test_sys.mem_ctrls[i].port = test_sys.iobus.master
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test_sys.ruby._cpu_ruby_ports[i].access_phys_mem = True
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# Create the appropriate memory controllers and connect them to the
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# PIO bus
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test_sys.mem_ctrls = [TestMemClass(range = r) for r in test_sys.mem_ranges]
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for i in xrange(len(test_sys.mem_ctrls)):
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test_sys.mem_ctrls[i].port = test_sys.iobus.master
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else:
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if options.caches or options.l2cache:
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# By default the IOCache runs at the system clock
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test_sys.iocache = IOCache(addr_ranges = test_sys.mem_ranges)
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test_sys.iocache.cpu_side = test_sys.iobus.master
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test_sys.iocache.mem_side = test_sys.membus.slave
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else:
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test_sys.iobridge = Bridge(delay='50ns', ranges = test_sys.mem_ranges)
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test_sys.iobridge.slave = test_sys.iobus.master
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test_sys.iobridge.master = test_sys.membus.slave
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if options.caches or options.l2cache:
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# By default the IOCache runs at the system clock
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test_sys.iocache = IOCache(addr_ranges = test_sys.mem_ranges)
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test_sys.iocache.cpu_side = test_sys.iobus.master
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test_sys.iocache.mem_side = test_sys.membus.slave
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else:
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test_sys.iobridge = Bridge(delay='50ns', ranges = test_sys.mem_ranges)
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test_sys.iobridge.slave = test_sys.iobus.master
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test_sys.iobridge.master = test_sys.membus.slave
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# Sanity check
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if options.fastmem:
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if TestCPUClass != AtomicSimpleCPU:
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fatal("Fastmem can only be used with atomic CPU!")
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if (options.caches or options.l2cache):
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fatal("You cannot use fastmem in combination with caches!")
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for i in xrange(np):
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# Sanity check
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if options.fastmem:
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test_sys.cpu[i].fastmem = True
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if options.checker:
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test_sys.cpu[i].addCheckerCpu()
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test_sys.cpu[i].createThreads()
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if TestCPUClass != AtomicSimpleCPU:
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fatal("Fastmem can only be used with atomic CPU!")
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if (options.caches or options.l2cache):
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fatal("You cannot use fastmem in combination with caches!")
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CacheConfig.config_cache(options, test_sys)
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MemConfig.config_mem(options, test_sys)
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for i in xrange(np):
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if options.fastmem:
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test_sys.cpu[i].fastmem = True
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if options.checker:
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test_sys.cpu[i].addCheckerCpu()
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test_sys.cpu[i].createThreads()
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CacheConfig.config_cache(options, test_sys)
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MemConfig.config_mem(options, test_sys)
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return test_sys
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def build_drive_system(np):
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# driver system CPU is always simple, so is the memory
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# Note this is an assignment of a class, not an instance.
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DriveCPUClass = AtomicSimpleCPU
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drive_mem_mode = 'atomic'
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DriveMemClass = SimpleMemory
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if len(bm) == 2:
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if buildEnv['TARGET_ISA'] == 'alpha':
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drive_sys = makeLinuxAlphaSystem(drive_mem_mode, bm[1])
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elif buildEnv['TARGET_ISA'] == 'mips':
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@ -253,7 +220,8 @@ if len(bm) == 2:
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drive_sys.voltage_domain = VoltageDomain(voltage = options.sys_voltage)
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# Create a source clock for the system and set the clock period
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drive_sys.clk_domain = SrcClockDomain(clock = options.sys_clock)
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drive_sys.clk_domain = SrcClockDomain(clock = options.sys_clock,
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voltage_domain = drive_sys.voltage_domain)
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# Create a CPU voltage domain
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drive_sys.cpu_voltage_domain = VoltageDomain()
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@ -289,6 +257,49 @@ if len(bm) == 2:
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drive_sys.mem_ctrls[i].port = drive_sys.membus.master
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drive_sys.init_param = options.init_param
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return drive_sys
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# Add options
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parser = optparse.OptionParser()
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Options.addCommonOptions(parser)
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Options.addFSOptions(parser)
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# Add the ruby specific and protocol specific options
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if '--ruby' in sys.argv:
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Ruby.define_options(parser)
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(options, args) = parser.parse_args()
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if args:
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print "Error: script doesn't take any positional arguments"
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sys.exit(1)
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# system under test can be any CPU
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(TestCPUClass, test_mem_mode, FutureClass) = Simulation.setCPUClass(options)
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# Match the memories with the CPUs, based on the options for the test system
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TestMemClass = Simulation.setMemClass(options)
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if options.benchmark:
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try:
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bm = Benchmarks[options.benchmark]
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except KeyError:
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print "Error benchmark %s has not been defined." % options.benchmark
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print "Valid benchmarks are: %s" % DefinedBenchmarks
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sys.exit(1)
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else:
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if options.dual:
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bm = [SysConfig(disk=options.disk_image, mem=options.mem_size),
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SysConfig(disk=options.disk_image, mem=options.mem_size)]
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else:
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bm = [SysConfig(disk=options.disk_image, mem=options.mem_size)]
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np = options.num_cpus
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test_sys = build_test_system(np)
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if len(bm) == 2:
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drive_sys = build_drive_system(np)
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root = makeDualRoot(True, test_sys, drive_sys, options.etherdump)
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elif len(bm) == 1:
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root = Root(full_system=True, system=test_sys)
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