inorder: check for interrupts each tick
use a dummy instruction to facilitate the squash after the interrupts trap
This commit is contained in:
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0bfdf342da
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f1c3691356
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@ -350,6 +350,16 @@ InOrderCPU::InOrderCPU(Params *params)
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asid[tid]);
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dummyReq[tid] = new ResourceRequest(resPool->getResource(0));
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#if FULL_SYSTEM
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// Use this dummy inst to force squashing behind every instruction
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// in pipeline
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dummyTrapInst[tid] = new InOrderDynInst(this, NULL, 0, 0, 0);
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dummyTrapInst[tid]->seqNum = 0;
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dummyTrapInst[tid]->squashSeqNum = 0;
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dummyTrapInst[tid]->setTid(tid);
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#endif
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}
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dummyReqInst = new InOrderDynInst(this, NULL, 0, 0, 0);
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@ -687,6 +697,8 @@ InOrderCPU::tick()
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pipes_idle = pipes_idle && pipelineStage[stNum]->idle;
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}
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checkForInterrupts();
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if (pipes_idle)
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idleCycles++;
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else
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@ -800,6 +812,43 @@ InOrderCPU::simPalCheck(int palFunc, ThreadID tid)
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return true;
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}
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void
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InOrderCPU::checkForInterrupts()
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{
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for (int i = 0; i < threadContexts.size(); i++) {
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ThreadContext *tc = threadContexts[i];
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if (interrupts->checkInterrupts(tc)) {
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Fault interrupt = interrupts->getInterrupt(tc);
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if (interrupt != NoFault) {
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DPRINTF(Interrupt, "Processing Intterupt for [tid:%i].\n",
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tc->threadId());
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ThreadID tid = tc->threadId();
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interrupts->updateIntrInfo(tc);
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// Squash from Last Stage in Pipeline
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unsigned last_stage = NumStages - 1;
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dummyTrapInst[tid]->squashingStage = last_stage;
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pipelineStage[last_stage]->setupSquash(dummyTrapInst[tid],
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tid);
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// By default, setupSquash will always squash from stage + 1
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pipelineStage[BackEndStartStage - 1]->setupSquash(dummyTrapInst[tid],
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tid);
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// Schedule Squash Through-out Resource Pool
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resPool->scheduleEvent(
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(InOrderCPU::CPUEventType)ResourcePool::SquashAll,
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dummyTrapInst[tid], 0);
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// Finally, Setup Trap to happen at end of cycle
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trapContext(interrupt, tid, dummyTrapInst[tid]);
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}
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}
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}
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}
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Fault
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InOrderCPU::getInterrupts()
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@ -253,6 +253,7 @@ class InOrderCPU : public BaseCPU
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DynInstPtr dummyInst[ThePipeline::MaxThreads];
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DynInstPtr dummyBufferInst;
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DynInstPtr dummyReqInst;
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DynInstPtr dummyTrapInst[ThePipeline::MaxThreads];
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/** Used by resources to signify a denied access to a resource. */
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ResourceRequest *dummyReq[ThePipeline::MaxThreads];
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@ -414,6 +415,8 @@ class InOrderCPU : public BaseCPU
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bool simPalCheck(int palFunc, ThreadID tid);
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void checkForInterrupts();
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/** Returns the Fault for any valid interrupt. */
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Fault getInterrupts();
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@ -364,9 +364,10 @@ PipelineStage::setupSquash(DynInstPtr inst, ThreadID tid)
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toPrevStages->stageInfo[squash_stage][tid].doneSeqNum =
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squash_seq_num;
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DPRINTF(InOrderStage, "[tid:%i]: Squashing after [sn:%i], "
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"due to [sn:%i] %s.\n", tid, squash_seq_num,
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inst->seqNum, inst->instName());
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DPRINTF(InOrderStage, "[tid:%i]: Setting up squashing after "
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"[sn:%i], due to [sn:%i] %s. Squash-Start-Stage:%i\n",
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tid, squash_seq_num, inst->seqNum, inst->instName(),
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squash_stage);
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// Save squash num for later stage use
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cpu->lastSquashCycle[tid] = curTick();
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@ -302,6 +302,8 @@ void
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Resource::squash(DynInstPtr inst, int stage_num, InstSeqNum squash_seq_num,
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ThreadID tid)
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{
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//@todo: check squash seq num before squashing. can save time going
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// through this function.
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for (int i = 0; i < width; i++) {
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ResReqPtr req_ptr = reqs[i];
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DynInstPtr inst = req_ptr->getInst();
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@ -1248,7 +1248,8 @@ void
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CacheUnit::squash(DynInstPtr inst, int stage_num,
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InstSeqNum squash_seq_num, ThreadID tid)
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{
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if (tlbBlockSeqNum[tid] > squash_seq_num) {
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if (tlbBlockSeqNum[tid] &&
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tlbBlockSeqNum[tid] > squash_seq_num) {
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DPRINTF(InOrderCachePort, "Releasing TLB Block due to "
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" squash after [sn:%i].\n", squash_seq_num);
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tlbBlocked[tid] = false;
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@ -49,6 +49,8 @@ FetchSeqUnit::FetchSeqUnit(std::string res_name, int res_id, int res_width,
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pcValid[tid] = false;
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pcBlockStage[tid] = 0;
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//@todo: Use CPU's squashSeqNum here instead of maintaining our own
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// state
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squashSeqNum[tid] = (InstSeqNum)-1;
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lastSquashCycle[tid] = 0;
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}
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@ -164,75 +166,77 @@ FetchSeqUnit::squash(DynInstPtr inst, int squash_stage,
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squashSeqNum[tid] = squash_seq_num;
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lastSquashCycle[tid] = curTick();
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if (inst->fault != NoFault) {
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// A Trap Caused This Fault and will update the pc state
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// when done trapping
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DPRINTF(InOrderFetchSeq, "[tid:%i] Blocking due to fault @ "
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"[sn:%i].%s %s \n", inst->seqNum,
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inst->instName(), inst->pcState());
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pcValid[tid] = false;
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} else {
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TheISA::PCState nextPC;
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assert(inst->staticInst);
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if (inst->isControl()) {
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nextPC = inst->readPredTarg();
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if (inst->staticInst) {
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if (inst->fault != NoFault) {
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// A Trap Caused This Fault and will update the pc state
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// when done trapping
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DPRINTF(InOrderFetchSeq, "[tid:%i] Blocking due to fault @ "
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"[sn:%i].%s %s \n", inst->seqNum,
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inst->instName(), inst->pcState());
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pcValid[tid] = false;
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} else {
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TheISA::PCState nextPC;
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assert(inst->staticInst);
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if (inst->isControl()) {
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nextPC = inst->readPredTarg();
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// If we are already fetching this PC then advance to next PC
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// =======
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// This should handle ISAs w/delay slots and annulled delay
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// slots to figure out which is the next PC to fetch after
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// a mispredict
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DynInstPtr bdelay_inst = NULL;
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ListIt bdelay_it;
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if (inst->onInstList) {
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bdelay_it = inst->getInstListIt();
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bdelay_it++;
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} else {
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InstSeqNum branch_delay_num = inst->seqNum + 1;
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bdelay_it = cpu->findInst(branch_delay_num, tid);
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}
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if (bdelay_it != cpu->instList[tid].end()) {
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bdelay_inst = (*bdelay_it);
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}
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if (bdelay_inst) {
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DPRINTF(Resource, "Evaluating %s v. %s\n",
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bdelay_inst->pc, nextPC);
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if (bdelay_inst->pc.instAddr() == nextPC.instAddr()) {
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bdelay_inst->pc = nextPC;
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advancePC(nextPC, inst->staticInst);
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DPRINTF(Resource, "Advanced PC to %s\n", nextPC);
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// If we are already fetching this PC then advance to next PC
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// =======
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// This should handle ISAs w/delay slots and annulled delay
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// slots to figure out which is the next PC to fetch after
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// a mispredict
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DynInstPtr bdelay_inst = NULL;
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ListIt bdelay_it;
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if (inst->onInstList) {
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bdelay_it = inst->getInstListIt();
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bdelay_it++;
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} else {
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InstSeqNum branch_delay_num = inst->seqNum + 1;
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bdelay_it = cpu->findInst(branch_delay_num, tid);
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}
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if (bdelay_it != cpu->instList[tid].end()) {
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bdelay_inst = (*bdelay_it);
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}
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if (bdelay_inst) {
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DPRINTF(Resource, "Evaluating %s v. %s\n",
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bdelay_inst->pc, nextPC);
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if (bdelay_inst->pc.instAddr() == nextPC.instAddr()) {
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bdelay_inst->pc = nextPC;
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advancePC(nextPC, inst->staticInst);
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DPRINTF(Resource, "Advanced PC to %s\n", nextPC);
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}
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}
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} else {
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nextPC = inst->pcState();
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advancePC(nextPC, inst->staticInst);
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}
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} else {
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nextPC = inst->pcState();
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advancePC(nextPC, inst->staticInst);
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DPRINTF(InOrderFetchSeq, "[tid:%i]: Setting PC to %s.\n",
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tid, nextPC);
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pc[tid] = nextPC;
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// Unblock Any Stages Waiting for this information to be updated ...
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if (!pcValid[tid]) {
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DPRINTF(InOrderFetchSeq, "[tid:%d]: Setting unblock signal "
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"for stage %i.\n",
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tid, pcBlockStage[tid]);
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// Need to use "fromNextStages" instead of "toPrevStages"
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// because the timebuffer will have already have advanced
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// in the tick function and this squash function will happen after
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// the tick
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cpu->pipelineStage[pcBlockStage[tid]]->
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fromNextStages->stageUnblock[pcBlockStage[tid]][tid] = true;
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}
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pcValid[tid] = true;
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}
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DPRINTF(InOrderFetchSeq, "[tid:%i]: Setting PC to %s.\n",
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tid, nextPC);
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pc[tid] = nextPC;
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// Unblock Any Stages Waiting for this information to be updated ...
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if (!pcValid[tid]) {
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DPRINTF(InOrderFetchSeq, "[tid:%d]: Setting unblock signal "
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"for stage %i.\n",
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tid, pcBlockStage[tid]);
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// Need to use "fromNextStages" instead of "toPrevStages"
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// because the timebuffer will have already have advanced
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// in the tick function and this squash function will happen after
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// the tick
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cpu->pipelineStage[pcBlockStage[tid]]->
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fromNextStages->stageUnblock[pcBlockStage[tid]][tid] = true;
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}
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pcValid[tid] = true;
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}
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}
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}
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Resource::squash(inst, squash_stage, squash_seq_num, tid);
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}
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@ -302,8 +306,6 @@ FetchSeqUnit::trap(Fault fault, ThreadID tid, DynInstPtr inst)
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"%s.\n", tid, pc[tid]);
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DPRINTF(InOrderFetchSeq, "[tid:%i]: Trap updating to PC: "
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"%s.\n", tid, pc[tid]);
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cpu->removePipelineStalls(tid);
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}
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void
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