sanchayanmaity/gem5
1
0
Fork 0
Code Issues Pull requests Projects Releases Packages Wiki Activity

X86: Hook up the IDE controller interrupt line.

Browse source
This commit is contained in:
Gabe Black 2009-02-01 00:25:15 -08:00
parent 18f6c18323
commit f1b43b39a7
2 changed files with 3 additions and 2 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

1
src/dev/x86/SouthBridge.py
View file

@ -87,6 +87,7 @@ class SouthBridge(SimObject):
ide.BAR3LegacyIO = True ide.BAR3LegacyIO = True
ide.BAR4 = 1 ide.BAR4 = 1
ide.Command = 1 ide.Command = 1
ide.InterruptLine = 20
def attachIO(self, bus): def attachIO(self, bus):
# Route interupt signals # Route interupt signals

4
src/dev/x86/pc.cc
View file

@ -127,13 +127,13 @@ Pc::clearConsoleInt()
void void
Pc::postPciInt(int line) Pc::postPciInt(int line)
{ {
panic("Need implementation\n"); southBridge->ioApic->signalInterrupt(line);
} }
void void
Pc::clearPciInt(int line) Pc::clearPciInt(int line)
{ {
panic("Need implementation\n"); warn_once("Tried to clear PCI interrupt %d\n", line);
} }
Addr Addr