X86: Implement a page table walker.
--HG-- extra : convert_revision : 36bab5750100318faa9ba7178dc2e38590053aec
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7 changed files with 293 additions and 10 deletions
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@ -53,12 +53,15 @@
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#
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# Authors: Gabe Black
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from m5.SimObject import SimObject
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from MemObject import MemObject
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from m5.params import *
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class X86TLB(SimObject):
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class X86TLB(MemObject):
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type = 'X86TLB'
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abstract = True
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size = Param.Int("TLB size")
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walker_port = Port("Port for the hardware table walker")
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system = Param.System(Parent.any, "system object")
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class X86DTB(X86TLB):
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type = 'X86DTB'
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@ -72,7 +72,7 @@
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namespace X86ISA {
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TLB::TLB(const Params *p) : SimObject(p), size(p->size)
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TLB::TLB(const Params *p) : MemObject(p), walker(name(), this), size(p->size)
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{
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tlb = new TlbEntry[size];
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std::memset(tlb, 0, sizeof(TlbEntry) * size);
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@ -81,6 +81,140 @@ TLB::TLB(const Params *p) : SimObject(p), size(p->size)
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freeList.push_back(&tlb[x]);
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}
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bool
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TLB::Walker::doNext(uint64_t data, PacketPtr &write)
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{
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assert(state != Ready && state != Waiting);
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write = NULL;
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switch(state) {
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case LongPML4:
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nextState = LongPDP;
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break;
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case LongPDP:
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nextState = LongPD;
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break;
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case LongPD:
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nextState = LongPTE;
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break;
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case LongPTE:
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nextState = Ready;
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return false;
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case PAEPDP:
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nextState = PAEPD;
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break;
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case PAEPD:
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break;
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case PAEPTE:
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nextState = Ready;
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return false;
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case PSEPD:
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break;
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case PD:
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nextState = PTE;
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break;
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case PTE:
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nextState = Ready;
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return false;
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default:
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panic("Unknown page table walker state %d!\n");
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}
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return true;
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}
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void
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TLB::Walker::buildReadPacket(Addr addr)
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{
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readRequest.setPhys(addr, size, PHYSICAL | uncachable ? UNCACHEABLE : 0);
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readPacket.reinitFromRequest();
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}
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TLB::walker::buildWritePacket(Addr addr)
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{
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writeRequest.setPhys(addr, size, PHYSICAL | uncachable ? UNCACHEABLE : 0);
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writePacket.reinitFromRequest();
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bool
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TLB::Walker::WalkerPort::recvTiming(PacketPtr pkt)
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{
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if (pkt->isResponse() && !pkt->wasNacked()) {
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if (pkt->isRead()) {
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assert(packet);
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assert(walker->state == Waiting);
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packet = NULL;
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walker->state = walker->nextState;
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walker->nextState = Ready;
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PacketPtr write;
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if (walker->doNext(pkt, write)) {
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packet = &walker->packet;
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port->sendTiming(packet);
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}
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if (write) {
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writes.push_back(write);
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}
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while (!port->blocked() && writes.size()) {
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if (port->sendTiming(writes.front())) {
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writes.pop_front();
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outstandingWrites++;
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}
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}
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} else {
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outstandingWrites--;
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}
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} else if (pkt->wasNacked()) {
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pkt->reinitNacked();
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if (!sendTiming(pkt)) {
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if (pkt->isWrite()) {
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writes.push_front(pkt);
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}
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}
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}
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return true;
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}
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Tick
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TLB::Walker::WalkerPort::recvAtomic(PacketPtr pkt)
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{
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return 0;
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}
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void
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TLB::Walker::WalkerPort::recvFunctional(PacketPtr pkt)
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{
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return;
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}
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void
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TLB::Walker::WalkerPort::recvStatusChange(Status status)
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{
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if (status == RangeChange) {
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if (!snoopRangeSent) {
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snoopRangeSent = true;
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sendStatusChange(Port::RangeChange);
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}
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return;
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}
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panic("Unexpected recvStatusChange.\n");
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}
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void
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TLB::Walker::WalkerPort::recvRetry()
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{
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retrying = false;
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if (!sendTiming(packet)) {
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retrying = true;
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}
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}
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Port *
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TLB::getPort(const std::string &if_name, int idx)
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{
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if (if_name == "walker_port")
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return &walker.port;
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else
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panic("No tlb port named %s!\n", if_name);
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}
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void
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TLB::insert(Addr vpn, TlbEntry &entry)
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{
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@ -59,10 +59,12 @@
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#define __ARCH_X86_TLB_HH__
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#include <list>
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#include <string>
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#include "arch/x86/pagetable.hh"
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#include "arch/x86/segmentregs.hh"
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#include "config/full_system.hh"
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#include "mem/mem_object.hh"
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#include "mem/request.hh"
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#include "params/X86DTB.hh"
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#include "params/X86ITB.hh"
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@ -76,13 +78,16 @@ namespace X86ISA
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{
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static const unsigned StoreCheck = 1 << NUM_SEGMENTREGS;
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class TLB : public SimObject
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class TLB;
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class TLB : public MemObject
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{
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#if !FULL_SYSTEM
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protected:
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friend class FakeITLBFault;
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friend class FakeDTLBFault;
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#endif
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System * sys;
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public:
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typedef X86TLBParams Params;
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TLB(const Params *p);
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@ -91,6 +96,137 @@ namespace X86ISA
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TlbEntry *lookup(Addr va, bool update_lru = true);
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#if FULL_SYSTEM
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protected:
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class Walker
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{
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public:
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enum State {
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Ready,
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Waiting,
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LongPML4,
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LongPDP,
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LongPD,
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LongPTE,
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PAEPDP,
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PAEPD,
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PAEPTE,
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PSEPD,
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PD,
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PTE
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};
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// Act on the current state and determine what to do next. If the
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// walker has finished updating the TLB, this will return false.
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bool doNext(PacketPtr read, PacketPtr &write);
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// This does an actual load to feed the walker. If we're in
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// atomic mode, this will drive the state machine itself until
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// the TLB is filled. If we're in timing mode, the port getting
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// a reply will drive the machine using this function which will
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// return after starting the memory operation.
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void doMemory(Addr addr);
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// Kick off the state machine.
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void start(bool _uncachable, Addr _vaddr, Addr cr3, State next)
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{
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assert(state == Ready);
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state = Waiting;
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nextState = next;
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// If PAE isn't being used, entries are 4 bytes. Otherwise
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// they're 8.
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if (next == PSEPD || next == PD || next == PTE)
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size = 4;
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else
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size = 8;
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vaddr = _vaddr;
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uncachable = _uncacheable;
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buildPacket(cr3);
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if (state == Enums::timing) {
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port->sendTiming(&packet);
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} else if (state == Enums::atomic) {
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port->sendAtomic(&packet);
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Addr addr;
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while(doNext(packet.get<uint64_t>(), addr)) {
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buildPacket(addr);
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port->sendAtomic(&packet);
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}
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} else {
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panic("Unrecognized memory system mode.\n");
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}
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};
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protected:
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friend class TLB;
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class WalkerPort : public Port
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{
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public:
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WalkerPort(const std::string &_name, Walker * _walker) :
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Port(_name, _walker->tlb), walker(_walker),
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packet(NULL), snoopRangeSent(false), retrying(false)
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{}
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protected:
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Walker * walker;
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PacketPtr packet;
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vector<PacketPtr> writes;
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bool snoopRangeSent;
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bool retrying;
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bool recvTiming(PacketPtr pkt);
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Tick recvAtomic(PacketPtr pkt);
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void recvFunctional(PacketPtr pkt);
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void recvStatusChange(Status status);
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void recvRetry();
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void getDeviceAddressRanges(AddrRangeList &resp,
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bool &snoop)
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{
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resp.clear();
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snoop = true;
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}
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public:
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bool sendTiming(PacketPtr pkt)
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{
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retrying = !Port::sendTiming(pkt);
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return !retrying;
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}
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bool blocked() { return retrying; }
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};
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friend class WalkerPort;
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WalkerPort port;
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Packet packet;
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Request request;
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TLB * tlb;
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State state;
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State nextState;
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int size;
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Addr vaddr;
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public:
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Walker(const std::string &_name, TLB * _tlb) :
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port(_name + "-walker_port", this),
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packet(&request, ReadExReq, Broadcast),
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tlb(_tlb), state(Ready), nextState(Ready)
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{
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}
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};
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Walker walker;
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#endif
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protected:
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int size;
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@ -100,6 +236,8 @@ namespace X86ISA
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EntryList freeList;
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EntryList entryList;
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Port *getPort(const std::string &if_name, int idx = -1);
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void insert(Addr vpn, TlbEntry &entry);
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void invalidateAll();
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@ -100,18 +100,25 @@ class BaseCPU(SimObject):
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_mem_ports = []
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if build_env['TARGET_ISA'] == 'x86':
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itb.walker_port = Port("ITB page table walker port")
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dtb.walker_port = Port("ITB page table walker port")
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_mem_ports = ["itb.walker_port", "dtb.walker_port"]
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def connectMemPorts(self, bus):
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for p in self._mem_ports:
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if p != 'physmem_port':
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exec('self.%s = bus.port' % p)
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def addPrivateSplitL1Caches(self, ic, dc):
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assert(len(self._mem_ports) == 2 or len(self._mem_ports) == 3)
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assert(len(self._mem_ports) < 6)
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self.icache = ic
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self.dcache = dc
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self.icache_port = ic.cpu_side
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self.dcache_port = dc.cpu_side
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self._mem_ports = ['icache.mem_side', 'dcache.mem_side']
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if build_env['TARGET_ISA'] == 'x86':
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self._mem_ports += ["itb.walker_port", "dtb.walker_port"]
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def addTwoLevelCacheHierarchy(self, ic, dc, l2c):
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self.addPrivateSplitL1Caches(ic, dc)
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@ -58,7 +58,7 @@ class DerivO3CPU(BaseCPU):
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cachePorts = Param.Unsigned(200, "Cache Ports")
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icache_port = Port("Instruction Port")
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dcache_port = Port("Data Port")
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_mem_ports = ['icache_port', 'dcache_port']
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_mem_ports = BaseCPU._mem_ports + ['icache_port', 'dcache_port']
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decodeToFetchDelay = Param.Unsigned(1, "Decode to fetch delay")
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renameToFetchDelay = Param.Unsigned(1 ,"Rename to fetch delay")
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@ -41,4 +41,5 @@ class AtomicSimpleCPU(BaseCPU):
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icache_port = Port("Instruction Port")
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dcache_port = Port("Data Port")
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physmem_port = Port("Physical Memory Port")
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_mem_ports = ['icache_port', 'dcache_port', 'physmem_port']
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_mem_ports = BaseCPU._mem_ports + \
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['icache_port', 'dcache_port', 'physmem_port']
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@ -38,4 +38,4 @@ class TimingSimpleCPU(BaseCPU):
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profile = Param.Latency('0ns', "trace the kernel stack")
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icache_port = Port("Instruction Port")
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dcache_port = Port("Data Port")
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_mem_ports = ['icache_port', 'dcache_port']
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_mem_ports = BaseCPU._mem_ports + ['icache_port', 'dcache_port']
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