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Regression: Update statistics for x86 long regression tests

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This patch updates reference statistics for the regression tests. This
update was necessitated by a recent change in behavior of some instructions
in the x86 architecture.
This commit is contained in:
Nilay Vaish 2011-11-17 22:53:56 -06:00
parent f3b4d10a05
commit f171a29118
11 changed files with 2052 additions and 2049 deletions
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9
tests/long/00.gzip/ref/x86/linux/o3-timing/simout
View file

@ -3,10 +3,11 @@ Redirecting stderr to build/X86_SE/tests/opt/long/00.gzip/x86/linux/o3-timing/si
gem5 Simulator System. http://gem5.org gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details. gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Aug 20 2011 13:24:14 gem5 compiled Nov 16 2011 11:08:03
gem5 started Aug 20 2011 13:24:28 gem5 started Nov 17 2011 13:09:16
gem5 executing on zizzer gem5 executing on ribera.cs.wisc.edu
command line: build/X86_SE/gem5.opt -d build/X86_SE/tests/opt/long/00.gzip/x86/linux/o3-timing -re tests/run.py build/X86_SE/tests/opt/long/00.gzip/x86/linux/o3-timing command line: build/X86_SE/gem5.opt -d build/X86_SE/tests/opt/long/00.gzip/x86/linux/o3-timing -re tests/run.py build/X86_SE/tests/opt/long/00.gzip/x86/linux/o3-timing
tests
Global frequency set at 1000000000000 ticks per second Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation... info: Entering event queue @ 0. Starting simulation...
spec_init spec_init
@ -1064,4 +1065,4 @@ Uncompressing Data
Uncompressed data 1048576 bytes in length Uncompressed data 1048576 bytes in length
Uncompressed data compared correctly Uncompressed data compared correctly
Tested 1MB buffer: OK! Tested 1MB buffer: OK!
Exiting @ tick 586755503000 because target called exit() Exiting @ tick 586294224000 because target called exit()

668
tests/long/00.gzip/ref/x86/linux/o3-timing/stats.txt
View file

@ -1,144 +1,144 @@
---------- Begin Simulation Statistics ---------- ---------- Begin Simulation Statistics ----------
sim_seconds 0.586756 # Number of seconds simulated sim_seconds 0.586294 # Number of seconds simulated
sim_ticks 586755503000 # Number of ticks simulated sim_ticks 586294224000 # Number of ticks simulated
sim_freq 1000000000000 # Frequency of simulated ticks sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 143909 # Simulator instruction rate (inst/s) host_inst_rate 112274 # Simulator instruction rate (inst/s)
host_tick_rate 52074943 # Simulator tick rate (ticks/s) host_tick_rate 40595683 # Simulator tick rate (ticks/s)
host_mem_usage 212036 # Number of bytes of host memory used host_mem_usage 244844 # Number of bytes of host memory used
host_seconds 11267.52 # Real time elapsed on the host host_seconds 14442.28 # Real time elapsed on the host
sim_insts 1621493982 # Number of instructions simulated sim_insts 1621493982 # Number of instructions simulated
system.cpu.workload.num_syscalls 48 # Number of system calls system.cpu.workload.num_syscalls 48 # Number of system calls
system.cpu.numCycles 1173511007 # number of cpu cycles simulated system.cpu.numCycles 1172588449 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.BPredUnit.lookups 142841694 # Number of BP lookups system.cpu.BPredUnit.lookups 142448983 # Number of BP lookups
system.cpu.BPredUnit.condPredicted 142841694 # Number of conditional branches predicted system.cpu.BPredUnit.condPredicted 142448983 # Number of conditional branches predicted
system.cpu.BPredUnit.condIncorrect 7891104 # Number of conditional branches incorrect system.cpu.BPredUnit.condIncorrect 7804844 # Number of conditional branches incorrect
system.cpu.BPredUnit.BTBLookups 135940863 # Number of BTB lookups system.cpu.BPredUnit.BTBLookups 134509889 # Number of BTB lookups
system.cpu.BPredUnit.BTBHits 135060067 # Number of BTB hits system.cpu.BPredUnit.BTBHits 133615988 # Number of BTB hits
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target. system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target.
system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions. system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions.
system.cpu.fetch.icacheStallCycles 143543484 # Number of cycles fetch is stalled on an Icache miss system.cpu.fetch.icacheStallCycles 143149229 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts 1144373207 # Number of instructions fetch has processed system.cpu.fetch.Insts 1143761055 # Number of instructions fetch has processed
system.cpu.fetch.Branches 142841694 # Number of branches that fetch encountered system.cpu.fetch.Branches 142448983 # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches 135060067 # Number of branches that fetch has predicted taken system.cpu.fetch.predictedBranches 133615988 # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles 330625683 # Number of cycles fetch has run and was not squashing or blocked system.cpu.fetch.Cycles 330199440 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles 57747911 # Number of cycles fetch has spent squashing system.cpu.fetch.SquashCycles 57554993 # Number of cycles fetch has spent squashing
system.cpu.fetch.BlockedCycles 649508878 # Number of cycles fetch has spent blocked system.cpu.fetch.BlockedCycles 649541012 # Number of cycles fetch has spent blocked
system.cpu.fetch.MiscStallCycles 57 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu.fetch.MiscStallCycles 52 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles 359 # Number of stall cycles due to pending traps system.cpu.fetch.PendingTrapStallCycles 331 # Number of stall cycles due to pending traps
system.cpu.fetch.CacheLines 137309352 # Number of cache lines fetched system.cpu.fetch.CacheLines 137027209 # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes 979465 # Number of outstanding Icache misses that were squashed system.cpu.fetch.IcacheSquashes 996742 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.rateDist::samples 1173333177 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::samples 1172439660 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean 1.784853 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::mean 1.784546 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev 3.106580 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::stdev 3.109877 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0 845712931 72.08% 72.08% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::0 845244296 72.09% 72.09% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1 16031093 1.37% 73.44% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::1 17110181 1.46% 73.55% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2 18099843 1.54% 74.99% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::2 18043141 1.54% 75.09% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3 17610691 1.50% 76.49% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::3 16408368 1.40% 76.49% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4 23355712 1.99% 78.48% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::4 23340182 1.99% 78.48% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5 16618957 1.42% 79.89% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::5 16629602 1.42% 79.90% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6 23183901 1.98% 81.87% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::6 21855680 1.86% 81.76% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7 28217498 2.40% 84.28% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::7 28257046 2.41% 84.17% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8 184502551 15.72% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::8 185551164 15.83% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total 1173333177 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::total 1172439660 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate 0.121722 # Number of branch fetches per cycle system.cpu.fetch.branchRate 0.121483 # Number of branch fetches per cycle
system.cpu.fetch.rate 0.975170 # Number of inst fetches per cycle system.cpu.fetch.rate 0.975416 # Number of inst fetches per cycle
system.cpu.decode.IdleCycles 241132491 # Number of cycles decode is idle system.cpu.decode.IdleCycles 240695556 # Number of cycles decode is idle
system.cpu.decode.BlockedCycles 558355752 # Number of cycles decode is blocked system.cpu.decode.BlockedCycles 558473143 # Number of cycles decode is blocked
system.cpu.decode.RunCycles 229474776 # Number of cycles decode is running system.cpu.decode.RunCycles 228947071 # Number of cycles decode is running
system.cpu.decode.UnblockCycles 94715442 # Number of cycles decode is unblocking system.cpu.decode.UnblockCycles 94774294 # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles 49654716 # Number of cycles decode is squashing system.cpu.decode.SquashCycles 49549596 # Number of cycles decode is squashing
system.cpu.decode.DecodedInsts 2072768748 # Number of instructions handled by decode system.cpu.decode.DecodedInsts 2070409567 # Number of instructions handled by decode
system.cpu.rename.SquashCycles 49654716 # Number of cycles rename is squashing system.cpu.rename.SquashCycles 49549596 # Number of cycles rename is squashing
system.cpu.rename.IdleCycles 290885704 # Number of cycles rename is idle system.cpu.rename.IdleCycles 290323713 # Number of cycles rename is idle
system.cpu.rename.BlockCycles 132416469 # Number of cycles rename is blocking system.cpu.rename.BlockCycles 132525789 # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles 3327 # count of cycles rename stalled for serializing inst system.cpu.rename.serializeStallCycles 3175 # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles 257077103 # Number of cycles rename is running system.cpu.rename.RunCycles 256725592 # Number of cycles rename is running
system.cpu.rename.UnblockCycles 443295858 # Number of cycles rename is unblocking system.cpu.rename.UnblockCycles 443311795 # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts 2043085659 # Number of instructions processed by rename system.cpu.rename.RenamedInsts 2043122328 # Number of instructions processed by rename
system.cpu.rename.ROBFullEvents 2266 # Number of times rename has blocked due to ROB full system.cpu.rename.ROBFullEvents 2634 # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents 278274210 # Number of times rename has blocked due to IQ full system.cpu.rename.IQFullEvents 278313629 # Number of times rename has blocked due to IQ full
system.cpu.rename.LSQFullEvents 129493006 # Number of times rename has blocked due to LSQ full system.cpu.rename.LSQFullEvents 129499394 # Number of times rename has blocked due to LSQ full
system.cpu.rename.RenamedOperands 2031275937 # Number of destination operands rename has renamed system.cpu.rename.RenamedOperands 2031527324 # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups 4957669219 # Number of register rename lookups that rename has made system.cpu.rename.RenameLookups 4954653616 # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups 4957665711 # Number of integer rename lookups system.cpu.rename.int_rename_lookups 4954649396 # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups 3508 # Number of floating rename lookups system.cpu.rename.fp_rename_lookups 4220 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 1617994650 # Number of HB maps that are committed system.cpu.rename.CommittedMaps 1617994650 # Number of HB maps that are committed
system.cpu.rename.UndoneMaps 413281287 # Number of HB maps that are undone due to squashing system.cpu.rename.UndoneMaps 413532674 # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts 97 # count of serializing insts renamed system.cpu.rename.serializingInsts 91 # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts 97 # count of temporary serializing insts renamed system.cpu.rename.tempSerializingInsts 91 # count of temporary serializing insts renamed
system.cpu.rename.skidInsts 792932011 # count of insts added to the skid buffer system.cpu.rename.skidInsts 793190427 # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads 519352258 # Number of loads inserted to the mem dependence unit. system.cpu.memDep0.insertedLoads 519090632 # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores 227004848 # Number of stores inserted to the mem dependence unit. system.cpu.memDep0.insertedStores 226808407 # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads 355033834 # Number of conflicting loads. system.cpu.memDep0.conflictingLoads 354951645 # Number of conflicting loads.
system.cpu.memDep0.conflictingStores 148905529 # Number of conflicting stores. system.cpu.memDep0.conflictingStores 148937435 # Number of conflicting stores.
system.cpu.iq.iqInstsAdded 1987362019 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqInstsAdded 1986583518 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded 91 # Number of non-speculative instructions added to the IQ system.cpu.iq.iqNonSpecInstsAdded 216 # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued 1782207350 # Number of instructions issued system.cpu.iq.iqInstsIssued 1781630005 # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued 181989 # Number of squashed instructions issued system.cpu.iq.iqSquashedInstsIssued 180825 # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined 365718291 # Number of squashed instructions iterated over during squash; mainly for profiling system.cpu.iq.iqSquashedInstsExamined 364939190 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined 672335048 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedOperandsExamined 670712331 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved 41 # Number of squashed non-spec instructions that were removed system.cpu.iq.iqSquashedNonSpecRemoved 166 # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples 1173333177 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::samples 1172439660 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean 1.518927 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::mean 1.519592 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev 1.333963 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::stdev 1.333662 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0 272616502 23.23% 23.23% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::0 271921708 23.19% 23.19% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1 416904584 35.53% 58.77% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::1 416937500 35.56% 58.75% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2 234897308 20.02% 78.79% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::2 234725234 20.02% 78.77% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3 156871571 13.37% 92.16% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::3 156776493 13.37% 92.15% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4 54320414 4.63% 96.78% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::4 54385701 4.64% 96.79% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5 21136145 1.80% 98.59% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::5 21203892 1.81% 98.59% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6 14479536 1.23% 99.82% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::6 14378982 1.23% 99.82% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7 1803096 0.15% 99.97% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 1804798 0.15% 99.97% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8 304021 0.03% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 305352 0.03% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total 1173333177 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::total 1172439660 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu 181055 7.04% 7.04% # attempts to use FU when none available system.cpu.iq.fu_full::IntAlu 179772 6.92% 6.92% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult 0 0.00% 7.04% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 0 0.00% 6.92% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv 0 0.00% 7.04% # attempts to use FU when none available system.cpu.iq.fu_full::IntDiv 0 0.00% 6.92% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd 0 0.00% 7.04% # attempts to use FU when none available system.cpu.iq.fu_full::FloatAdd 0 0.00% 6.92% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp 0 0.00% 7.04% # attempts to use FU when none available system.cpu.iq.fu_full::FloatCmp 0 0.00% 6.92% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt 0 0.00% 7.04% # attempts to use FU when none available system.cpu.iq.fu_full::FloatCvt 0 0.00% 6.92% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult 0 0.00% 7.04% # attempts to use FU when none available system.cpu.iq.fu_full::FloatMult 0 0.00% 6.92% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv 0 0.00% 7.04% # attempts to use FU when none available system.cpu.iq.fu_full::FloatDiv 0 0.00% 6.92% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 7.04% # attempts to use FU when none available system.cpu.iq.fu_full::FloatSqrt 0 0.00% 6.92% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd 0 0.00% 7.04% # attempts to use FU when none available system.cpu.iq.fu_full::SimdAdd 0 0.00% 6.92% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 7.04% # attempts to use FU when none available system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 6.92% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu 0 0.00% 7.04% # attempts to use FU when none available system.cpu.iq.fu_full::SimdAlu 0 0.00% 6.92% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp 0 0.00% 7.04% # attempts to use FU when none available system.cpu.iq.fu_full::SimdCmp 0 0.00% 6.92% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt 0 0.00% 7.04% # attempts to use FU when none available system.cpu.iq.fu_full::SimdCvt 0 0.00% 6.92% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc 0 0.00% 7.04% # attempts to use FU when none available system.cpu.iq.fu_full::SimdMisc 0 0.00% 6.92% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult 0 0.00% 7.04% # attempts to use FU when none available system.cpu.iq.fu_full::SimdMult 0 0.00% 6.92% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 7.04% # attempts to use FU when none available system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 6.92% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift 0 0.00% 7.04% # attempts to use FU when none available system.cpu.iq.fu_full::SimdShift 0 0.00% 6.92% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 7.04% # attempts to use FU when none available system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 6.92% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 7.04% # attempts to use FU when none available system.cpu.iq.fu_full::SimdSqrt 0 0.00% 6.92% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 7.04% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 6.92% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 7.04% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 6.92% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 7.04% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 6.92% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 7.04% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 6.92% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 7.04% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 6.92% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 7.04% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 6.92% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 7.04% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 6.92% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 7.04% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.92% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 7.04% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 6.92% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead 2242910 87.15% 94.19% # attempts to use FU when none available system.cpu.iq.fu_full::MemRead 2269895 87.35% 94.27% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite 149595 5.81% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::MemWrite 148998 5.73% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 26996432 1.51% 1.51% # Type of FU issued system.cpu.iq.FU_type_0::No_OpClass 26894248 1.51% 1.51% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu 1102299326 61.85% 63.37% # Type of FU issued system.cpu.iq.FU_type_0::IntAlu 1102052870 61.86% 63.37% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult 0 0.00% 63.37% # Type of FU issued system.cpu.iq.FU_type_0::IntMult 0 0.00% 63.37% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 63.37% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 63.37% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 63.37% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 63.37% # Type of FU issued
@ -167,85 +167,85 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 63.37% # Ty
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 63.37% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 63.37% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 63.37% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 63.37% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 63.37% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 63.37% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead 458202367 25.71% 89.07% # Type of FU issued system.cpu.iq.FU_type_0::MemRead 457985397 25.71% 89.07% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite 194709225 10.93% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::MemWrite 194697490 10.93% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::total 1782207350 # Type of FU issued system.cpu.iq.FU_type_0::total 1781630005 # Type of FU issued
system.cpu.iq.rate 1.518697 # Inst issue rate system.cpu.iq.rate 1.519399 # Inst issue rate
system.cpu.iq.fu_busy_cnt 2573560 # FU busy when requested system.cpu.iq.fu_busy_cnt 2598665 # FU busy when requested
system.cpu.iq.fu_busy_rate 0.001444 # FU busy rate (busy events/executed inst) system.cpu.iq.fu_busy_rate 0.001459 # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads 4740503284 # Number of integer instruction queue reads system.cpu.iq.int_inst_queue_reads 4738479065 # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes 2353289601 # Number of integer instruction queue writes system.cpu.iq.int_inst_queue_writes 2351732069 # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses 1760306484 # Number of integer instruction queue wakeup accesses system.cpu.iq.int_inst_queue_wakeup_accesses 1760053766 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 142 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_reads 95 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes 608 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_writes 542 # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses 36 # Number of floating instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_wakeup_accesses 12 # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses 1757784406 # Number of integer alu accesses system.cpu.iq.int_alu_accesses 1757334382 # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses 72 # Number of floating point alu accesses system.cpu.iq.fp_alu_accesses 40 # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads 205673181 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.forwLoads 205665909 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread0.squashedLoads 100310133 # Number of loads squashed system.cpu.iew.lsq.thread0.squashedLoads 100048507 # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses 59834 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread0.ignoredResponses 60622 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation 216613 # Number of memory ordering violations system.cpu.iew.lsq.thread0.memOrderViolation 216417 # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores 38818791 # Number of stores squashed system.cpu.iew.lsq.thread0.squashedStores 38622350 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads 1385 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.rescheduledLoads 849 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked 35852 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.lsq.thread0.cacheBlocked 34395 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
system.cpu.iew.iewSquashCycles 49654716 # Number of cycles IEW is squashing system.cpu.iew.iewSquashCycles 49549596 # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles 1300952 # Number of cycles IEW is blocking system.cpu.iew.iewBlockCycles 1308890 # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles 134624 # Number of cycles IEW is unblocking system.cpu.iew.iewUnblockCycles 133908 # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts 1987362110 # Number of instructions dispatched to IQ system.cpu.iew.iewDispatchedInsts 1986583734 # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts 591185 # Number of squashed instructions skipped by dispatch system.cpu.iew.iewDispSquashedInsts 659432 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts 519352258 # Number of dispatched load instructions system.cpu.iew.iewDispLoadInsts 519090632 # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts 227004848 # Number of dispatched store instructions system.cpu.iew.iewDispStoreInsts 226808407 # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts 91 # Number of dispatched non-speculative instructions system.cpu.iew.iewDispNonSpecInsts 86 # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents 65366 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewIQFullEvents 64911 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents 32 # Number of times the LSQ has become full, causing a stall system.cpu.iew.iewLSQFullEvents 28 # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents 216613 # Number of memory order violations system.cpu.iew.memOrderViolationEvents 216417 # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect 4590434 # Number of branches that were predicted taken incorrectly system.cpu.iew.predictedTakenIncorrect 4603219 # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect 3486470 # Number of branches that were predicted not taken incorrectly system.cpu.iew.predictedNotTakenIncorrect 3388875 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts 8076904 # Number of branch mispredicts detected at execute system.cpu.iew.branchMispredicts 7992094 # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts 1768811104 # Number of executed instructions system.cpu.iew.iewExecutedInsts 1768232809 # Number of executed instructions
system.cpu.iew.iewExecLoadInsts 452331737 # Number of load instructions executed system.cpu.iew.iewExecLoadInsts 452047218 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 13396246 # Number of squashed instructions skipped in execute system.cpu.iew.iewExecSquashedInsts 13397196 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_swp 0 # number of swp insts executed
system.cpu.iew.exec_nop 0 # number of nop insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed
system.cpu.iew.exec_refs 646217865 # number of memory reference insts executed system.cpu.iew.exec_refs 645919458 # number of memory reference insts executed
system.cpu.iew.exec_branches 112172746 # Number of branches executed system.cpu.iew.exec_branches 112169596 # Number of branches executed
system.cpu.iew.exec_stores 193886128 # Number of stores executed system.cpu.iew.exec_stores 193872240 # Number of stores executed
system.cpu.iew.exec_rate 1.507281 # Inst execution rate system.cpu.iew.exec_rate 1.507974 # Inst execution rate
system.cpu.iew.wb_sent 1766741886 # cumulative count of insts sent to commit system.cpu.iew.wb_sent 1766226830 # cumulative count of insts sent to commit
system.cpu.iew.wb_count 1760306520 # cumulative count of insts written-back system.cpu.iew.wb_count 1760053778 # cumulative count of insts written-back
system.cpu.iew.wb_producers 1336435928 # num instructions producing a value system.cpu.iew.wb_producers 1336567337 # num instructions producing a value
system.cpu.iew.wb_consumers 2002913192 # num instructions consuming a value system.cpu.iew.wb_consumers 2003494286 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu.iew.wb_rate 1.500034 # insts written-back per cycle system.cpu.iew.wb_rate 1.500999 # insts written-back per cycle
system.cpu.iew.wb_fanout 0.667246 # average fanout of values written-back system.cpu.iew.wb_fanout 0.667118 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.commit.commitCommittedInsts 1621493982 # The number of committed instructions system.cpu.commit.commitCommittedInsts 1621493982 # The number of committed instructions
system.cpu.commit.commitSquashedInsts 365887065 # The number of squashed insts skipped by commit system.cpu.commit.commitSquashedInsts 365103312 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 50 # The number of times commit has been forced to stall to communicate backwards system.cpu.commit.commitNonSpecStalls 50 # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts 7891152 # The number of times a branch was mispredicted system.cpu.commit.branchMispredicts 7804888 # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples 1123678461 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::samples 1122890064 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean 1.443023 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::mean 1.444036 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev 1.662640 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::stdev 1.662985 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0 347480674 30.92% 30.92% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::0 346724877 30.88% 30.88% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1 438655867 39.04% 69.96% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::1 438665808 39.07% 69.94% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2 94938828 8.45% 78.41% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::2 94902960 8.45% 78.40% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3 133745830 11.90% 90.31% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::3 133728922 11.91% 90.30% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4 36833685 3.28% 93.59% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::4 36854784 3.28% 93.59% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5 26175862 2.33% 95.92% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::5 26115374 2.33% 95.91% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6 22548594 2.01% 97.93% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::6 22565758 2.01% 97.92% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7 8175613 0.73% 98.65% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::7 8207714 0.73% 98.65% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8 15123508 1.35% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::8 15123867 1.35% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total 1123678461 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::total 1122890064 # Number of insts commited each cycle
system.cpu.commit.count 1621493982 # Number of instructions committed system.cpu.commit.count 1621493982 # Number of instructions committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.refs 607228182 # Number of memory references committed system.cpu.commit.refs 607228182 # Number of memory references committed
@ -255,48 +255,48 @@ system.cpu.commit.branches 107161579 # Nu
system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. system.cpu.commit.fp_insts 0 # Number of committed floating point instructions.
system.cpu.commit.int_insts 1621354492 # Number of committed integer instructions. system.cpu.commit.int_insts 1621354492 # Number of committed integer instructions.
system.cpu.commit.function_calls 0 # Number of function calls committed. system.cpu.commit.function_calls 0 # Number of function calls committed.
system.cpu.commit.bw_lim_events 15123508 # number cycles where commit BW limit reached system.cpu.commit.bw_lim_events 15123867 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
system.cpu.rob.rob_reads 3095936000 # The number of ROB reads system.cpu.rob.rob_reads 3094363491 # The number of ROB reads
system.cpu.rob.rob_writes 4024437562 # The number of ROB writes system.cpu.rob.rob_writes 4022764791 # The number of ROB writes
system.cpu.timesIdled 44153 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.timesIdled 43542 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 177830 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.idleCycles 148789 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts 1621493982 # Number of Instructions Simulated system.cpu.committedInsts 1621493982 # Number of Instructions Simulated
system.cpu.committedInsts_total 1621493982 # Number of Instructions Simulated system.cpu.committedInsts_total 1621493982 # Number of Instructions Simulated
system.cpu.cpi 0.723722 # CPI: Cycles Per Instruction system.cpu.cpi 0.723153 # CPI: Cycles Per Instruction
system.cpu.cpi_total 0.723722 # CPI: Total CPI of All Threads system.cpu.cpi_total 0.723153 # CPI: Total CPI of All Threads
system.cpu.ipc 1.381746 # IPC: Instructions Per Cycle system.cpu.ipc 1.382833 # IPC: Instructions Per Cycle
system.cpu.ipc_total 1.381746 # IPC: Total IPC of All Threads system.cpu.ipc_total 1.382833 # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads 3273654764 # number of integer regfile reads system.cpu.int_regfile_reads 3273039620 # number of integer regfile reads
system.cpu.int_regfile_writes 1756473314 # number of integer regfile writes system.cpu.int_regfile_writes 1756091293 # number of integer regfile writes
system.cpu.fp_regfile_reads 36 # number of floating regfile reads system.cpu.fp_regfile_reads 12 # number of floating regfile reads
system.cpu.misc_regfile_reads 909253494 # number of misc regfile reads system.cpu.misc_regfile_reads 908871446 # number of misc regfile reads
system.cpu.icache.replacements 16 # number of replacements system.cpu.icache.replacements 12 # number of replacements
system.cpu.icache.tagsinuse 813.268656 # Cycle average of tags in use system.cpu.icache.tagsinuse 810.394392 # Cycle average of tags in use
system.cpu.icache.total_refs 137308116 # Total number of references to valid blocks. system.cpu.icache.total_refs 137025977 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 900 # Sample count of references to valid blocks. system.cpu.icache.sampled_refs 893 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 152564.573333 # Average number of references to valid blocks. system.cpu.icache.avg_refs 153444.543113 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.occ_blocks::0 813.268656 # Average occupied blocks per context system.cpu.icache.occ_blocks::0 810.394392 # Average occupied blocks per context
system.cpu.icache.occ_percent::0 0.397104 # Average percentage of cache occupancy system.cpu.icache.occ_percent::0 0.395700 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits 137308116 # number of ReadReq hits system.cpu.icache.ReadReq_hits 137025977 # number of ReadReq hits
system.cpu.icache.demand_hits 137308116 # number of demand (read+write) hits system.cpu.icache.demand_hits 137025977 # number of demand (read+write) hits
system.cpu.icache.overall_hits 137308116 # number of overall hits system.cpu.icache.overall_hits 137025977 # number of overall hits
system.cpu.icache.ReadReq_misses 1236 # number of ReadReq misses system.cpu.icache.ReadReq_misses 1232 # number of ReadReq misses
system.cpu.icache.demand_misses 1236 # number of demand (read+write) misses system.cpu.icache.demand_misses 1232 # number of demand (read+write) misses
system.cpu.icache.overall_misses 1236 # number of overall misses system.cpu.icache.overall_misses 1232 # number of overall misses
system.cpu.icache.ReadReq_miss_latency 43480000 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_latency 43328500 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency 43480000 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_latency 43328500 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency 43480000 # number of overall miss cycles system.cpu.icache.overall_miss_latency 43328500 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses 137309352 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses 137027209 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses 137309352 # number of demand (read+write) accesses system.cpu.icache.demand_accesses 137027209 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses 137309352 # number of overall (read+write) accesses system.cpu.icache.overall_accesses 137027209 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate 0.000009 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate 0.000009 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate 0.000009 # miss rate for demand accesses system.cpu.icache.demand_miss_rate 0.000009 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate 0.000009 # miss rate for overall accesses system.cpu.icache.overall_miss_rate 0.000009 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency 35177.993528 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_miss_latency 35169.237013 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency 35177.993528 # average overall miss latency system.cpu.icache.demand_avg_miss_latency 35169.237013 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency 35177.993528 # average overall miss latency system.cpu.icache.overall_avg_miss_latency 35169.237013 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
@ -306,130 +306,130 @@ system.cpu.icache.avg_blocked_cycles::no_targets no_value
system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.writebacks 0 # number of writebacks system.cpu.icache.writebacks 0 # number of writebacks
system.cpu.icache.ReadReq_mshr_hits 336 # number of ReadReq MSHR hits system.cpu.icache.ReadReq_mshr_hits 339 # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits 336 # number of demand (read+write) MSHR hits system.cpu.icache.demand_mshr_hits 339 # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits 336 # number of overall MSHR hits system.cpu.icache.overall_mshr_hits 339 # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses 900 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses 893 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses 900 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses 893 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses 900 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses 893 # number of overall MSHR misses
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.icache.ReadReq_mshr_miss_latency 31792500 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_latency 31560500 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency 31792500 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_latency 31560500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency 31792500 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency 31560500 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.icache.ReadReq_mshr_miss_rate 0.000007 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate 0.000007 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate 0.000007 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate 0.000007 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate 0.000007 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate 0.000007 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency 35325 # average ReadReq mshr miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency 35342.105263 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency 35325 # average overall mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency 35342.105263 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 35325 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency 35342.105263 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 459082 # number of replacements system.cpu.dcache.replacements 459077 # number of replacements
system.cpu.dcache.tagsinuse 4094.908409 # Cycle average of tags in use system.cpu.dcache.tagsinuse 4094.907333 # Cycle average of tags in use
system.cpu.dcache.total_refs 433296852 # Total number of references to valid blocks. system.cpu.dcache.total_refs 433034493 # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs 463178 # Sample count of references to valid blocks. system.cpu.dcache.sampled_refs 463173 # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs 935.486685 # Average number of references to valid blocks. system.cpu.dcache.avg_refs 934.930346 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 317735000 # Cycle when the warmup percentage was hit. system.cpu.dcache.warmup_cycle 317767000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::0 4094.908409 # Average occupied blocks per context system.cpu.dcache.occ_blocks::0 4094.907333 # Average occupied blocks per context
system.cpu.dcache.occ_percent::0 0.999733 # Average percentage of cache occupancy system.cpu.dcache.occ_percent::0 0.999733 # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits 246417961 # number of ReadReq hits system.cpu.dcache.ReadReq_hits 246142702 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits 186878891 # number of WriteReq hits system.cpu.dcache.WriteReq_hits 186891791 # number of WriteReq hits
system.cpu.dcache.demand_hits 433296852 # number of demand (read+write) hits system.cpu.dcache.demand_hits 433034493 # number of demand (read+write) hits
system.cpu.dcache.overall_hits 433296852 # number of overall hits system.cpu.dcache.overall_hits 433034493 # number of overall hits
system.cpu.dcache.ReadReq_misses 217222 # number of ReadReq misses system.cpu.dcache.ReadReq_misses 217277 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses 1307166 # number of WriteReq misses system.cpu.dcache.WriteReq_misses 1294266 # number of WriteReq misses
system.cpu.dcache.demand_misses 1524388 # number of demand (read+write) misses system.cpu.dcache.demand_misses 1511543 # number of demand (read+write) misses
system.cpu.dcache.overall_misses 1524388 # number of overall misses system.cpu.dcache.overall_misses 1511543 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency 2206460500 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_latency 2206130500 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency 25191688497 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_latency 25062764496 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency 27398148997 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_latency 27268894996 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency 27398148997 # number of overall miss cycles system.cpu.dcache.overall_miss_latency 27268894996 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses 246635183 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses 246359979 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses 188186057 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses 188186057 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.demand_accesses 434821240 # number of demand (read+write) accesses system.cpu.dcache.demand_accesses 434546036 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses 434821240 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses 434546036 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate 0.000881 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate 0.000882 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate 0.006946 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate 0.006878 # miss rate for WriteReq accesses
system.cpu.dcache.demand_miss_rate 0.003506 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate 0.003478 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate 0.003506 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate 0.003478 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency 10157.629062 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency 10153.539031 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency 19271.988789 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency 19364.461785 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency 17973.212199 # average overall miss latency system.cpu.dcache.demand_avg_miss_latency 18040.436161 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency 17973.212199 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency 18040.436161 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 1884500 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_mshrs 1883000 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 490158000 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 482947000 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 482 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 482 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 33499 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 32670 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs 3909.751037 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs 3906.639004 # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets 14632.018866 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets 14782.583410 # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.writebacks 410010 # number of writebacks system.cpu.dcache.writebacks 410037 # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits 3618 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_hits 3648 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits 1057590 # number of WriteReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits 1044720 # number of WriteReq MSHR hits
system.cpu.dcache.demand_mshr_hits 1061208 # number of demand (read+write) MSHR hits system.cpu.dcache.demand_mshr_hits 1048368 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits 1061208 # number of overall MSHR hits system.cpu.dcache.overall_mshr_hits 1048368 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses 213604 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses 213629 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses 249576 # number of WriteReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses 249546 # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses 463180 # number of demand (read+write) MSHR misses system.cpu.dcache.demand_mshr_misses 463175 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses 463180 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses 463175 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.dcache.ReadReq_mshr_miss_latency 1533784000 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_latency 1533480500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency 2518332500 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency 2506697000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency 4052116500 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_latency 4040177500 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency 4052116500 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency 4040177500 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_miss_rate 0.000866 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate 0.000867 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate 0.001326 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate 0.001326 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate 0.001065 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate 0.001066 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate 0.001065 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate 0.001066 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 7180.502238 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency 7178.241250 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 10090.443392 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency 10045.029774 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 8748.470357 # average overall mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency 8722.788363 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 8748.470357 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency 8722.788363 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 73626 # number of replacements system.cpu.l2cache.replacements 73618 # number of replacements
system.cpu.l2cache.tagsinuse 17961.057219 # Cycle average of tags in use system.cpu.l2cache.tagsinuse 17964.500601 # Cycle average of tags in use
system.cpu.l2cache.total_refs 452680 # Total number of references to valid blocks. system.cpu.l2cache.total_refs 452679 # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs 89247 # Sample count of references to valid blocks. system.cpu.l2cache.sampled_refs 89237 # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs 5.072215 # Average number of references to valid blocks. system.cpu.l2cache.avg_refs 5.072773 # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.occ_blocks::0 1976.377276 # Average occupied blocks per context system.cpu.l2cache.occ_blocks::0 1976.098849 # Average occupied blocks per context
system.cpu.l2cache.occ_blocks::1 15984.679942 # Average occupied blocks per context system.cpu.l2cache.occ_blocks::1 15988.401752 # Average occupied blocks per context
system.cpu.l2cache.occ_percent::0 0.060314 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::0 0.060306 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::1 0.487814 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::1 0.487927 # Average percentage of cache occupancy
system.cpu.l2cache.ReadReq_hits 181326 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits 181359 # number of ReadReq hits
system.cpu.l2cache.Writeback_hits 410010 # number of Writeback hits system.cpu.l2cache.Writeback_hits 410037 # number of Writeback hits
system.cpu.l2cache.ReadExReq_hits 190857 # number of ReadExReq hits system.cpu.l2cache.ReadExReq_hits 190824 # number of ReadExReq hits
system.cpu.l2cache.demand_hits 372183 # number of demand (read+write) hits system.cpu.l2cache.demand_hits 372183 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits 372183 # number of overall hits system.cpu.l2cache.overall_hits 372183 # number of overall hits
system.cpu.l2cache.ReadReq_misses 33178 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses 33163 # number of ReadReq misses
system.cpu.l2cache.ReadExReq_misses 58719 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_misses 58722 # number of ReadExReq misses
system.cpu.l2cache.demand_misses 91897 # number of demand (read+write) misses system.cpu.l2cache.demand_misses 91885 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses 91897 # number of overall misses system.cpu.l2cache.overall_misses 91885 # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency 1131489500 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_latency 1130840000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency 2019003500 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency 2017374000 # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency 3150493000 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_latency 3148214000 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency 3150493000 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency 3148214000 # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses 214504 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses 214522 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses 410010 # number of Writeback accesses(hits+misses) system.cpu.l2cache.Writeback_accesses 410037 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses 249576 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses 249546 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses 464080 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses 464068 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses 464080 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses 464068 # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate 0.154673 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate 0.154590 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_miss_rate 0.235275 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_miss_rate 0.235315 # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate 0.198020 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate 0.197999 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate 0.198020 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate 0.197999 # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency 34103.607812 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency 34099.448180 # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency 34384.160153 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency 34354.654133 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency 34282.871040 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency 34262.545573 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency 34282.871040 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency 34262.545573 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 202000 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_mshrs 202000 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 122 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 122 # number of cycles access was blocked
@ -438,27 +438,27 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs 1655.737705
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.writebacks 58507 # number of writebacks system.cpu.l2cache.writebacks 58503 # number of writebacks
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
system.cpu.l2cache.ReadReq_mshr_misses 33178 # number of ReadReq MSHR misses system.cpu.l2cache.ReadReq_mshr_misses 33163 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses 58719 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses 58722 # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses 91897 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses 91885 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses 91897 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses 91885 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.l2cache.ReadReq_mshr_miss_latency 1028691000 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_latency 1028236500 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency 1828336500 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency 1828595500 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency 2857027500 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency 2856832000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency 2857027500 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency 2856832000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.154673 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate 0.154590 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.235275 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.235315 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate 0.198020 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate 0.197999 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate 0.198020 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate 0.197999 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31005.214299 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31005.533275 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31137.051040 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31139.870917 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency 31089.453410 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency 31091.385972 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 31089.453410 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 31091.385972 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions

11
tests/long/10.linux-boot/ref/x86/linux/pc-o3-timing/simout
View file

@ -3,13 +3,14 @@ Redirecting stderr to build/X86_FS/tests/opt/long/10.linux-boot/x86/linux/pc-o3-
gem5 Simulator System. http://gem5.org gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details. gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Aug 20 2011 15:40:58 gem5 compiled Nov 17 2011 18:36:33
gem5 started Aug 20 2011 15:42:13 gem5 started Nov 17 2011 18:37:39
gem5 executing on zizzer gem5 executing on ribera.cs.wisc.edu
command line: build/X86_FS/gem5.opt -d build/X86_FS/tests/opt/long/10.linux-boot/x86/linux/pc-o3-timing -re tests/run.py build/X86_FS/tests/opt/long/10.linux-boot/x86/linux/pc-o3-timing command line: build/X86_FS/gem5.opt -d build/X86_FS/tests/opt/long/10.linux-boot/x86/linux/pc-o3-timing -re tests/run.py build/X86_FS/tests/opt/long/10.linux-boot/x86/linux/pc-o3-timing
tests
warning: add_child('terminal'): child 'terminal' already has parent warning: add_child('terminal'): child 'terminal' already has parent
Global frequency set at 1000000000000 ticks per second Global frequency set at 1000000000000 ticks per second
info: kernel located at: /dist/m5/system/binaries/x86_64-vmlinux-2.6.22.9 info: kernel located at: /scratch/nilay/GEM5/system/binaries/x86_64-vmlinux-2.6.22.9
0: rtc: Real-time clock set to Sun Jan 1 00:00:00 2012 0: rtc: Real-time clock set to Sun Jan 1 00:00:00 2012
info: Entering event queue @ 0. Starting simulation... info: Entering event queue @ 0. Starting simulation...
Exiting @ tick 5147601271500 because m5_exit instruction encountered Exiting @ tick 5145286546500 because m5_exit instruction encountered

1242
tests/long/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt
View file

File diff suppressed because it is too large Load diff

2
tests/long/10.linux-boot/ref/x86/linux/pc-o3-timing/system.pc.com_1.terminal
View file

@ -39,7 +39,7 @@ ACPI: Core revision 20070126
ACPI Exception (tbxface-0618): AE_NO_ACPI_TABLES, While loading namespace from ACPI tables [20070126] ACPI Exception (tbxface-0618): AE_NO_ACPI_TABLES, While loading namespace from ACPI tables [20070126]
ACPI: Unable to load the System Description Tables ACPI: Unable to load the System Description Tables
Using local APIC timer interrupts. Using local APIC timer interrupts.
result 7812515 result 7812511
Detected 7.812 MHz APIC timer. Detected 7.812 MHz APIC timer.
NET: Registered protocol family 16 NET: Registered protocol family 16
PCI: Using configuration type 1 PCI: Using configuration type 1

9
tests/long/10.mcf/ref/x86/linux/o3-timing/simout
View file

@ -3,10 +3,11 @@ Redirecting stderr to build/X86_SE/tests/opt/long/10.mcf/x86/linux/o3-timing/sim
gem5 Simulator System. http://gem5.org gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details. gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Aug 20 2011 13:24:14 gem5 compiled Nov 16 2011 11:08:03
gem5 started Aug 20 2011 13:24:28 gem5 started Nov 17 2011 13:09:16
gem5 executing on zizzer gem5 executing on ribera.cs.wisc.edu
command line: build/X86_SE/gem5.opt -d build/X86_SE/tests/opt/long/10.mcf/x86/linux/o3-timing -re tests/run.py build/X86_SE/tests/opt/long/10.mcf/x86/linux/o3-timing command line: build/X86_SE/gem5.opt -d build/X86_SE/tests/opt/long/10.mcf/x86/linux/o3-timing -re tests/run.py build/X86_SE/tests/opt/long/10.mcf/x86/linux/o3-timing
tests
Global frequency set at 1000000000000 ticks per second Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation... info: Entering event queue @ 0. Starting simulation...
@ -25,4 +26,4 @@ simplex iterations : 2663
flow value : 3080014995 flow value : 3080014995
checksum : 68389 checksum : 68389
optimal optimal
Exiting @ tick 70374234500 because target called exit() Exiting @ tick 70312944500 because target called exit()

718
tests/long/10.mcf/ref/x86/linux/o3-timing/stats.txt
View file

@ -1,251 +1,251 @@
---------- Begin Simulation Statistics ---------- ---------- Begin Simulation Statistics ----------
sim_seconds 0.070374 # Number of seconds simulated sim_seconds 0.070313 # Number of seconds simulated
sim_ticks 70374234500 # Number of ticks simulated sim_ticks 70312944500 # Number of ticks simulated
sim_freq 1000000000000 # Frequency of simulated ticks sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 169063 # Simulator instruction rate (inst/s) host_inst_rate 125815 # Simulator instruction rate (inst/s)
host_tick_rate 42767879 # Simulator tick rate (ticks/s) host_tick_rate 31799589 # Simulator tick rate (ticks/s)
host_mem_usage 346452 # Number of bytes of host memory used host_mem_usage 378944 # Number of bytes of host memory used
host_seconds 1645.49 # Real time elapsed on the host host_seconds 2211.13 # Real time elapsed on the host
sim_insts 278192519 # Number of instructions simulated sim_insts 278192519 # Number of instructions simulated
system.cpu.workload.num_syscalls 444 # Number of system calls system.cpu.workload.num_syscalls 444 # Number of system calls
system.cpu.numCycles 140748470 # number of cpu cycles simulated system.cpu.numCycles 140625890 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.BPredUnit.lookups 37906853 # Number of BP lookups system.cpu.BPredUnit.lookups 37833804 # Number of BP lookups
system.cpu.BPredUnit.condPredicted 37906853 # Number of conditional branches predicted system.cpu.BPredUnit.condPredicted 37833804 # Number of conditional branches predicted
system.cpu.BPredUnit.condIncorrect 1330176 # Number of conditional branches incorrect system.cpu.BPredUnit.condIncorrect 1322933 # Number of conditional branches incorrect
system.cpu.BPredUnit.BTBLookups 33468761 # Number of BTB lookups system.cpu.BPredUnit.BTBLookups 33591925 # Number of BTB lookups
system.cpu.BPredUnit.BTBHits 32955372 # Number of BTB hits system.cpu.BPredUnit.BTBHits 33081589 # Number of BTB hits
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target. system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target.
system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions. system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions.
system.cpu.fetch.icacheStallCycles 29094074 # Number of cycles fetch is stalled on an Icache miss system.cpu.fetch.icacheStallCycles 29087381 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts 203757407 # Number of instructions fetch has processed system.cpu.fetch.Insts 203627812 # Number of instructions fetch has processed
system.cpu.fetch.Branches 37906853 # Number of branches that fetch encountered system.cpu.fetch.Branches 37833804 # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches 32955372 # Number of branches that fetch has predicted taken system.cpu.fetch.predictedBranches 33081589 # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles 63225813 # Number of cycles fetch has run and was not squashing or blocked system.cpu.fetch.Cycles 63297987 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles 10352620 # Number of cycles fetch has spent squashing system.cpu.fetch.SquashCycles 10276298 # Number of cycles fetch has spent squashing
system.cpu.fetch.BlockedCycles 38317432 # Number of cycles fetch has spent blocked system.cpu.fetch.BlockedCycles 38195582 # Number of cycles fetch has spent blocked
system.cpu.fetch.MiscStallCycles 22 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu.fetch.MiscStallCycles 21 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles 97 # Number of stall cycles due to pending traps system.cpu.fetch.PendingTrapStallCycles 95 # Number of stall cycles due to pending traps
system.cpu.fetch.CacheLines 28270666 # Number of cache lines fetched system.cpu.fetch.CacheLines 28266291 # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes 203655 # Number of outstanding Icache misses that were squashed system.cpu.fetch.IcacheSquashes 204981 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.rateDist::samples 139622279 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::samples 139497150 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean 2.575042 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::mean 2.574262 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev 3.293353 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::stdev 3.291399 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0 78878326 56.49% 56.49% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::0 78673130 56.40% 56.40% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1 3468234 2.48% 58.98% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::1 3606277 2.59% 58.98% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2 2811542 2.01% 60.99% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::2 2810090 2.01% 61.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3 4524513 3.24% 64.23% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::3 4532102 3.25% 64.25% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4 6755323 4.84% 69.07% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::4 6824412 4.89% 69.14% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5 5317016 3.81% 72.88% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::5 5279008 3.78% 72.92% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6 7687744 5.51% 78.38% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::6 7637539 5.48% 78.40% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7 4301095 3.08% 81.47% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::7 4315201 3.09% 81.49% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8 25878486 18.53% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::8 25819391 18.51% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total 139622279 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::total 139497150 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate 0.269323 # Number of branch fetches per cycle system.cpu.fetch.branchRate 0.269039 # Number of branch fetches per cycle
system.cpu.fetch.rate 1.447670 # Number of inst fetches per cycle system.cpu.fetch.rate 1.448011 # Number of inst fetches per cycle
system.cpu.decode.IdleCycles 41959628 # Number of cycles decode is idle system.cpu.decode.IdleCycles 41917744 # Number of cycles decode is idle
system.cpu.decode.BlockedCycles 28656621 # Number of cycles decode is blocked system.cpu.decode.BlockedCycles 28560060 # Number of cycles decode is blocked
system.cpu.decode.RunCycles 52572729 # Number of cycles decode is running system.cpu.decode.RunCycles 52643719 # Number of cycles decode is running
system.cpu.decode.UnblockCycles 7448460 # Number of cycles decode is unblocking system.cpu.decode.UnblockCycles 7459543 # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles 8984841 # Number of cycles decode is squashing system.cpu.decode.SquashCycles 8916084 # Number of cycles decode is squashing
system.cpu.decode.DecodedInsts 355072137 # Number of instructions handled by decode system.cpu.decode.DecodedInsts 354657218 # Number of instructions handled by decode
system.cpu.rename.SquashCycles 8984841 # Number of cycles rename is squashing system.cpu.rename.SquashCycles 8916084 # Number of cycles rename is squashing
system.cpu.rename.IdleCycles 48879402 # Number of cycles rename is idle system.cpu.rename.IdleCycles 48823983 # Number of cycles rename is idle
system.cpu.rename.BlockCycles 4457870 # Number of cycles rename is blocking system.cpu.rename.BlockCycles 4469241 # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles 6893 # count of cycles rename stalled for serializing inst system.cpu.rename.serializeStallCycles 6888 # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles 52910993 # Number of cycles rename is running system.cpu.rename.RunCycles 53004642 # Number of cycles rename is running
system.cpu.rename.UnblockCycles 24382280 # Number of cycles rename is unblocking system.cpu.rename.UnblockCycles 24276312 # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts 350563031 # Number of instructions processed by rename system.cpu.rename.RenamedInsts 350176569 # Number of instructions processed by rename
system.cpu.rename.ROBFullEvents 15 # Number of times rename has blocked due to ROB full system.cpu.rename.ROBFullEvents 14 # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents 104227 # Number of times rename has blocked due to IQ full system.cpu.rename.IQFullEvents 101342 # Number of times rename has blocked due to IQ full
system.cpu.rename.LSQFullEvents 20384891 # Number of times rename has blocked due to LSQ full system.cpu.rename.LSQFullEvents 20289844 # Number of times rename has blocked due to LSQ full
system.cpu.rename.RenamedOperands 314779048 # Number of destination operands rename has renamed system.cpu.rename.RenamedOperands 314446851 # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups 862154595 # Number of register rename lookups that rename has made system.cpu.rename.RenameLookups 861231533 # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups 862151489 # Number of integer rename lookups system.cpu.rename.int_rename_lookups 861227904 # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups 3106 # Number of floating rename lookups system.cpu.rename.fp_rename_lookups 3629 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 248344192 # Number of HB maps that are committed system.cpu.rename.CommittedMaps 248344192 # Number of HB maps that are committed
system.cpu.rename.UndoneMaps 66434856 # Number of HB maps that are undone due to squashing system.cpu.rename.UndoneMaps 66102659 # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts 479 # count of serializing insts renamed system.cpu.rename.serializingInsts 479 # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts 472 # count of temporary serializing insts renamed system.cpu.rename.tempSerializingInsts 472 # count of temporary serializing insts renamed
system.cpu.rename.skidInsts 56483579 # count of insts added to the skid buffer system.cpu.rename.skidInsts 56104077 # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads 112824537 # Number of loads inserted to the mem dependence unit. system.cpu.memDep0.insertedLoads 112666461 # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores 37669092 # Number of stores inserted to the mem dependence unit. system.cpu.memDep0.insertedStores 37647255 # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads 48262856 # Number of conflicting loads. system.cpu.memDep0.conflictingLoads 48253520 # Number of conflicting loads.
system.cpu.memDep0.conflictingStores 8162457 # Number of conflicting stores. system.cpu.memDep0.conflictingStores 8188094 # Number of conflicting stores.
system.cpu.iq.iqInstsAdded 343955075 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqInstsAdded 343455788 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded 466 # Number of non-speculative instructions added to the IQ system.cpu.iq.iqNonSpecInstsAdded 2295 # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued 316373550 # Number of instructions issued system.cpu.iq.iqInstsIssued 316242386 # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued 98329 # Number of squashed instructions issued system.cpu.iq.iqSquashedInstsIssued 89834 # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined 65563048 # Number of squashed instructions iterated over during squash; mainly for profiling system.cpu.iq.iqSquashedInstsExamined 65098177 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined 93813941 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedOperandsExamined 92870721 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved 20 # Number of squashed non-spec instructions that were removed system.cpu.iq.iqSquashedNonSpecRemoved 1849 # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples 139622279 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::samples 139497150 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean 2.265925 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::mean 2.267017 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev 1.753143 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::stdev 1.750973 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0 31939796 22.88% 22.88% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::0 31795649 22.79% 22.79% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1 18447556 13.21% 36.09% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::1 18418675 13.20% 36.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2 25584563 18.32% 54.41% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::2 25717845 18.44% 54.43% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3 29944678 21.45% 75.86% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::3 29872112 21.41% 75.85% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4 18447649 13.21% 89.07% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::4 18507796 13.27% 89.11% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5 10291416 7.37% 96.44% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::5 10200782 7.31% 96.43% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6 3138355 2.25% 98.69% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::6 3199934 2.29% 98.72% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7 1781100 1.28% 99.97% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 1737869 1.25% 99.97% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8 47166 0.03% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 46488 0.03% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total 139622279 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::total 139497150 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu 26426 1.39% 1.39% # attempts to use FU when none available system.cpu.iq.fu_full::IntAlu 25785 1.36% 1.36% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult 0 0.00% 1.39% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 0 0.00% 1.36% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv 0 0.00% 1.39% # attempts to use FU when none available system.cpu.iq.fu_full::IntDiv 0 0.00% 1.36% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd 0 0.00% 1.39% # attempts to use FU when none available system.cpu.iq.fu_full::FloatAdd 0 0.00% 1.36% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp 0 0.00% 1.39% # attempts to use FU when none available system.cpu.iq.fu_full::FloatCmp 0 0.00% 1.36% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt 0 0.00% 1.39% # attempts to use FU when none available system.cpu.iq.fu_full::FloatCvt 0 0.00% 1.36% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult 0 0.00% 1.39% # attempts to use FU when none available system.cpu.iq.fu_full::FloatMult 0 0.00% 1.36% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv 0 0.00% 1.39% # attempts to use FU when none available system.cpu.iq.fu_full::FloatDiv 0 0.00% 1.36% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 1.39% # attempts to use FU when none available system.cpu.iq.fu_full::FloatSqrt 0 0.00% 1.36% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd 0 0.00% 1.39% # attempts to use FU when none available system.cpu.iq.fu_full::SimdAdd 0 0.00% 1.36% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 1.39% # attempts to use FU when none available system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 1.36% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu 0 0.00% 1.39% # attempts to use FU when none available system.cpu.iq.fu_full::SimdAlu 0 0.00% 1.36% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp 0 0.00% 1.39% # attempts to use FU when none available system.cpu.iq.fu_full::SimdCmp 0 0.00% 1.36% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt 0 0.00% 1.39% # attempts to use FU when none available system.cpu.iq.fu_full::SimdCvt 0 0.00% 1.36% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc 0 0.00% 1.39% # attempts to use FU when none available system.cpu.iq.fu_full::SimdMisc 0 0.00% 1.36% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult 0 0.00% 1.39% # attempts to use FU when none available system.cpu.iq.fu_full::SimdMult 0 0.00% 1.36% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 1.39% # attempts to use FU when none available system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 1.36% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift 0 0.00% 1.39% # attempts to use FU when none available system.cpu.iq.fu_full::SimdShift 0 0.00% 1.36% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 1.39% # attempts to use FU when none available system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 1.36% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 1.39% # attempts to use FU when none available system.cpu.iq.fu_full::SimdSqrt 0 0.00% 1.36% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 1.39% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 1.36% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 1.39% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 1.36% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 1.39% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 1.36% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 1.39% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 1.36% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 1.39% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 1.36% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 1.39% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 1.36% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 1.39% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 1.36% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.39% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.36% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 1.39% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 1.36% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead 1802884 94.84% 96.23% # attempts to use FU when none available system.cpu.iq.fu_full::MemRead 1795857 94.47% 95.83% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite 71697 3.77% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::MemWrite 79349 4.17% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 16711 0.01% 0.01% # Type of FU issued system.cpu.iq.FU_type_0::No_OpClass 16711 0.01% 0.01% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu 180370396 57.01% 57.02% # Type of FU issued system.cpu.iq.FU_type_0::IntAlu 180262574 57.00% 57.01% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult 0 0.00% 57.02% # Type of FU issued system.cpu.iq.FU_type_0::IntMult 0 0.00% 57.01% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 57.02% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 57.01% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd 163 0.00% 57.02% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 195 0.00% 57.01% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 57.02% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 57.01% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 57.02% # Type of FU issued system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 57.01% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 57.02% # Type of FU issued system.cpu.iq.FU_type_0::FloatMult 0 0.00% 57.01% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 57.02% # Type of FU issued system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 57.01% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 57.02% # Type of FU issued system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 57.01% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 57.02% # Type of FU issued system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 57.01% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 57.02% # Type of FU issued system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 57.01% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 57.02% # Type of FU issued system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 57.01% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 57.02% # Type of FU issued system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 57.01% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 57.02% # Type of FU issued system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 57.01% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 57.02% # Type of FU issued system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 57.01% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 57.02% # Type of FU issued system.cpu.iq.FU_type_0::SimdMult 0 0.00% 57.01% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 57.02% # Type of FU issued system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 57.01% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 57.02% # Type of FU issued system.cpu.iq.FU_type_0::SimdShift 0 0.00% 57.01% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 57.02% # Type of FU issued system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 57.01% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 57.02% # Type of FU issued system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 57.01% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 57.02% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 57.01% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 57.02% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 57.01% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 57.02% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 57.01% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 57.02% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 57.01% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 57.02% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 57.01% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 57.02% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 57.01% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 57.02% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 57.01% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 57.02% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 57.01% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 57.02% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 57.01% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead 101485830 32.08% 89.10% # Type of FU issued system.cpu.iq.FU_type_0::MemRead 101451147 32.08% 89.09% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite 34500450 10.90% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::MemWrite 34511759 10.91% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::total 316373550 # Type of FU issued system.cpu.iq.FU_type_0::total 316242386 # Type of FU issued
system.cpu.iq.rate 2.247794 # Inst issue rate system.cpu.iq.rate 2.248821 # Inst issue rate
system.cpu.iq.fu_busy_cnt 1901007 # FU busy when requested system.cpu.iq.fu_busy_cnt 1900991 # FU busy when requested
system.cpu.iq.fu_busy_rate 0.006009 # FU busy rate (busy events/executed inst) system.cpu.iq.fu_busy_rate 0.006011 # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads 774367858 # Number of integer instruction queue reads system.cpu.iq.int_inst_queue_reads 773971833 # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes 409550255 # Number of integer instruction queue writes system.cpu.iq.int_inst_queue_writes 408587092 # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses 312670753 # Number of integer instruction queue wakeup accesses system.cpu.iq.int_inst_queue_wakeup_accesses 312537049 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 857 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_reads 914 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes 1937 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_writes 2332 # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses 344 # Number of floating instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_wakeup_accesses 382 # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses 318257421 # Number of integer alu accesses system.cpu.iq.int_alu_accesses 318126211 # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses 425 # Number of floating point alu accesses system.cpu.iq.fp_alu_accesses 455 # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads 45906074 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.forwLoads 45906656 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread0.squashedLoads 22045149 # Number of loads squashed system.cpu.iew.lsq.thread0.squashedLoads 21887073 # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses 125133 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread0.ignoredResponses 122159 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation 34222 # Number of memory ordering violations system.cpu.iew.lsq.thread0.memOrderViolation 33758 # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores 6229341 # Number of stores squashed system.cpu.iew.lsq.thread0.squashedStores 6207504 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads 2799 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.rescheduledLoads 2763 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked 15405 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.lsq.thread0.cacheBlocked 15488 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
system.cpu.iew.iewSquashCycles 8984841 # Number of cycles IEW is squashing system.cpu.iew.iewSquashCycles 8916084 # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles 901233 # Number of cycles IEW is blocking system.cpu.iew.iewBlockCycles 901068 # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles 88686 # Number of cycles IEW is unblocking system.cpu.iew.iewUnblockCycles 88602 # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts 343955541 # Number of instructions dispatched to IQ system.cpu.iew.iewDispatchedInsts 343458083 # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts 25713 # Number of squashed instructions skipped by dispatch system.cpu.iew.iewDispSquashedInsts 26305 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts 112824537 # Number of dispatched load instructions system.cpu.iew.iewDispLoadInsts 112666461 # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts 37669092 # Number of dispatched store instructions system.cpu.iew.iewDispStoreInsts 37647255 # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts 466 # Number of dispatched non-speculative instructions system.cpu.iew.iewDispNonSpecInsts 465 # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents 1563 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewIQFullEvents 1597 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents 48845 # Number of times the LSQ has become full, causing a stall system.cpu.iew.iewLSQFullEvents 48733 # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents 34222 # Number of memory order violations system.cpu.iew.memOrderViolationEvents 33758 # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect 1237215 # Number of branches that were predicted taken incorrectly system.cpu.iew.predictedTakenIncorrect 1219939 # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect 226162 # Number of branches that were predicted not taken incorrectly system.cpu.iew.predictedNotTakenIncorrect 230098 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts 1463377 # Number of branch mispredicts detected at execute system.cpu.iew.branchMispredicts 1450037 # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts 314277739 # Number of executed instructions system.cpu.iew.iewExecutedInsts 314144155 # Number of executed instructions
system.cpu.iew.iewExecLoadInsts 100905928 # Number of load instructions executed system.cpu.iew.iewExecLoadInsts 100864248 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 2095811 # Number of squashed instructions skipped in execute system.cpu.iew.iewExecSquashedInsts 2098231 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_swp 0 # number of swp insts executed
system.cpu.iew.exec_nop 0 # number of nop insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed
system.cpu.iew.exec_refs 134999174 # number of memory reference insts executed system.cpu.iew.exec_refs 134973322 # number of memory reference insts executed
system.cpu.iew.exec_branches 31825957 # Number of branches executed system.cpu.iew.exec_branches 31810521 # Number of branches executed
system.cpu.iew.exec_stores 34093246 # Number of stores executed system.cpu.iew.exec_stores 34109074 # Number of stores executed
system.cpu.iew.exec_rate 2.232903 # Inst execution rate system.cpu.iew.exec_rate 2.233900 # Inst execution rate
system.cpu.iew.wb_sent 313326251 # cumulative count of insts sent to commit system.cpu.iew.wb_sent 313190495 # cumulative count of insts sent to commit
system.cpu.iew.wb_count 312671097 # cumulative count of insts written-back system.cpu.iew.wb_count 312537431 # cumulative count of insts written-back
system.cpu.iew.wb_producers 232527981 # num instructions producing a value system.cpu.iew.wb_producers 232392592 # num instructions producing a value
system.cpu.iew.wb_consumers 318649991 # num instructions consuming a value system.cpu.iew.wb_consumers 318468890 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu.iew.wb_rate 2.221488 # insts written-back per cycle system.cpu.iew.wb_rate 2.222474 # insts written-back per cycle
system.cpu.iew.wb_fanout 0.729729 # average fanout of values written-back system.cpu.iew.wb_fanout 0.729718 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.commit.commitCommittedInsts 278192519 # The number of committed instructions system.cpu.commit.commitCommittedInsts 278192519 # The number of committed instructions
system.cpu.commit.commitSquashedInsts 65767670 # The number of squashed insts skipped by commit system.cpu.commit.commitSquashedInsts 65270328 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 446 # The number of times commit has been forced to stall to communicate backwards system.cpu.commit.commitNonSpecStalls 446 # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts 1330190 # The number of times a branch was mispredicted system.cpu.commit.branchMispredicts 1322946 # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples 130637438 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::samples 130581066 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean 2.129501 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::mean 2.130420 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev 2.662910 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::stdev 2.663472 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0 50443323 38.61% 38.61% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::0 50414718 38.61% 38.61% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1 24364180 18.65% 57.26% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::1 24339651 18.64% 57.25% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2 16505841 12.63% 69.90% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::2 16499074 12.64% 69.88% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3 12375620 9.47% 79.37% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::3 12376450 9.48% 79.36% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4 3710115 2.84% 82.21% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::4 3696747 2.83% 82.19% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5 3458000 2.65% 84.86% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::5 3466084 2.65% 84.85% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6 2751645 2.11% 86.96% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::6 2761727 2.11% 86.96% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7 1180245 0.90% 87.87% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::7 1175320 0.90% 87.86% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8 15848469 12.13% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::8 15851295 12.14% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total 130637438 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::total 130581066 # Number of insts commited each cycle
system.cpu.commit.count 278192519 # Number of instructions committed system.cpu.commit.count 278192519 # Number of instructions committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.refs 122219139 # Number of memory references committed system.cpu.commit.refs 122219139 # Number of memory references committed
@ -255,49 +255,49 @@ system.cpu.commit.branches 29309710 # Nu
system.cpu.commit.fp_insts 40 # Number of committed floating point instructions. system.cpu.commit.fp_insts 40 # Number of committed floating point instructions.
system.cpu.commit.int_insts 278186227 # Number of committed integer instructions. system.cpu.commit.int_insts 278186227 # Number of committed integer instructions.
system.cpu.commit.function_calls 0 # Number of function calls committed. system.cpu.commit.function_calls 0 # Number of function calls committed.
system.cpu.commit.bw_lim_events 15848469 # number cycles where commit BW limit reached system.cpu.commit.bw_lim_events 15851295 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
system.cpu.rob.rob_reads 458749158 # The number of ROB reads system.cpu.rob.rob_reads 458192618 # The number of ROB reads
system.cpu.rob.rob_writes 696922141 # The number of ROB writes system.cpu.rob.rob_writes 695856607 # The number of ROB writes
system.cpu.timesIdled 33627 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.timesIdled 33615 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 1126191 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.idleCycles 1128740 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts 278192519 # Number of Instructions Simulated system.cpu.committedInsts 278192519 # Number of Instructions Simulated
system.cpu.committedInsts_total 278192519 # Number of Instructions Simulated system.cpu.committedInsts_total 278192519 # Number of Instructions Simulated
system.cpu.cpi 0.505939 # CPI: Cycles Per Instruction system.cpu.cpi 0.505498 # CPI: Cycles Per Instruction
system.cpu.cpi_total 0.505939 # CPI: Total CPI of All Threads system.cpu.cpi_total 0.505498 # CPI: Total CPI of All Threads
system.cpu.ipc 1.976523 # IPC: Instructions Per Cycle system.cpu.ipc 1.978245 # IPC: Instructions Per Cycle
system.cpu.ipc_total 1.976523 # IPC: Total IPC of All Threads system.cpu.ipc_total 1.978245 # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads 555004477 # number of integer regfile reads system.cpu.int_regfile_reads 554794614 # number of integer regfile reads
system.cpu.int_regfile_writes 279973081 # number of integer regfile writes system.cpu.int_regfile_writes 279836675 # number of integer regfile writes
system.cpu.fp_regfile_reads 378 # number of floating regfile reads system.cpu.fp_regfile_reads 437 # number of floating regfile reads
system.cpu.fp_regfile_writes 284 # number of floating regfile writes system.cpu.fp_regfile_writes 335 # number of floating regfile writes
system.cpu.misc_regfile_reads 201255053 # number of misc regfile reads system.cpu.misc_regfile_reads 201195947 # number of misc regfile reads
system.cpu.icache.replacements 68 # number of replacements system.cpu.icache.replacements 68 # number of replacements
system.cpu.icache.tagsinuse 824.627975 # Cycle average of tags in use system.cpu.icache.tagsinuse 824.679926 # Cycle average of tags in use
system.cpu.icache.total_refs 28269362 # Total number of references to valid blocks. system.cpu.icache.total_refs 28264985 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 1028 # Sample count of references to valid blocks. system.cpu.icache.sampled_refs 1027 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 27499.379377 # Average number of references to valid blocks. system.cpu.icache.avg_refs 27521.893866 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.occ_blocks::0 824.627975 # Average occupied blocks per context system.cpu.icache.occ_blocks::0 824.679926 # Average occupied blocks per context
system.cpu.icache.occ_percent::0 0.402650 # Average percentage of cache occupancy system.cpu.icache.occ_percent::0 0.402676 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits 28269362 # number of ReadReq hits system.cpu.icache.ReadReq_hits 28264985 # number of ReadReq hits
system.cpu.icache.demand_hits 28269362 # number of demand (read+write) hits system.cpu.icache.demand_hits 28264985 # number of demand (read+write) hits
system.cpu.icache.overall_hits 28269362 # number of overall hits system.cpu.icache.overall_hits 28264985 # number of overall hits
system.cpu.icache.ReadReq_misses 1304 # number of ReadReq misses system.cpu.icache.ReadReq_misses 1306 # number of ReadReq misses
system.cpu.icache.demand_misses 1304 # number of demand (read+write) misses system.cpu.icache.demand_misses 1306 # number of demand (read+write) misses
system.cpu.icache.overall_misses 1304 # number of overall misses system.cpu.icache.overall_misses 1306 # number of overall misses
system.cpu.icache.ReadReq_miss_latency 47096500 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_latency 47073500 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency 47096500 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_latency 47073500 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency 47096500 # number of overall miss cycles system.cpu.icache.overall_miss_latency 47073500 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses 28270666 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses 28266291 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses 28270666 # number of demand (read+write) accesses system.cpu.icache.demand_accesses 28266291 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses 28270666 # number of overall (read+write) accesses system.cpu.icache.overall_accesses 28266291 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate 0.000046 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate 0.000046 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate 0.000046 # miss rate for demand accesses system.cpu.icache.demand_miss_rate 0.000046 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate 0.000046 # miss rate for overall accesses system.cpu.icache.overall_miss_rate 0.000046 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency 36116.947853 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_miss_latency 36044.027565 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency 36116.947853 # average overall miss latency system.cpu.icache.demand_avg_miss_latency 36044.027565 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency 36116.947853 # average overall miss latency system.cpu.icache.overall_avg_miss_latency 36044.027565 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
@ -307,166 +307,166 @@ system.cpu.icache.avg_blocked_cycles::no_targets no_value
system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.writebacks 0 # number of writebacks system.cpu.icache.writebacks 0 # number of writebacks
system.cpu.icache.ReadReq_mshr_hits 275 # number of ReadReq MSHR hits system.cpu.icache.ReadReq_mshr_hits 278 # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits 275 # number of demand (read+write) MSHR hits system.cpu.icache.demand_mshr_hits 278 # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits 275 # number of overall MSHR hits system.cpu.icache.overall_mshr_hits 278 # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses 1029 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses 1028 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses 1029 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses 1028 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses 1029 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses 1028 # number of overall MSHR misses
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.icache.ReadReq_mshr_miss_latency 36215000 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_latency 36154500 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency 36215000 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_latency 36154500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency 36215000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency 36154500 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.icache.ReadReq_mshr_miss_rate 0.000036 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate 0.000036 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate 0.000036 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate 0.000036 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate 0.000036 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate 0.000036 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency 35194.363460 # average ReadReq mshr miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency 35169.747082 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency 35194.363460 # average overall mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency 35169.747082 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 35194.363460 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency 35169.747082 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 2073072 # number of replacements system.cpu.dcache.replacements 2073066 # number of replacements
system.cpu.dcache.tagsinuse 4076.002534 # Cycle average of tags in use system.cpu.dcache.tagsinuse 4076.005888 # Cycle average of tags in use
system.cpu.dcache.total_refs 83850634 # Total number of references to valid blocks. system.cpu.dcache.total_refs 83808707 # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs 2077168 # Sample count of references to valid blocks. system.cpu.dcache.sampled_refs 2077162 # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs 40.367767 # Average number of references to valid blocks. system.cpu.dcache.avg_refs 40.347699 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 23897616000 # Cycle when the warmup percentage was hit. system.cpu.dcache.warmup_cycle 23845092000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::0 4076.002534 # Average occupied blocks per context system.cpu.dcache.occ_blocks::0 4076.005888 # Average occupied blocks per context
system.cpu.dcache.occ_percent::0 0.995118 # Average percentage of cache occupancy system.cpu.dcache.occ_percent::0 0.995119 # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits 52653882 # number of ReadReq hits system.cpu.dcache.ReadReq_hits 52611944 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits 31196743 # number of WriteReq hits system.cpu.dcache.WriteReq_hits 31196754 # number of WriteReq hits
system.cpu.dcache.demand_hits 83850625 # number of demand (read+write) hits system.cpu.dcache.demand_hits 83808698 # number of demand (read+write) hits
system.cpu.dcache.overall_hits 83850625 # number of overall hits system.cpu.dcache.overall_hits 83808698 # number of overall hits
system.cpu.dcache.ReadReq_misses 2263157 # number of ReadReq misses system.cpu.dcache.ReadReq_misses 2262875 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses 243008 # number of WriteReq misses system.cpu.dcache.WriteReq_misses 242997 # number of WriteReq misses
system.cpu.dcache.demand_misses 2506165 # number of demand (read+write) misses system.cpu.dcache.demand_misses 2505872 # number of demand (read+write) misses
system.cpu.dcache.overall_misses 2506165 # number of overall misses system.cpu.dcache.overall_misses 2505872 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency 14623728000 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_latency 14629803500 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency 4401886592 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_latency 4394648436 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency 19025614592 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_latency 19024451936 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency 19025614592 # number of overall miss cycles system.cpu.dcache.overall_miss_latency 19024451936 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses 54917039 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses 54874819 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses 31439751 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses 31439751 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.demand_accesses 86356790 # number of demand (read+write) accesses system.cpu.dcache.demand_accesses 86314570 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses 86356790 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses 86314570 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate 0.041210 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate 0.041237 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate 0.007729 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate 0.007729 # miss rate for WriteReq accesses
system.cpu.dcache.demand_miss_rate 0.029021 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate 0.029032 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate 0.029021 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate 0.029032 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency 6461.649810 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency 6465.139922 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency 18114.163287 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency 18085.196262 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency 7591.525136 # average overall miss latency system.cpu.dcache.demand_avg_miss_latency 7591.948805 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency 7591.525136 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency 7591.948805 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 296000 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_mshrs 289000 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 93 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 92 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs 3182.795699 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs 3141.304348 # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.writebacks 1447092 # number of writebacks system.cpu.dcache.writebacks 1447147 # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits 291450 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_hits 291175 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits 137543 # number of WriteReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits 137531 # number of WriteReq MSHR hits
system.cpu.dcache.demand_mshr_hits 428993 # number of demand (read+write) MSHR hits system.cpu.dcache.demand_mshr_hits 428706 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits 428993 # number of overall MSHR hits system.cpu.dcache.overall_mshr_hits 428706 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses 1971707 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses 1971700 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses 105465 # number of WriteReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses 105466 # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses 2077172 # number of demand (read+write) MSHR misses system.cpu.dcache.demand_mshr_misses 2077166 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses 2077172 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses 2077166 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.dcache.ReadReq_mshr_miss_latency 5599733000 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_latency 5609142000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency 1876757592 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency 1870309936 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency 7476490592 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_latency 7479451936 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency 7476490592 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency 7479451936 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_miss_rate 0.035903 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate 0.035931 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate 0.003355 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate 0.003355 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate 0.024053 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate 0.024065 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate 0.024053 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate 0.024065 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2840.043171 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2844.825278 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 17795.075068 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency 17733.771414 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 3599.360377 # average overall mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency 3600.796439 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 3599.360377 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency 3600.796439 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 49070 # number of replacements system.cpu.l2cache.replacements 49057 # number of replacements
system.cpu.l2cache.tagsinuse 18849.812777 # Cycle average of tags in use system.cpu.l2cache.tagsinuse 18859.305089 # Cycle average of tags in use
system.cpu.l2cache.total_refs 3318008 # Total number of references to valid blocks. system.cpu.l2cache.total_refs 3318010 # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs 77081 # Sample count of references to valid blocks. system.cpu.l2cache.sampled_refs 77063 # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs 43.045731 # Average number of references to valid blocks. system.cpu.l2cache.avg_refs 43.055811 # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.occ_blocks::0 6745.826593 # Average occupied blocks per context system.cpu.l2cache.occ_blocks::0 6747.919367 # Average occupied blocks per context
system.cpu.l2cache.occ_blocks::1 12103.986183 # Average occupied blocks per context system.cpu.l2cache.occ_blocks::1 12111.385721 # Average occupied blocks per context
system.cpu.l2cache.occ_percent::0 0.205866 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::0 0.205930 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::1 0.369384 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::1 0.369610 # Average percentage of cache occupancy
system.cpu.l2cache.ReadReq_hits 1938133 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits 1938157 # number of ReadReq hits
system.cpu.l2cache.Writeback_hits 1447092 # number of Writeback hits system.cpu.l2cache.Writeback_hits 1447147 # number of Writeback hits
system.cpu.l2cache.ReadExReq_hits 63539 # number of ReadExReq hits system.cpu.l2cache.ReadExReq_hits 63526 # number of ReadExReq hits
system.cpu.l2cache.demand_hits 2001672 # number of demand (read+write) hits system.cpu.l2cache.demand_hits 2001683 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits 2001672 # number of overall hits system.cpu.l2cache.overall_hits 2001683 # number of overall hits
system.cpu.l2cache.ReadReq_misses 34492 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses 34474 # number of ReadReq misses
system.cpu.l2cache.UpgradeReq_misses 1 # number of UpgradeReq misses system.cpu.l2cache.UpgradeReq_misses 1 # number of UpgradeReq misses
system.cpu.l2cache.ReadExReq_misses 42035 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_misses 42035 # number of ReadExReq misses
system.cpu.l2cache.demand_misses 76527 # number of demand (read+write) misses system.cpu.l2cache.demand_misses 76509 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses 76527 # number of overall misses system.cpu.l2cache.overall_misses 76509 # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency 1179607000 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_latency 1179443000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency 1438839000 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency 1438838000 # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency 2618446000 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_latency 2618281000 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency 2618446000 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency 2618281000 # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses 1972625 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses 1972631 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses 1447092 # number of Writeback accesses(hits+misses) system.cpu.l2cache.Writeback_accesses 1447147 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses 1 # number of UpgradeReq accesses(hits+misses) system.cpu.l2cache.UpgradeReq_accesses 1 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses 105574 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses 105561 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses 2078199 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses 2078192 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses 2078199 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses 2078192 # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate 0.017485 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate 0.017476 # miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_miss_rate 0.398157 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_miss_rate 0.398206 # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate 0.036824 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate 0.036815 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate 0.036824 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate 0.036815 # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency 34199.437551 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency 34212.536984 # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency 34229.546806 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency 34229.523017 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency 34215.976061 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency 34221.869323 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency 34215.976061 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency 34221.869323 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 39000 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_mshrs 37500 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 14 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 14 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs 2785.714286 # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_mshrs 2678.571429 # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.writebacks 29193 # number of writebacks system.cpu.l2cache.writebacks 29185 # number of writebacks
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
system.cpu.l2cache.ReadReq_mshr_misses 34492 # number of ReadReq MSHR misses system.cpu.l2cache.ReadReq_mshr_misses 34474 # number of ReadReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses 1 # number of UpgradeReq MSHR misses system.cpu.l2cache.UpgradeReq_mshr_misses 1 # number of UpgradeReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses 42035 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses 42035 # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses 76527 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses 76509 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses 76527 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses 76509 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.l2cache.ReadReq_mshr_miss_latency 1069993000 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_latency 1069429500 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency 31000 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_latency 31000 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency 1307215500 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency 1307209000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency 2377208500 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency 2376638500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency 2377208500 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency 2376638500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.017485 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate 0.017476 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.398157 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.398206 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate 0.036824 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate 0.036815 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate 0.036824 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate 0.036815 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31021.483242 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31021.334919 # average ReadReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31000 # average UpgradeReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31000 # average UpgradeReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31098.263352 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31098.108719 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency 31063.657271 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency 31063.515403 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 31063.657271 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 31063.515403 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions

9
tests/long/20.parser/ref/x86/linux/o3-timing/simout
View file

@ -3,10 +3,11 @@ Redirecting stderr to build/X86_SE/tests/opt/long/20.parser/x86/linux/o3-timing/
gem5 Simulator System. http://gem5.org gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details. gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Aug 20 2011 13:24:14 gem5 compiled Nov 16 2011 11:08:03
gem5 started Aug 20 2011 13:24:28 gem5 started Nov 17 2011 13:09:16
gem5 executing on zizzer gem5 executing on ribera.cs.wisc.edu
command line: build/X86_SE/gem5.opt -d build/X86_SE/tests/opt/long/20.parser/x86/linux/o3-timing -re tests/run.py build/X86_SE/tests/opt/long/20.parser/x86/linux/o3-timing command line: build/X86_SE/gem5.opt -d build/X86_SE/tests/opt/long/20.parser/x86/linux/o3-timing -re tests/run.py build/X86_SE/tests/opt/long/20.parser/x86/linux/o3-timing
tests
Global frequency set at 1000000000000 ticks per second Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation... info: Entering event queue @ 0. Starting simulation...
@ -81,4 +82,4 @@ info: Increasing stack size by one page.
about 2 million people attended about 2 million people attended
the five best costumes got prizes the five best costumes got prizes
No errors! No errors!
Exiting @ tick 493847859500 because target called exit() Exiting @ tick 494093841000 because target called exit()

714
tests/long/20.parser/ref/x86/linux/o3-timing/stats.txt
View file

@ -1,149 +1,149 @@
---------- Begin Simulation Statistics ---------- ---------- Begin Simulation Statistics ----------
sim_seconds 0.493848 # Number of seconds simulated sim_seconds 0.494094 # Number of seconds simulated
sim_ticks 493847859500 # Number of ticks simulated sim_ticks 494093841000 # Number of ticks simulated
sim_freq 1000000000000 # Frequency of simulated ticks sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 141014 # Simulator instruction rate (inst/s) host_inst_rate 111156 # Simulator instruction rate (inst/s)
host_tick_rate 45545926 # Simulator tick rate (ticks/s) host_tick_rate 35920075 # Simulator tick rate (ticks/s)
host_mem_usage 250808 # Number of bytes of host memory used host_mem_usage 281020 # Number of bytes of host memory used
host_seconds 10842.85 # Real time elapsed on the host host_seconds 13755.37 # Real time elapsed on the host
sim_insts 1528988756 # Number of instructions simulated sim_insts 1528988756 # Number of instructions simulated
system.cpu.workload.num_syscalls 551 # Number of system calls system.cpu.workload.num_syscalls 551 # Number of system calls
system.cpu.numCycles 987695720 # number of cpu cycles simulated system.cpu.numCycles 988187683 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.BPredUnit.lookups 245701836 # Number of BP lookups system.cpu.BPredUnit.lookups 245753731 # Number of BP lookups
system.cpu.BPredUnit.condPredicted 245701836 # Number of conditional branches predicted system.cpu.BPredUnit.condPredicted 245753731 # Number of conditional branches predicted
system.cpu.BPredUnit.condIncorrect 16595687 # Number of conditional branches incorrect system.cpu.BPredUnit.condIncorrect 16579058 # Number of conditional branches incorrect
system.cpu.BPredUnit.BTBLookups 236380847 # Number of BTB lookups system.cpu.BPredUnit.BTBLookups 236460078 # Number of BTB lookups
system.cpu.BPredUnit.BTBHits 218346080 # Number of BTB hits system.cpu.BPredUnit.BTBHits 218454939 # Number of BTB hits
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target. system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target.
system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions. system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions.
system.cpu.fetch.icacheStallCycles 205619767 # Number of cycles fetch is stalled on an Icache miss system.cpu.fetch.icacheStallCycles 205538766 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts 1343825400 # Number of instructions fetch has processed system.cpu.fetch.Insts 1343537923 # Number of instructions fetch has processed
system.cpu.fetch.Branches 245701836 # Number of branches that fetch encountered system.cpu.fetch.Branches 245753731 # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches 218346080 # Number of branches that fetch has predicted taken system.cpu.fetch.predictedBranches 218454939 # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles 436746169 # Number of cycles fetch has run and was not squashing or blocked system.cpu.fetch.Cycles 436709904 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles 120030037 # Number of cycles fetch has spent squashing system.cpu.fetch.SquashCycles 120016352 # Number of cycles fetch has spent squashing
system.cpu.fetch.BlockedCycles 218211728 # Number of cycles fetch has spent blocked system.cpu.fetch.BlockedCycles 218837683 # Number of cycles fetch has spent blocked
system.cpu.fetch.MiscStallCycles 32810 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu.fetch.MiscStallCycles 33103 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles 394519 # Number of stall cycles due to pending traps system.cpu.fetch.PendingTrapStallCycles 345399 # Number of stall cycles due to pending traps
system.cpu.fetch.CacheLines 194794908 # Number of cache lines fetched system.cpu.fetch.CacheLines 194719765 # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes 4074174 # Number of outstanding Icache misses that were squashed system.cpu.fetch.IcacheSquashes 4085375 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.rateDist::samples 964173518 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::samples 964635983 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean 2.600326 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::mean 2.598912 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev 3.317708 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::stdev 3.317298 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0 531478687 55.12% 55.12% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::0 531979476 55.15% 55.15% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1 32400706 3.36% 58.48% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::1 32383346 3.36% 58.51% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2 38829894 4.03% 62.51% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::2 38813168 4.02% 62.53% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3 32544605 3.38% 65.89% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::3 32534184 3.37% 65.90% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4 21858974 2.27% 68.15% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::4 21860326 2.27% 68.17% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5 36433886 3.78% 71.93% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::5 36455994 3.78% 71.95% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6 49094534 5.09% 77.02% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::6 49125826 5.09% 77.04% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7 36959436 3.83% 80.86% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::7 36953777 3.83% 80.87% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8 184572796 19.14% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::8 184529886 19.13% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total 964173518 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::total 964635983 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate 0.248763 # Number of branch fetches per cycle system.cpu.fetch.branchRate 0.248691 # Number of branch fetches per cycle
system.cpu.fetch.rate 1.360566 # Number of inst fetches per cycle system.cpu.fetch.rate 1.359598 # Number of inst fetches per cycle
system.cpu.decode.IdleCycles 264598468 # Number of cycles decode is idle system.cpu.decode.IdleCycles 264568111 # Number of cycles decode is idle
system.cpu.decode.BlockedCycles 174292947 # Number of cycles decode is blocked system.cpu.decode.BlockedCycles 174813294 # Number of cycles decode is blocked
system.cpu.decode.RunCycles 373121057 # Number of cycles decode is running system.cpu.decode.RunCycles 373028079 # Number of cycles decode is running
system.cpu.decode.UnblockCycles 48992521 # Number of cycles decode is unblocking system.cpu.decode.UnblockCycles 49055371 # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles 103168525 # Number of cycles decode is squashing system.cpu.decode.SquashCycles 103171128 # Number of cycles decode is squashing
system.cpu.decode.DecodedInsts 2446276906 # Number of instructions handled by decode system.cpu.decode.DecodedInsts 2446190376 # Number of instructions handled by decode
system.cpu.decode.SquashedInsts 2 # Number of squashed instructions handled by decode system.cpu.decode.SquashedInsts 2 # Number of squashed instructions handled by decode
system.cpu.rename.SquashCycles 103168525 # Number of cycles rename is squashing system.cpu.rename.SquashCycles 103171128 # Number of cycles rename is squashing
system.cpu.rename.IdleCycles 301836329 # Number of cycles rename is idle system.cpu.rename.IdleCycles 301809231 # Number of cycles rename is idle
system.cpu.rename.BlockCycles 39995204 # Number of cycles rename is blocking system.cpu.rename.BlockCycles 40269862 # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles 12425 # count of cycles rename stalled for serializing inst system.cpu.rename.serializeStallCycles 9996 # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles 383530410 # Number of cycles rename is running system.cpu.rename.RunCycles 383504038 # Number of cycles rename is running
system.cpu.rename.UnblockCycles 135630625 # Number of cycles rename is unblocking system.cpu.rename.UnblockCycles 135871728 # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts 2393744264 # Number of instructions processed by rename system.cpu.rename.RenamedInsts 2393655047 # Number of instructions processed by rename
system.cpu.rename.ROBFullEvents 2638 # Number of times rename has blocked due to ROB full system.cpu.rename.ROBFullEvents 2663 # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents 25354791 # Number of times rename has blocked due to IQ full system.cpu.rename.IQFullEvents 25553817 # Number of times rename has blocked due to IQ full
system.cpu.rename.LSQFullEvents 92046607 # Number of times rename has blocked due to LSQ full system.cpu.rename.LSQFullEvents 92121641 # Number of times rename has blocked due to LSQ full
system.cpu.rename.FullRegisterEvents 28 # Number of times there has been no free registers system.cpu.rename.FullRegisterEvents 4 # Number of times there has been no free registers
system.cpu.rename.RenamedOperands 2227310497 # Number of destination operands rename has renamed system.cpu.rename.RenamedOperands 2227336205 # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups 5630161832 # Number of register rename lookups that rename has made system.cpu.rename.RenameLookups 5630423595 # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups 5629928430 # Number of integer rename lookups system.cpu.rename.int_rename_lookups 5630180918 # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups 233402 # Number of floating rename lookups system.cpu.rename.fp_rename_lookups 242677 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 1427299027 # Number of HB maps that are committed system.cpu.rename.CommittedMaps 1427299027 # Number of HB maps that are committed
system.cpu.rename.UndoneMaps 800011470 # Number of HB maps that are undone due to squashing system.cpu.rename.UndoneMaps 800037178 # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts 1318 # count of serializing insts renamed system.cpu.rename.serializingInsts 1323 # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts 1303 # count of temporary serializing insts renamed system.cpu.rename.tempSerializingInsts 1277 # count of temporary serializing insts renamed
system.cpu.rename.skidInsts 319166295 # count of insts added to the skid buffer system.cpu.rename.skidInsts 319257105 # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads 577919050 # Number of loads inserted to the mem dependence unit. system.cpu.memDep0.insertedLoads 577954406 # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores 226606684 # Number of stores inserted to the mem dependence unit. system.cpu.memDep0.insertedStores 226554784 # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads 227271329 # Number of conflicting loads. system.cpu.memDep0.conflictingLoads 227345729 # Number of conflicting loads.
system.cpu.memDep0.conflictingStores 66051723 # Number of conflicting stores. system.cpu.memDep0.conflictingStores 66055755 # Number of conflicting stores.
system.cpu.iq.iqInstsAdded 2286915029 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqInstsAdded 2286934263 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded 6159 # Number of non-speculative instructions added to the IQ system.cpu.iq.iqNonSpecInstsAdded 9822 # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued 1922683409 # Number of instructions issued system.cpu.iq.iqInstsIssued 1922478378 # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued 1316831 # Number of squashed instructions issued system.cpu.iq.iqSquashedInstsIssued 1310077 # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined 755416366 # Number of squashed instructions iterated over during squash; mainly for profiling system.cpu.iq.iqSquashedInstsExamined 755451043 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined 1189575311 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedOperandsExamined 1190251690 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved 5606 # Number of squashed non-spec instructions that were removed system.cpu.iq.iqSquashedNonSpecRemoved 9269 # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples 964173518 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::samples 964635983 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean 1.994126 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::mean 1.992957 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev 1.811461 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::stdev 1.810982 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0 282941420 29.35% 29.35% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::0 283040019 29.34% 29.34% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1 159777972 16.57% 45.92% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::1 160280005 16.62% 45.96% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2 162985907 16.90% 62.82% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::2 162996180 16.90% 62.85% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3 148632114 15.42% 78.24% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::3 148777682 15.42% 78.28% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4 109327758 11.34% 89.58% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::4 109013815 11.30% 89.58% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5 60035944 6.23% 95.80% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::5 60046720 6.22% 95.80% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6 30803018 3.19% 99.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::6 30822079 3.20% 99.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7 8626659 0.89% 99.89% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 8624231 0.89% 99.89% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8 1042726 0.11% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 1035252 0.11% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total 964173518 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::total 964635983 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu 2258663 14.74% 14.74% # attempts to use FU when none available system.cpu.iq.fu_full::IntAlu 2243375 14.67% 14.67% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult 0 0.00% 14.74% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 0 0.00% 14.67% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv 0 0.00% 14.74% # attempts to use FU when none available system.cpu.iq.fu_full::IntDiv 0 0.00% 14.67% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd 0 0.00% 14.74% # attempts to use FU when none available system.cpu.iq.fu_full::FloatAdd 0 0.00% 14.67% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp 0 0.00% 14.74% # attempts to use FU when none available system.cpu.iq.fu_full::FloatCmp 0 0.00% 14.67% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt 0 0.00% 14.74% # attempts to use FU when none available system.cpu.iq.fu_full::FloatCvt 0 0.00% 14.67% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult 0 0.00% 14.74% # attempts to use FU when none available system.cpu.iq.fu_full::FloatMult 0 0.00% 14.67% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv 0 0.00% 14.74% # attempts to use FU when none available system.cpu.iq.fu_full::FloatDiv 0 0.00% 14.67% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 14.74% # attempts to use FU when none available system.cpu.iq.fu_full::FloatSqrt 0 0.00% 14.67% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd 0 0.00% 14.74% # attempts to use FU when none available system.cpu.iq.fu_full::SimdAdd 0 0.00% 14.67% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 14.74% # attempts to use FU when none available system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 14.67% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu 0 0.00% 14.74% # attempts to use FU when none available system.cpu.iq.fu_full::SimdAlu 0 0.00% 14.67% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp 0 0.00% 14.74% # attempts to use FU when none available system.cpu.iq.fu_full::SimdCmp 0 0.00% 14.67% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt 0 0.00% 14.74% # attempts to use FU when none available system.cpu.iq.fu_full::SimdCvt 0 0.00% 14.67% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc 0 0.00% 14.74% # attempts to use FU when none available system.cpu.iq.fu_full::SimdMisc 0 0.00% 14.67% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult 0 0.00% 14.74% # attempts to use FU when none available system.cpu.iq.fu_full::SimdMult 0 0.00% 14.67% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 14.74% # attempts to use FU when none available system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 14.67% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift 0 0.00% 14.74% # attempts to use FU when none available system.cpu.iq.fu_full::SimdShift 0 0.00% 14.67% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 14.74% # attempts to use FU when none available system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 14.67% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 14.74% # attempts to use FU when none available system.cpu.iq.fu_full::SimdSqrt 0 0.00% 14.67% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 14.74% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 14.67% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 14.74% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 14.67% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 14.74% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 14.67% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 14.74% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 14.67% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 14.74% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 14.67% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 14.74% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 14.67% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 14.74% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 14.67% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 14.74% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 14.67% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 14.74% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 14.67% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead 9960479 65.00% 79.74% # attempts to use FU when none available system.cpu.iq.fu_full::MemRead 9951583 65.07% 79.74% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite 3103804 20.26% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::MemWrite 3098283 20.26% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 2419995 0.13% 0.13% # Type of FU issued system.cpu.iq.FU_type_0::No_OpClass 2418078 0.13% 0.13% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu 1274972987 66.31% 66.44% # Type of FU issued system.cpu.iq.FU_type_0::IntAlu 1274783906 66.31% 66.44% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult 0 0.00% 66.44% # Type of FU issued system.cpu.iq.FU_type_0::IntMult 0 0.00% 66.44% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 66.44% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 66.44% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd 9 0.00% 66.44% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 3 0.00% 66.44% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.44% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.44% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.44% # Type of FU issued system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.44% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 66.44% # Type of FU issued system.cpu.iq.FU_type_0::FloatMult 0 0.00% 66.44% # Type of FU issued
@ -169,85 +169,85 @@ system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.44% # Ty
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.44% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.44% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.44% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.44% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.44% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.44% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead 463702844 24.12% 90.56% # Type of FU issued system.cpu.iq.FU_type_0::MemRead 463737726 24.12% 90.56% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite 181587574 9.44% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::MemWrite 181538665 9.44% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::total 1922683409 # Type of FU issued system.cpu.iq.FU_type_0::total 1922478378 # Type of FU issued
system.cpu.iq.rate 1.946635 # Inst issue rate system.cpu.iq.rate 1.945459 # Inst issue rate
system.cpu.iq.fu_busy_cnt 15322946 # FU busy when requested system.cpu.iq.fu_busy_cnt 15293241 # FU busy when requested
system.cpu.iq.fu_busy_rate 0.007970 # FU busy rate (busy events/executed inst) system.cpu.iq.fu_busy_rate 0.007955 # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads 4826174769 # Number of integer instruction queue reads system.cpu.iq.int_inst_queue_reads 4826191069 # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes 3042532180 # Number of integer instruction queue writes system.cpu.iq.int_inst_queue_writes 3042585561 # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses 1874952899 # Number of integer instruction queue wakeup accesses system.cpu.iq.int_inst_queue_wakeup_accesses 1874784055 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 5344 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_reads 4988 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes 78632 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_writes 82956 # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses 143 # Number of floating instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_wakeup_accesses 103 # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses 1935584605 # Number of integer alu accesses system.cpu.iq.int_alu_accesses 1935351994 # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses 1755 # Number of floating point alu accesses system.cpu.iq.fp_alu_accesses 1547 # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads 158265730 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.forwLoads 158191943 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread0.squashedLoads 193816890 # Number of loads squashed system.cpu.iew.lsq.thread0.squashedLoads 193852246 # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses 368616 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread0.ignoredResponses 372238 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation 283851 # Number of memory ordering violations system.cpu.iew.lsq.thread0.memOrderViolation 283888 # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores 77446847 # Number of stores squashed system.cpu.iew.lsq.thread0.squashedStores 77394965 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads 2334 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.rescheduledLoads 2343 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked 14 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.lsq.thread0.cacheBlocked 34 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
system.cpu.iew.iewSquashCycles 103168525 # Number of cycles IEW is squashing system.cpu.iew.iewSquashCycles 103171128 # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles 9000117 # Number of cycles IEW is blocking system.cpu.iew.iewBlockCycles 9041820 # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles 1434115 # Number of cycles IEW is unblocking system.cpu.iew.iewUnblockCycles 1420232 # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts 2286921188 # Number of instructions dispatched to IQ system.cpu.iew.iewDispatchedInsts 2286944085 # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts 1114031 # Number of squashed instructions skipped by dispatch system.cpu.iew.iewDispSquashedInsts 1121311 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts 577919050 # Number of dispatched load instructions system.cpu.iew.iewDispLoadInsts 577954406 # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts 226607032 # Number of dispatched store instructions system.cpu.iew.iewDispStoreInsts 226555150 # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts 6159 # Number of dispatched non-speculative instructions system.cpu.iew.iewDispNonSpecInsts 6075 # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents 1032728 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewIQFullEvents 1022506 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents 29962 # Number of times the LSQ has become full, causing a stall system.cpu.iew.iewLSQFullEvents 29752 # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents 283851 # Number of memory order violations system.cpu.iew.memOrderViolationEvents 283888 # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect 15679501 # Number of branches that were predicted taken incorrectly system.cpu.iew.predictedTakenIncorrect 15692203 # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect 2385329 # Number of branches that were predicted not taken incorrectly system.cpu.iew.predictedNotTakenIncorrect 2347782 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts 18064830 # Number of branch mispredicts detected at execute system.cpu.iew.branchMispredicts 18039985 # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts 1889474492 # Number of executed instructions system.cpu.iew.iewExecutedInsts 1889278448 # Number of executed instructions
system.cpu.iew.iewExecLoadInsts 454765570 # Number of load instructions executed system.cpu.iew.iewExecLoadInsts 454785721 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 33208917 # Number of squashed instructions skipped in execute system.cpu.iew.iewExecSquashedInsts 33199930 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_swp 0 # number of swp insts executed
system.cpu.iew.exec_nop 0 # number of nop insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed
system.cpu.iew.exec_refs 629342688 # number of memory reference insts executed system.cpu.iew.exec_refs 629316980 # number of memory reference insts executed
system.cpu.iew.exec_branches 176743901 # Number of branches executed system.cpu.iew.exec_branches 176731992 # Number of branches executed
system.cpu.iew.exec_stores 174577118 # Number of stores executed system.cpu.iew.exec_stores 174531259 # Number of stores executed
system.cpu.iew.exec_rate 1.913013 # Inst execution rate system.cpu.iew.exec_rate 1.911862 # Inst execution rate
system.cpu.iew.wb_sent 1882825411 # cumulative count of insts sent to commit system.cpu.iew.wb_sent 1882655317 # cumulative count of insts sent to commit
system.cpu.iew.wb_count 1874953042 # cumulative count of insts written-back system.cpu.iew.wb_count 1874784158 # cumulative count of insts written-back
system.cpu.iew.wb_producers 1440779649 # num instructions producing a value system.cpu.iew.wb_producers 1440755706 # num instructions producing a value
system.cpu.iew.wb_consumers 2134933130 # num instructions consuming a value system.cpu.iew.wb_consumers 2135030641 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu.iew.wb_rate 1.898310 # insts written-back per cycle system.cpu.iew.wb_rate 1.897194 # insts written-back per cycle
system.cpu.iew.wb_fanout 0.674859 # average fanout of values written-back system.cpu.iew.wb_fanout 0.674817 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.commit.commitCommittedInsts 1528988756 # The number of committed instructions system.cpu.commit.commitCommittedInsts 1528988756 # The number of committed instructions
system.cpu.commit.commitSquashedInsts 757942908 # The number of squashed insts skipped by commit system.cpu.commit.commitSquashedInsts 757965703 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 553 # The number of times commit has been forced to stall to communicate backwards system.cpu.commit.commitNonSpecStalls 553 # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts 16623561 # The number of times a branch was mispredicted system.cpu.commit.branchMispredicts 16607079 # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples 861004993 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::samples 861464855 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean 1.775819 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::mean 1.774871 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev 2.288206 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::stdev 2.287572 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0 338275347 39.29% 39.29% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::0 338524013 39.30% 39.30% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1 210593488 24.46% 63.75% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::1 210779915 24.47% 63.76% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2 75171542 8.73% 72.48% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::2 75257513 8.74% 72.50% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3 92637359 10.76% 83.24% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::3 92637954 10.75% 83.25% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4 34049472 3.95% 87.19% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::4 34058407 3.95% 87.21% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5 27973994 3.25% 90.44% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::5 27966548 3.25% 90.45% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6 16051033 1.86% 92.31% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::6 15953506 1.85% 92.31% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7 12256013 1.42% 93.73% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::7 12303443 1.43% 93.73% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8 53996745 6.27% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::8 53983556 6.27% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total 861004993 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::total 861464855 # Number of insts commited each cycle
system.cpu.commit.count 1528988756 # Number of instructions committed system.cpu.commit.count 1528988756 # Number of instructions committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.refs 533262345 # Number of memory references committed system.cpu.commit.refs 533262345 # Number of memory references committed
@ -257,49 +257,49 @@ system.cpu.commit.branches 149758588 # Nu
system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. system.cpu.commit.fp_insts 0 # Number of committed floating point instructions.
system.cpu.commit.int_insts 1528317614 # Number of committed integer instructions. system.cpu.commit.int_insts 1528317614 # Number of committed integer instructions.
system.cpu.commit.function_calls 0 # Number of function calls committed. system.cpu.commit.function_calls 0 # Number of function calls committed.
system.cpu.commit.bw_lim_events 53996745 # number cycles where commit BW limit reached system.cpu.commit.bw_lim_events 53983556 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
system.cpu.rob.rob_reads 3093939912 # The number of ROB reads system.cpu.rob.rob_reads 3094435758 # The number of ROB reads
system.cpu.rob.rob_writes 4677211584 # The number of ROB writes system.cpu.rob.rob_writes 4677260376 # The number of ROB writes
system.cpu.timesIdled 604649 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.timesIdled 606046 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 23522202 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.idleCycles 23551700 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts 1528988756 # Number of Instructions Simulated system.cpu.committedInsts 1528988756 # Number of Instructions Simulated
system.cpu.committedInsts_total 1528988756 # Number of Instructions Simulated system.cpu.committedInsts_total 1528988756 # Number of Instructions Simulated
system.cpu.cpi 0.645980 # CPI: Cycles Per Instruction system.cpu.cpi 0.646301 # CPI: Cycles Per Instruction
system.cpu.cpi_total 0.645980 # CPI: Total CPI of All Threads system.cpu.cpi_total 0.646301 # CPI: Total CPI of All Threads
system.cpu.ipc 1.548036 # IPC: Instructions Per Cycle system.cpu.ipc 1.547266 # IPC: Instructions Per Cycle
system.cpu.ipc_total 1.548036 # IPC: Total IPC of All Threads system.cpu.ipc_total 1.547266 # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads 3179615221 # number of integer regfile reads system.cpu.int_regfile_reads 3179235417 # number of integer regfile reads
system.cpu.int_regfile_writes 1745014633 # number of integer regfile writes system.cpu.int_regfile_writes 1744932190 # number of integer regfile writes
system.cpu.fp_regfile_reads 160 # number of floating regfile reads system.cpu.fp_regfile_reads 109 # number of floating regfile reads
system.cpu.fp_regfile_writes 9 # number of floating regfile writes system.cpu.fp_regfile_writes 3 # number of floating regfile writes
system.cpu.misc_regfile_reads 1039384818 # number of misc regfile reads system.cpu.misc_regfile_reads 1039364909 # number of misc regfile reads
system.cpu.icache.replacements 9994 # number of replacements system.cpu.icache.replacements 9996 # number of replacements
system.cpu.icache.tagsinuse 979.138170 # Cycle average of tags in use system.cpu.icache.tagsinuse 975.733254 # Cycle average of tags in use
system.cpu.icache.total_refs 194574782 # Total number of references to valid blocks. system.cpu.icache.total_refs 194489021 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 11491 # Sample count of references to valid blocks. system.cpu.icache.sampled_refs 11497 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 16932.798016 # Average number of references to valid blocks. system.cpu.icache.avg_refs 16916.501783 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.occ_blocks::0 979.138170 # Average occupied blocks per context system.cpu.icache.occ_blocks::0 975.733254 # Average occupied blocks per context
system.cpu.icache.occ_percent::0 0.478095 # Average percentage of cache occupancy system.cpu.icache.occ_percent::0 0.476432 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits 194581368 # number of ReadReq hits system.cpu.icache.ReadReq_hits 194495909 # number of ReadReq hits
system.cpu.icache.demand_hits 194581368 # number of demand (read+write) hits system.cpu.icache.demand_hits 194495909 # number of demand (read+write) hits
system.cpu.icache.overall_hits 194581368 # number of overall hits system.cpu.icache.overall_hits 194495909 # number of overall hits
system.cpu.icache.ReadReq_misses 213540 # number of ReadReq misses system.cpu.icache.ReadReq_misses 223856 # number of ReadReq misses
system.cpu.icache.demand_misses 213540 # number of demand (read+write) misses system.cpu.icache.demand_misses 223856 # number of demand (read+write) misses
system.cpu.icache.overall_misses 213540 # number of overall misses system.cpu.icache.overall_misses 223856 # number of overall misses
system.cpu.icache.ReadReq_miss_latency 1483328000 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_latency 1547338000 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency 1483328000 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_latency 1547338000 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency 1483328000 # number of overall miss cycles system.cpu.icache.overall_miss_latency 1547338000 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses 194794908 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses 194719765 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses 194794908 # number of demand (read+write) accesses system.cpu.icache.demand_accesses 194719765 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses 194794908 # number of overall (read+write) accesses system.cpu.icache.overall_accesses 194719765 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate 0.001096 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate 0.001150 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate 0.001096 # miss rate for demand accesses system.cpu.icache.demand_miss_rate 0.001150 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate 0.001096 # miss rate for overall accesses system.cpu.icache.overall_miss_rate 0.001150 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency 6946.370703 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_miss_latency 6912.202487 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency 6946.370703 # average overall miss latency system.cpu.icache.demand_avg_miss_latency 6912.202487 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency 6946.370703 # average overall miss latency system.cpu.icache.overall_avg_miss_latency 6912.202487 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
@ -308,137 +308,137 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs no_value
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.writebacks 7 # number of writebacks system.cpu.icache.writebacks 6 # number of writebacks
system.cpu.icache.ReadReq_mshr_hits 2095 # number of ReadReq MSHR hits system.cpu.icache.ReadReq_mshr_hits 2117 # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits 2095 # number of demand (read+write) MSHR hits system.cpu.icache.demand_mshr_hits 2117 # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits 2095 # number of overall MSHR hits system.cpu.icache.overall_mshr_hits 2117 # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses 211445 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses 221739 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses 211445 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses 221739 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses 211445 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses 221739 # number of overall MSHR misses
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.icache.ReadReq_mshr_miss_latency 798407000 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_latency 830917000 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency 798407000 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_latency 830917000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency 798407000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency 830917000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.icache.ReadReq_mshr_miss_rate 0.001085 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate 0.001139 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate 0.001085 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate 0.001139 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate 0.001085 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate 0.001139 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency 3775.955922 # average ReadReq mshr miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency 3747.274949 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency 3775.955922 # average overall mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency 3747.274949 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 3775.955922 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency 3747.274949 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 2527816 # number of replacements system.cpu.dcache.replacements 2527207 # number of replacements
system.cpu.dcache.tagsinuse 4087.589623 # Cycle average of tags in use system.cpu.dcache.tagsinuse 4087.569371 # Cycle average of tags in use
system.cpu.dcache.total_refs 440722661 # Total number of references to valid blocks. system.cpu.dcache.total_refs 440821768 # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs 2531912 # Sample count of references to valid blocks. system.cpu.dcache.sampled_refs 2531303 # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs 174.067132 # Average number of references to valid blocks. system.cpu.dcache.avg_refs 174.148163 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 2123837000 # Cycle when the warmup percentage was hit. system.cpu.dcache.warmup_cycle 2135798000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::0 4087.589623 # Average occupied blocks per context system.cpu.dcache.occ_blocks::0 4087.569371 # Average occupied blocks per context
system.cpu.dcache.occ_percent::0 0.997947 # Average percentage of cache occupancy system.cpu.dcache.occ_percent::0 0.997942 # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits 291994352 # number of ReadReq hits system.cpu.dcache.ReadReq_hits 292074612 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits 147612028 # number of WriteReq hits system.cpu.dcache.WriteReq_hits 147577545 # number of WriteReq hits
system.cpu.dcache.demand_hits 439606380 # number of demand (read+write) hits system.cpu.dcache.demand_hits 439652157 # number of demand (read+write) hits
system.cpu.dcache.overall_hits 439606380 # number of overall hits system.cpu.dcache.overall_hits 439652157 # number of overall hits
system.cpu.dcache.ReadReq_misses 3097887 # number of ReadReq misses system.cpu.dcache.ReadReq_misses 3115587 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses 1548173 # number of WriteReq misses system.cpu.dcache.WriteReq_misses 1582656 # number of WriteReq misses
system.cpu.dcache.demand_misses 4646060 # number of demand (read+write) misses system.cpu.dcache.demand_misses 4698243 # number of demand (read+write) misses
system.cpu.dcache.overall_misses 4646060 # number of overall misses system.cpu.dcache.overall_misses 4698243 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency 51505231500 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_latency 51949082000 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency 36276487000 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_latency 37383634500 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency 87781718500 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_latency 89332716500 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency 87781718500 # number of overall miss cycles system.cpu.dcache.overall_miss_latency 89332716500 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses 295092239 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses 295190199 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses 149160201 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses 149160201 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.demand_accesses 444252440 # number of demand (read+write) accesses system.cpu.dcache.demand_accesses 444350400 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses 444252440 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses 444350400 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate 0.010498 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate 0.010555 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate 0.010379 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate 0.010610 # miss rate for WriteReq accesses
system.cpu.dcache.demand_miss_rate 0.010458 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate 0.010573 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate 0.010458 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate 0.010573 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency 16625.923250 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency 16673.930787 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency 23431.804456 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency 23620.821265 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency 18893.797863 # average overall miss latency system.cpu.dcache.demand_avg_miss_latency 19014.068983 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency 18893.797863 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency 19014.068983 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 20000 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 74500 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 1 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 4 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets 20000 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets 18625 # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.writebacks 2229445 # number of writebacks system.cpu.dcache.writebacks 2229206 # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits 1337511 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_hits 1355757 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits 584931 # number of WriteReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits 609338 # number of WriteReq MSHR hits
system.cpu.dcache.demand_mshr_hits 1922442 # number of demand (read+write) MSHR hits system.cpu.dcache.demand_mshr_hits 1965095 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits 1922442 # number of overall MSHR hits system.cpu.dcache.overall_mshr_hits 1965095 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses 1760376 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses 1759830 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses 963242 # number of WriteReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses 973318 # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses 2723618 # number of demand (read+write) MSHR misses system.cpu.dcache.demand_mshr_misses 2733148 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses 2723618 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses 2733148 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.dcache.ReadReq_mshr_miss_latency 14910828500 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_latency 14896925000 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency 16810626500 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency 17174770000 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency 31721455000 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_latency 32071695000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency 31721455000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency 32071695000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_miss_rate 0.005966 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate 0.005962 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate 0.006458 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate 0.006525 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate 0.006131 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate 0.006151 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate 0.006131 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate 0.006151 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 8470.252094 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency 8464.979572 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 17452.131967 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency 17645.589622 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 11646.807665 # average overall mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency 11734.342597 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 11646.807665 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency 11734.342597 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 574929 # number of replacements system.cpu.l2cache.replacements 574699 # number of replacements
system.cpu.l2cache.tagsinuse 21600.538558 # Cycle average of tags in use system.cpu.l2cache.tagsinuse 21595.701500 # Cycle average of tags in use
system.cpu.l2cache.total_refs 3193840 # Total number of references to valid blocks. system.cpu.l2cache.total_refs 3193363 # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs 594089 # Sample count of references to valid blocks. system.cpu.l2cache.sampled_refs 593876 # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs 5.376030 # Average number of references to valid blocks. system.cpu.l2cache.avg_refs 5.377154 # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 271573746000 # Cycle when the warmup percentage was hit. system.cpu.l2cache.warmup_cycle 271431195000 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.occ_blocks::0 7800.784816 # Average occupied blocks per context system.cpu.l2cache.occ_blocks::0 7794.557657 # Average occupied blocks per context
system.cpu.l2cache.occ_blocks::1 13799.753742 # Average occupied blocks per context system.cpu.l2cache.occ_blocks::1 13801.143843 # Average occupied blocks per context
system.cpu.l2cache.occ_percent::0 0.238061 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::0 0.237871 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::1 0.421135 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::1 0.421177 # Average percentage of cache occupancy
system.cpu.l2cache.ReadReq_hits 1433037 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits 1432788 # number of ReadReq hits
system.cpu.l2cache.Writeback_hits 2229452 # number of Writeback hits system.cpu.l2cache.Writeback_hits 2229212 # number of Writeback hits
system.cpu.l2cache.UpgradeReq_hits 1223 # number of UpgradeReq hits system.cpu.l2cache.UpgradeReq_hits 1238 # number of UpgradeReq hits
system.cpu.l2cache.ReadExReq_hits 524485 # number of ReadExReq hits system.cpu.l2cache.ReadExReq_hits 524381 # number of ReadExReq hits
system.cpu.l2cache.demand_hits 1957522 # number of demand (read+write) hits system.cpu.l2cache.demand_hits 1957169 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits 1957522 # number of overall hits system.cpu.l2cache.overall_hits 1957169 # number of overall hits
system.cpu.l2cache.ReadReq_misses 338639 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses 338369 # number of ReadReq misses
system.cpu.l2cache.UpgradeReq_misses 198705 # number of UpgradeReq misses system.cpu.l2cache.UpgradeReq_misses 208965 # number of UpgradeReq misses
system.cpu.l2cache.ReadExReq_misses 247104 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_misses 247135 # number of ReadExReq misses
system.cpu.l2cache.demand_misses 585743 # number of demand (read+write) misses system.cpu.l2cache.demand_misses 585504 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses 585743 # number of overall misses system.cpu.l2cache.overall_misses 585504 # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency 11565729500 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_latency 11556474000 # number of ReadReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency 9755500 # number of UpgradeReq miss cycles system.cpu.l2cache.UpgradeReq_miss_latency 9921000 # number of UpgradeReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency 8475498500 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency 8477435500 # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency 20041228000 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_latency 20033909500 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency 20041228000 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency 20033909500 # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses 1771676 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses 1771157 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses 2229452 # number of Writeback accesses(hits+misses) system.cpu.l2cache.Writeback_accesses 2229212 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses 199928 # number of UpgradeReq accesses(hits+misses) system.cpu.l2cache.UpgradeReq_accesses 210203 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses 771589 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses 771516 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses 2543265 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses 2542673 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses 2543265 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses 2542673 # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate 0.191140 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate 0.191044 # miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate 0.993883 # miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_miss_rate 0.994110 # miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_miss_rate 0.320253 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_miss_rate 0.320324 # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate 0.230311 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate 0.230271 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate 0.230311 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate 0.230271 # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency 34153.566187 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency 34153.465595 # average ReadReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency 49.095393 # average UpgradeReq miss latency system.cpu.l2cache.UpgradeReq_avg_miss_latency 47.476850 # average UpgradeReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency 34299.317292 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency 34302.852692 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency 34215.053360 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency 34216.520297 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency 34215.053360 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency 34216.520297 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
@ -447,31 +447,31 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.writebacks 411255 # number of writebacks system.cpu.l2cache.writebacks 411193 # number of writebacks
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
system.cpu.l2cache.ReadReq_mshr_misses 338639 # number of ReadReq MSHR misses system.cpu.l2cache.ReadReq_mshr_misses 338369 # number of ReadReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses 198705 # number of UpgradeReq MSHR misses system.cpu.l2cache.UpgradeReq_mshr_misses 208965 # number of UpgradeReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses 247104 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses 247135 # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses 585743 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses 585504 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses 585743 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses 585504 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.l2cache.ReadReq_mshr_miss_latency 10504876500 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_latency 10496162500 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency 6160011500 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_latency 6478082000 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency 7664207000 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency 7666148000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency 18169083500 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency 18162310500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency 18169083500 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency 18162310500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.191140 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate 0.191044 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate 0.993883 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate 0.994110 # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.320253 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.320324 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate 0.230311 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate 0.230271 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate 0.230311 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate 0.230271 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31020.870307 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31019.870319 # average ReadReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31000.787600 # average UpgradeReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31000.799177 # average UpgradeReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31016.118719 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31020.082141 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency 31018.865782 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency 31019.959727 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 31018.865782 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 31019.959727 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions

11
tests/long/70.twolf/ref/x86/linux/o3-timing/simout
View file

@ -3,12 +3,11 @@ Redirecting stderr to build/X86_SE/tests/opt/long/70.twolf/x86/linux/o3-timing/s
gem5 Simulator System. http://gem5.org gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details. gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Aug 20 2011 13:24:14 gem5 compiled Nov 16 2011 11:08:03
gem5 started Aug 20 2011 13:24:28 gem5 started Nov 17 2011 13:09:16
gem5 executing on zizzer gem5 executing on ribera.cs.wisc.edu
command line: build/X86_SE/gem5.opt -d build/X86_SE/tests/opt/long/70.twolf/x86/linux/o3-timing -re tests/run.py build/X86_SE/tests/opt/long/70.twolf/x86/linux/o3-timing command line: build/X86_SE/gem5.opt -d build/X86_SE/tests/opt/long/70.twolf/x86/linux/o3-timing -re tests/run.py build/X86_SE/tests/opt/long/70.twolf/x86/linux/o3-timing
Couldn't unlink build/X86_SE/tests/opt/long/70.twolf/x86/linux/o3-timing/smred.sav tests
Couldn't unlink build/X86_SE/tests/opt/long/70.twolf/x86/linux/o3-timing/smred.sv2
Global frequency set at 1000000000000 ticks per second Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation... info: Entering event queue @ 0. Starting simulation...
@ -26,4 +25,4 @@ info: Increasing stack size by one page.
76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90
91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105
106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120
122 123 124 Exiting @ tick 96610526000 because target called exit() 122 123 124 Exiting @ tick 96689893000 because target called exit()

708
tests/long/70.twolf/ref/x86/linux/o3-timing/stats.txt
View file

@ -1,251 +1,251 @@
---------- Begin Simulation Statistics ---------- ---------- Begin Simulation Statistics ----------
sim_seconds 0.096611 # Number of seconds simulated sim_seconds 0.096690 # Number of seconds simulated
sim_ticks 96610526000 # Number of ticks simulated sim_ticks 96689893000 # Number of ticks simulated
sim_freq 1000000000000 # Frequency of simulated ticks sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 102112 # Simulator instruction rate (inst/s) host_inst_rate 89575 # Simulator instruction rate (inst/s)
host_tick_rate 44565176 # Simulator tick rate (ticks/s) host_tick_rate 39125952 # Simulator tick rate (ticks/s)
host_mem_usage 220868 # Number of bytes of host memory used host_mem_usage 253168 # Number of bytes of host memory used
host_seconds 2167.85 # Real time elapsed on the host host_seconds 2471.25 # Real time elapsed on the host
sim_insts 221363017 # Number of instructions simulated sim_insts 221363017 # Number of instructions simulated
system.cpu.workload.num_syscalls 400 # Number of system calls system.cpu.workload.num_syscalls 400 # Number of system calls
system.cpu.numCycles 193221053 # number of cpu cycles simulated system.cpu.numCycles 193379787 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.BPredUnit.lookups 25817967 # Number of BP lookups system.cpu.BPredUnit.lookups 25818202 # Number of BP lookups
system.cpu.BPredUnit.condPredicted 25817967 # Number of conditional branches predicted system.cpu.BPredUnit.condPredicted 25818202 # Number of conditional branches predicted
system.cpu.BPredUnit.condIncorrect 2894858 # Number of conditional branches incorrect system.cpu.BPredUnit.condIncorrect 2898724 # Number of conditional branches incorrect
system.cpu.BPredUnit.BTBLookups 23614164 # Number of BTB lookups system.cpu.BPredUnit.BTBLookups 23602930 # Number of BTB lookups
system.cpu.BPredUnit.BTBHits 20981330 # Number of BTB hits system.cpu.BPredUnit.BTBHits 20841363 # Number of BTB hits
system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target. system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target.
system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions. system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions.
system.cpu.fetch.icacheStallCycles 30977399 # Number of cycles fetch is stalled on an Icache miss system.cpu.fetch.icacheStallCycles 30995459 # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts 261503264 # Number of instructions fetch has processed system.cpu.fetch.Insts 261573615 # Number of instructions fetch has processed
system.cpu.fetch.Branches 25817967 # Number of branches that fetch encountered system.cpu.fetch.Branches 25818202 # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches 20981330 # Number of branches that fetch has predicted taken system.cpu.fetch.predictedBranches 20841363 # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles 70791188 # Number of cycles fetch has run and was not squashing or blocked system.cpu.fetch.Cycles 70808397 # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles 26915794 # Number of cycles fetch has spent squashing system.cpu.fetch.SquashCycles 26924712 # Number of cycles fetch has spent squashing
system.cpu.fetch.BlockedCycles 67651206 # Number of cycles fetch has spent blocked system.cpu.fetch.BlockedCycles 67767699 # Number of cycles fetch has spent blocked
system.cpu.fetch.MiscStallCycles 160 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu.fetch.MiscStallCycles 120 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingTrapStallCycles 1398 # Number of stall cycles due to pending traps system.cpu.fetch.PendingTrapStallCycles 1017 # Number of stall cycles due to pending traps
system.cpu.fetch.CacheLines 28846864 # Number of cache lines fetched system.cpu.fetch.CacheLines 28859729 # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes 549492 # Number of outstanding Icache misses that were squashed system.cpu.fetch.IcacheSquashes 549788 # Number of outstanding Icache misses that were squashed
system.cpu.fetch.rateDist::samples 193133856 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::samples 193293197 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean 2.260391 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::mean 2.259018 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev 3.334586 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::stdev 3.335260 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0 124189193 64.30% 64.30% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::0 124336745 64.33% 64.33% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1 4110604 2.13% 66.43% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::1 4112034 2.13% 66.45% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2 3242349 1.68% 68.11% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::2 3238737 1.68% 68.13% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3 4337138 2.25% 70.35% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::3 4462671 2.31% 70.44% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::4 4293938 2.22% 72.58% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::4 4295145 2.22% 72.66% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::5 4598067 2.38% 74.96% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::5 4476640 2.32% 74.98% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::6 5546943 2.87% 77.83% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::6 5418723 2.80% 77.78% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::7 3021455 1.56% 79.40% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::7 3020771 1.56% 79.34% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::8 39794169 20.60% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::8 39931731 20.66% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total 193133856 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::total 193293197 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate 0.133619 # Number of branch fetches per cycle system.cpu.fetch.branchRate 0.133510 # Number of branch fetches per cycle
system.cpu.fetch.rate 1.353389 # Number of inst fetches per cycle system.cpu.fetch.rate 1.352642 # Number of inst fetches per cycle
system.cpu.decode.IdleCycles 44744191 # Number of cycles decode is idle system.cpu.decode.IdleCycles 44764810 # Number of cycles decode is idle
system.cpu.decode.BlockedCycles 57710964 # Number of cycles decode is blocked system.cpu.decode.BlockedCycles 57827624 # Number of cycles decode is blocked
system.cpu.decode.RunCycles 57165261 # Number of cycles decode is running system.cpu.decode.RunCycles 57161965 # Number of cycles decode is running
system.cpu.decode.UnblockCycles 9800935 # Number of cycles decode is unblocking system.cpu.decode.UnblockCycles 9818293 # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles 23712505 # Number of cycles decode is squashing system.cpu.decode.SquashCycles 23720505 # Number of cycles decode is squashing
system.cpu.decode.DecodedInsts 424257825 # Number of instructions handled by decode system.cpu.decode.DecodedInsts 424367292 # Number of instructions handled by decode
system.cpu.rename.SquashCycles 23712505 # Number of cycles rename is squashing system.cpu.rename.SquashCycles 23720505 # Number of cycles rename is squashing
system.cpu.rename.IdleCycles 53368695 # Number of cycles rename is idle system.cpu.rename.IdleCycles 53388300 # Number of cycles rename is idle
system.cpu.rename.BlockCycles 14594998 # Number of cycles rename is blocking system.cpu.rename.BlockCycles 14632169 # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles 21883 # count of cycles rename stalled for serializing inst system.cpu.rename.serializeStallCycles 21921 # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles 57606354 # Number of cycles rename is running system.cpu.rename.RunCycles 57615812 # Number of cycles rename is running
system.cpu.rename.UnblockCycles 43829421 # Number of cycles rename is unblocking system.cpu.rename.UnblockCycles 43914490 # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts 411666463 # Number of instructions processed by rename system.cpu.rename.RenamedInsts 411765049 # Number of instructions processed by rename
system.cpu.rename.ROBFullEvents 15 # Number of times rename has blocked due to ROB full system.cpu.rename.ROBFullEvents 18 # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents 18981117 # Number of times rename has blocked due to IQ full system.cpu.rename.IQFullEvents 19034939 # Number of times rename has blocked due to IQ full
system.cpu.rename.LSQFullEvents 22454802 # Number of times rename has blocked due to LSQ full system.cpu.rename.LSQFullEvents 22478875 # Number of times rename has blocked due to LSQ full
system.cpu.rename.RenamedOperands 438110122 # Number of destination operands rename has renamed system.cpu.rename.RenamedOperands 438156432 # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups 1066455351 # Number of register rename lookups that rename has made system.cpu.rename.RenameLookups 1066580371 # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups 1055559190 # Number of integer rename lookups system.cpu.rename.int_rename_lookups 1055689317 # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups 10896161 # Number of floating rename lookups system.cpu.rename.fp_rename_lookups 10891054 # Number of floating rename lookups
system.cpu.rename.CommittedMaps 234363409 # Number of HB maps that are committed system.cpu.rename.CommittedMaps 234363409 # Number of HB maps that are committed
system.cpu.rename.UndoneMaps 203746713 # Number of HB maps that are undone due to squashing system.cpu.rename.UndoneMaps 203793023 # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts 1780 # count of serializing insts renamed system.cpu.rename.serializingInsts 1794 # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts 1774 # count of temporary serializing insts renamed system.cpu.rename.tempSerializingInsts 1788 # count of temporary serializing insts renamed
system.cpu.rename.skidInsts 94916865 # count of insts added to the skid buffer system.cpu.rename.skidInsts 94980657 # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads 104240418 # Number of loads inserted to the mem dependence unit. system.cpu.memDep0.insertedLoads 104262380 # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores 37277466 # Number of stores inserted to the mem dependence unit. system.cpu.memDep0.insertedStores 37289638 # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads 67123936 # Number of conflicting loads. system.cpu.memDep0.conflictingLoads 67232013 # Number of conflicting loads.
system.cpu.memDep0.conflictingStores 21592423 # Number of conflicting stores. system.cpu.memDep0.conflictingStores 21668119 # Number of conflicting stores.
system.cpu.iq.iqInstsAdded 396698453 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqInstsAdded 396788007 # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded 1768 # Number of non-speculative instructions added to the IQ system.cpu.iq.iqNonSpecInstsAdded 2705 # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued 287681057 # Number of instructions issued system.cpu.iq.iqInstsIssued 287703359 # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued 248197 # Number of squashed instructions issued system.cpu.iq.iqSquashedInstsIssued 254770 # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined 174766428 # Number of squashed instructions iterated over during squash; mainly for profiling system.cpu.iq.iqSquashedInstsExamined 174855842 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined 350779105 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedOperandsExamined 350938331 # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved 522 # Number of squashed non-spec instructions that were removed system.cpu.iq.iqSquashedNonSpecRemoved 1459 # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples 193133856 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::samples 193293197 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean 1.489542 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::mean 1.488430 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev 1.479240 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::stdev 1.480803 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0 60593209 31.37% 31.37% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::0 60724695 31.42% 31.42% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1 53908728 27.91% 59.29% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::1 54019027 27.95% 59.36% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2 35738338 18.50% 77.79% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::2 35712551 18.48% 77.84% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3 21062429 10.91% 88.70% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::3 21012235 10.87% 88.71% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4 13747169 7.12% 95.81% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::4 13686479 7.08% 95.79% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5 5239198 2.71% 98.53% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::5 5222239 2.70% 98.49% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6 2106456 1.09% 99.62% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::6 2184583 1.13% 99.62% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7 621668 0.32% 99.94% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 593188 0.31% 99.93% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8 116661 0.06% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 138200 0.07% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total 193133856 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::total 193293197 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu 106266 3.87% 3.87% # attempts to use FU when none available system.cpu.iq.fu_full::IntAlu 110269 4.01% 4.01% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult 0 0.00% 3.87% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 0 0.00% 4.01% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv 0 0.00% 3.87% # attempts to use FU when none available system.cpu.iq.fu_full::IntDiv 0 0.00% 4.01% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.87% # attempts to use FU when none available system.cpu.iq.fu_full::FloatAdd 0 0.00% 4.01% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.87% # attempts to use FU when none available system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.01% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.87% # attempts to use FU when none available system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.01% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult 0 0.00% 3.87% # attempts to use FU when none available system.cpu.iq.fu_full::FloatMult 0 0.00% 4.01% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv 0 0.00% 3.87% # attempts to use FU when none available system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.01% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.87% # attempts to use FU when none available system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.01% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.87% # attempts to use FU when none available system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.01% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.87% # attempts to use FU when none available system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.01% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu 0 0.00% 3.87% # attempts to use FU when none available system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.01% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp 0 0.00% 3.87% # attempts to use FU when none available system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.01% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt 0 0.00% 3.87% # attempts to use FU when none available system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.01% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc 0 0.00% 3.87% # attempts to use FU when none available system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.01% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult 0 0.00% 3.87% # attempts to use FU when none available system.cpu.iq.fu_full::SimdMult 0 0.00% 4.01% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.87% # attempts to use FU when none available system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.01% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift 0 0.00% 3.87% # attempts to use FU when none available system.cpu.iq.fu_full::SimdShift 0 0.00% 4.01% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.87% # attempts to use FU when none available system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.01% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.87% # attempts to use FU when none available system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.01% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.87% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.01% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.87% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.01% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.87% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.01% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.87% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.01% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.87% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.01% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.87% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.01% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.87% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.01% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.87% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.01% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.87% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.01% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead 2319161 84.53% 88.40% # attempts to use FU when none available system.cpu.iq.fu_full::MemRead 2317531 84.31% 88.32% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite 318223 11.60% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::MemWrite 321034 11.68% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 1204809 0.42% 0.42% # Type of FU issued system.cpu.iq.FU_type_0::No_OpClass 1208234 0.42% 0.42% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu 187032245 65.01% 65.43% # Type of FU issued system.cpu.iq.FU_type_0::IntAlu 187072997 65.02% 65.44% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult 0 0.00% 65.43% # Type of FU issued system.cpu.iq.FU_type_0::IntMult 0 0.00% 65.44% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 65.43% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 65.44% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd 1651608 0.57% 66.01% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 1650386 0.57% 66.02% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.01% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.02% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.01% # Type of FU issued system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.02% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult 0 0.00% 66.01% # Type of FU issued system.cpu.iq.FU_type_0::FloatMult 0 0.00% 66.02% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 66.01% # Type of FU issued system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 66.02% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.01% # Type of FU issued system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.02% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 66.01% # Type of FU issued system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 66.02% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 66.01% # Type of FU issued system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 66.02% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 66.01% # Type of FU issued system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 66.02% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 66.01% # Type of FU issued system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 66.02% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 66.01% # Type of FU issued system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 66.02% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 66.01% # Type of FU issued system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 66.02% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult 0 0.00% 66.01% # Type of FU issued system.cpu.iq.FU_type_0::SimdMult 0 0.00% 66.02% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 66.01% # Type of FU issued system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 66.02% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift 0 0.00% 66.01% # Type of FU issued system.cpu.iq.FU_type_0::SimdShift 0 0.00% 66.02% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.01% # Type of FU issued system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.02% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 66.01% # Type of FU issued system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 66.02% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.01% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.02% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.01% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.02% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.01% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.02% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.01% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.02% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.01% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.02% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.01% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.02% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.01% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.02% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.01% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.02% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.01% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.02% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead 73242981 25.46% 91.47% # Type of FU issued system.cpu.iq.FU_type_0::MemRead 73223880 25.45% 91.47% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite 24549414 8.53% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::MemWrite 24547862 8.53% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::total 287681057 # Type of FU issued system.cpu.iq.FU_type_0::total 287703359 # Type of FU issued
system.cpu.iq.rate 1.488870 # Inst issue rate system.cpu.iq.rate 1.487763 # Inst issue rate
system.cpu.iq.fu_busy_cnt 2743650 # FU busy when requested system.cpu.iq.fu_busy_cnt 2748834 # FU busy when requested
system.cpu.iq.fu_busy_rate 0.009537 # FU busy rate (busy events/executed inst) system.cpu.iq.fu_busy_rate 0.009554 # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads 765972748 # Number of integer instruction queue reads system.cpu.iq.int_inst_queue_reads 766190945 # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes 566387994 # Number of integer instruction queue writes system.cpu.iq.int_inst_queue_writes 566572341 # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses 278383951 # Number of integer instruction queue wakeup accesses system.cpu.iq.int_inst_queue_wakeup_accesses 278374724 # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads 5515069 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_reads 5512574 # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes 5414925 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_writes 5407408 # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses 2649060 # Number of floating instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_wakeup_accesses 2648186 # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses 286446350 # Number of integer alu accesses system.cpu.iq.int_alu_accesses 286471551 # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses 2773548 # Number of floating point alu accesses system.cpu.iq.fp_alu_accesses 2772408 # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads 18375293 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.forwLoads 18351013 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread0.squashedLoads 47590828 # Number of loads squashed system.cpu.iew.lsq.thread0.squashedLoads 47612790 # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses 32389 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread0.ignoredResponses 32223 # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation 343467 # Number of memory ordering violations system.cpu.iew.lsq.thread0.memOrderViolation 339608 # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores 16761750 # Number of stores squashed system.cpu.iew.lsq.thread0.squashedStores 16773922 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads 46017 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.rescheduledLoads 46155 # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
system.cpu.iew.iewSquashCycles 23712505 # Number of cycles IEW is squashing system.cpu.iew.iewSquashCycles 23720505 # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles 356267 # Number of cycles IEW is blocking system.cpu.iew.iewBlockCycles 359624 # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles 212332 # Number of cycles IEW is unblocking system.cpu.iew.iewUnblockCycles 213865 # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts 396700221 # Number of instructions dispatched to IQ system.cpu.iew.iewDispatchedInsts 396790712 # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts 134682 # Number of squashed instructions skipped by dispatch system.cpu.iew.iewDispSquashedInsts 135718 # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts 104240418 # Number of dispatched load instructions system.cpu.iew.iewDispLoadInsts 104262380 # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts 37277466 # Number of dispatched store instructions system.cpu.iew.iewDispStoreInsts 37289638 # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts 1768 # Number of dispatched non-speculative instructions system.cpu.iew.iewDispNonSpecInsts 1786 # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents 118966 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewIQFullEvents 119790 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents 14039 # Number of times the LSQ has become full, causing a stall system.cpu.iew.iewLSQFullEvents 15845 # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents 343467 # Number of memory order violations system.cpu.iew.memOrderViolationEvents 339608 # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect 2505670 # Number of branches that were predicted taken incorrectly system.cpu.iew.predictedTakenIncorrect 2505263 # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect 594786 # Number of branches that were predicted not taken incorrectly system.cpu.iew.predictedNotTakenIncorrect 598160 # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts 3100456 # Number of branch mispredicts detected at execute system.cpu.iew.branchMispredicts 3103423 # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts 283858854 # Number of executed instructions system.cpu.iew.iewExecutedInsts 283855997 # Number of executed instructions
system.cpu.iew.iewExecLoadInsts 71711617 # Number of load instructions executed system.cpu.iew.iewExecLoadInsts 71689961 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 3822203 # Number of squashed instructions skipped in execute system.cpu.iew.iewExecSquashedInsts 3847362 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_swp 0 # number of swp insts executed
system.cpu.iew.exec_nop 0 # number of nop insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed
system.cpu.iew.exec_refs 95762495 # number of memory reference insts executed system.cpu.iew.exec_refs 95739480 # number of memory reference insts executed
system.cpu.iew.exec_branches 15668383 # Number of branches executed system.cpu.iew.exec_branches 15662592 # Number of branches executed
system.cpu.iew.exec_stores 24050878 # Number of stores executed system.cpu.iew.exec_stores 24049519 # Number of stores executed
system.cpu.iew.exec_rate 1.469089 # Inst execution rate system.cpu.iew.exec_rate 1.467868 # Inst execution rate
system.cpu.iew.wb_sent 282330192 # cumulative count of insts sent to commit system.cpu.iew.wb_sent 282319460 # cumulative count of insts sent to commit
system.cpu.iew.wb_count 281033011 # cumulative count of insts written-back system.cpu.iew.wb_count 281022910 # cumulative count of insts written-back
system.cpu.iew.wb_producers 227942764 # num instructions producing a value system.cpu.iew.wb_producers 227917239 # num instructions producing a value
system.cpu.iew.wb_consumers 378918606 # num instructions consuming a value system.cpu.iew.wb_consumers 378870882 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu.iew.wb_rate 1.454464 # insts written-back per cycle system.cpu.iew.wb_rate 1.453218 # insts written-back per cycle
system.cpu.iew.wb_fanout 0.601561 # average fanout of values written-back system.cpu.iew.wb_fanout 0.601570 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.commit.commitCommittedInsts 221363017 # The number of committed instructions system.cpu.commit.commitCommittedInsts 221363017 # The number of committed instructions
system.cpu.commit.commitSquashedInsts 175344362 # The number of squashed insts skipped by commit system.cpu.commit.commitSquashedInsts 175435625 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 1246 # The number of times commit has been forced to stall to communicate backwards system.cpu.commit.commitNonSpecStalls 1246 # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts 2895014 # The number of times a branch was mispredicted system.cpu.commit.branchMispredicts 2898838 # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples 169421351 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::samples 169572692 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean 1.306583 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::mean 1.305417 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev 1.742468 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::stdev 1.741291 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0 63568929 37.52% 37.52% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::0 63662174 37.54% 37.54% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1 62259787 36.75% 74.27% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::1 62350604 36.77% 74.31% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2 15643694 9.23% 83.50% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::2 15592003 9.19% 83.51% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3 11988406 7.08% 90.58% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::3 11999288 7.08% 90.58% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4 5417709 3.20% 93.78% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::4 5440588 3.21% 93.79% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5 2980917 1.76% 95.54% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::5 2982193 1.76% 95.55% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6 2013932 1.19% 96.73% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::6 2011991 1.19% 96.74% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7 1192205 0.70% 97.43% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::7 1185528 0.70% 97.44% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8 4355772 2.57% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::8 4348323 2.56% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total 169421351 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::total 169572692 # Number of insts commited each cycle
system.cpu.commit.count 221363017 # Number of instructions committed system.cpu.commit.count 221363017 # Number of instructions committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.refs 77165306 # Number of memory references committed system.cpu.commit.refs 77165306 # Number of memory references committed
@ -255,50 +255,50 @@ system.cpu.commit.branches 12326943 # Nu
system.cpu.commit.fp_insts 2162459 # Number of committed floating point instructions. system.cpu.commit.fp_insts 2162459 # Number of committed floating point instructions.
system.cpu.commit.int_insts 220339606 # Number of committed integer instructions. system.cpu.commit.int_insts 220339606 # Number of committed integer instructions.
system.cpu.commit.function_calls 0 # Number of function calls committed. system.cpu.commit.function_calls 0 # Number of function calls committed.
system.cpu.commit.bw_lim_events 4355772 # number cycles where commit BW limit reached system.cpu.commit.bw_lim_events 4348323 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
system.cpu.rob.rob_reads 561772958 # The number of ROB reads system.cpu.rob.rob_reads 562023011 # The number of ROB reads
system.cpu.rob.rob_writes 817171098 # The number of ROB writes system.cpu.rob.rob_writes 817360743 # The number of ROB writes
system.cpu.timesIdled 1889 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.timesIdled 1880 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 87197 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.idleCycles 86590 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts 221363017 # Number of Instructions Simulated system.cpu.committedInsts 221363017 # Number of Instructions Simulated
system.cpu.committedInsts_total 221363017 # Number of Instructions Simulated system.cpu.committedInsts_total 221363017 # Number of Instructions Simulated
system.cpu.cpi 0.872870 # CPI: Cycles Per Instruction system.cpu.cpi 0.873587 # CPI: Cycles Per Instruction
system.cpu.cpi_total 0.872870 # CPI: Total CPI of All Threads system.cpu.cpi_total 0.873587 # CPI: Total CPI of All Threads
system.cpu.ipc 1.145646 # IPC: Instructions Per Cycle system.cpu.ipc 1.144706 # IPC: Instructions Per Cycle
system.cpu.ipc_total 1.145646 # IPC: Total IPC of All Threads system.cpu.ipc_total 1.144706 # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads 530742767 # number of integer regfile reads system.cpu.int_regfile_reads 530675330 # number of integer regfile reads
system.cpu.int_regfile_writes 288972647 # number of integer regfile writes system.cpu.int_regfile_writes 288962100 # number of integer regfile writes
system.cpu.fp_regfile_reads 3616458 # number of floating regfile reads system.cpu.fp_regfile_reads 3614411 # number of floating regfile reads
system.cpu.fp_regfile_writes 2303580 # number of floating regfile writes system.cpu.fp_regfile_writes 2302807 # number of floating regfile writes
system.cpu.misc_regfile_reads 149927786 # number of misc regfile reads system.cpu.misc_regfile_reads 149913222 # number of misc regfile reads
system.cpu.misc_regfile_writes 844 # number of misc regfile writes system.cpu.misc_regfile_writes 844 # number of misc regfile writes
system.cpu.icache.replacements 4235 # number of replacements system.cpu.icache.replacements 4227 # number of replacements
system.cpu.icache.tagsinuse 1597.100373 # Cycle average of tags in use system.cpu.icache.tagsinuse 1595.324923 # Cycle average of tags in use
system.cpu.icache.total_refs 28839309 # Total number of references to valid blocks. system.cpu.icache.total_refs 28852140 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 6200 # Sample count of references to valid blocks. system.cpu.icache.sampled_refs 6194 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 4651.501452 # Average number of references to valid blocks. system.cpu.icache.avg_refs 4658.078786 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.occ_blocks::0 1597.100373 # Average occupied blocks per context system.cpu.icache.occ_blocks::0 1595.324923 # Average occupied blocks per context
system.cpu.icache.occ_percent::0 0.779834 # Average percentage of cache occupancy system.cpu.icache.occ_percent::0 0.778967 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits 28839309 # number of ReadReq hits system.cpu.icache.ReadReq_hits 28852140 # number of ReadReq hits
system.cpu.icache.demand_hits 28839309 # number of demand (read+write) hits system.cpu.icache.demand_hits 28852140 # number of demand (read+write) hits
system.cpu.icache.overall_hits 28839309 # number of overall hits system.cpu.icache.overall_hits 28852140 # number of overall hits
system.cpu.icache.ReadReq_misses 7555 # number of ReadReq misses system.cpu.icache.ReadReq_misses 7589 # number of ReadReq misses
system.cpu.icache.demand_misses 7555 # number of demand (read+write) misses system.cpu.icache.demand_misses 7589 # number of demand (read+write) misses
system.cpu.icache.overall_misses 7555 # number of overall misses system.cpu.icache.overall_misses 7589 # number of overall misses
system.cpu.icache.ReadReq_miss_latency 173857500 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_latency 174464500 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency 173857500 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_latency 174464500 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency 173857500 # number of overall miss cycles system.cpu.icache.overall_miss_latency 174464500 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses 28846864 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses 28859729 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses 28846864 # number of demand (read+write) accesses system.cpu.icache.demand_accesses 28859729 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses 28846864 # number of overall (read+write) accesses system.cpu.icache.overall_accesses 28859729 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate 0.000262 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate 0.000263 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate 0.000262 # miss rate for demand accesses system.cpu.icache.demand_miss_rate 0.000263 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate 0.000262 # miss rate for overall accesses system.cpu.icache.overall_miss_rate 0.000263 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency 23012.243547 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_miss_latency 22989.129003 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency 23012.243547 # average overall miss latency system.cpu.icache.demand_avg_miss_latency 22989.129003 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency 23012.243547 # average overall miss latency system.cpu.icache.overall_avg_miss_latency 22989.129003 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
@ -308,59 +308,59 @@ system.cpu.icache.avg_blocked_cycles::no_targets no_value
system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.writebacks 0 # number of writebacks system.cpu.icache.writebacks 0 # number of writebacks
system.cpu.icache.ReadReq_mshr_hits 1113 # number of ReadReq MSHR hits system.cpu.icache.ReadReq_mshr_hits 1125 # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits 1113 # number of demand (read+write) MSHR hits system.cpu.icache.demand_mshr_hits 1125 # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits 1113 # number of overall MSHR hits system.cpu.icache.overall_mshr_hits 1125 # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses 6442 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses 6464 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses 6442 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses 6464 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses 6442 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses 6464 # number of overall MSHR misses
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.icache.ReadReq_mshr_miss_latency 125492000 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_latency 125677000 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency 125492000 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_latency 125677000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency 125492000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency 125677000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.icache.ReadReq_mshr_miss_rate 0.000223 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate 0.000224 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate 0.000223 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate 0.000224 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate 0.000223 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate 0.000224 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency 19480.285626 # average ReadReq mshr miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency 19442.605198 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency 19480.285626 # average overall mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency 19442.605198 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency 19480.285626 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency 19442.605198 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 59 # number of replacements system.cpu.dcache.replacements 59 # number of replacements
system.cpu.dcache.tagsinuse 1420.172872 # Cycle average of tags in use system.cpu.dcache.tagsinuse 1416.877097 # Cycle average of tags in use
system.cpu.dcache.total_refs 73596568 # Total number of references to valid blocks. system.cpu.dcache.total_refs 73598603 # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs 1986 # Sample count of references to valid blocks. system.cpu.dcache.sampled_refs 1986 # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs 37057.687815 # Average number of references to valid blocks. system.cpu.dcache.avg_refs 37058.712487 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::0 1420.172872 # Average occupied blocks per context system.cpu.dcache.occ_blocks::0 1416.877097 # Average occupied blocks per context
system.cpu.dcache.occ_percent::0 0.346722 # Average percentage of cache occupancy system.cpu.dcache.occ_percent::0 0.345917 # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits 53088625 # number of ReadReq hits system.cpu.dcache.ReadReq_hits 53090649 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits 20507488 # number of WriteReq hits system.cpu.dcache.WriteReq_hits 20507453 # number of WriteReq hits
system.cpu.dcache.demand_hits 73596113 # number of demand (read+write) hits system.cpu.dcache.demand_hits 73598102 # number of demand (read+write) hits
system.cpu.dcache.overall_hits 73596113 # number of overall hits system.cpu.dcache.overall_hits 73598102 # number of overall hits
system.cpu.dcache.ReadReq_misses 844 # number of ReadReq misses system.cpu.dcache.ReadReq_misses 848 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses 8242 # number of WriteReq misses system.cpu.dcache.WriteReq_misses 8277 # number of WriteReq misses
system.cpu.dcache.demand_misses 9086 # number of demand (read+write) misses system.cpu.dcache.demand_misses 9125 # number of demand (read+write) misses
system.cpu.dcache.overall_misses 9086 # number of overall misses system.cpu.dcache.overall_misses 9125 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency 26292500 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_latency 26447500 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency 227102000 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_latency 228348000 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency 253394500 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_latency 254795500 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency 253394500 # number of overall miss cycles system.cpu.dcache.overall_miss_latency 254795500 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses 53089469 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses 53091497 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses 20515730 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses 20515730 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.demand_accesses 73605199 # number of demand (read+write) accesses system.cpu.dcache.demand_accesses 73607227 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses 73605199 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses 73607227 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate 0.000016 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate 0.000016 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate 0.000402 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate 0.000403 # miss rate for WriteReq accesses
system.cpu.dcache.demand_miss_rate 0.000123 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate 0.000124 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate 0.000123 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate 0.000124 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency 31152.251185 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency 31188.089623 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency 27554.234409 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency 27588.256615 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency 27888.454766 # average overall miss latency system.cpu.dcache.demand_avg_miss_latency 27922.794521 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency 27888.454766 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency 27922.794521 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
@ -370,71 +370,71 @@ system.cpu.dcache.avg_blocked_cycles::no_targets no_value
system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.writebacks 14 # number of writebacks system.cpu.dcache.writebacks 14 # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits 420 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_hits 424 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits 6436 # number of WriteReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits 6443 # number of WriteReq MSHR hits
system.cpu.dcache.demand_mshr_hits 6856 # number of demand (read+write) MSHR hits system.cpu.dcache.demand_mshr_hits 6867 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits 6856 # number of overall MSHR hits system.cpu.dcache.overall_mshr_hits 6867 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses 424 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses 424 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses 1806 # number of WriteReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses 1834 # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses 2230 # number of demand (read+write) MSHR misses system.cpu.dcache.demand_mshr_misses 2258 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses 2230 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses 2258 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.dcache.ReadReq_mshr_miss_latency 14047000 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_latency 13981500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency 63209500 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency 64146500 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency 77256500 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_latency 78128000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency 77256500 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency 78128000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_miss_rate 0.000008 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate 0.000008 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate 0.000088 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate 0.000089 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate 0.000030 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate 0.000031 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate 0.000030 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate 0.000031 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 33129.716981 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency 32975.235849 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 34999.723145 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency 34976.281352 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency 34644.170404 # average overall mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency 34600.531444 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency 34644.170404 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency 34600.531444 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 0 # number of replacements system.cpu.l2cache.replacements 0 # number of replacements
system.cpu.l2cache.tagsinuse 2499.008056 # Cycle average of tags in use system.cpu.l2cache.tagsinuse 2499.166941 # Cycle average of tags in use
system.cpu.l2cache.total_refs 2867 # Total number of references to valid blocks. system.cpu.l2cache.total_refs 2858 # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs 3761 # Sample count of references to valid blocks. system.cpu.l2cache.sampled_refs 3763 # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs 0.762297 # Average number of references to valid blocks. system.cpu.l2cache.avg_refs 0.759500 # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.occ_blocks::0 2497.026903 # Average occupied blocks per context system.cpu.l2cache.occ_blocks::0 2497.181729 # Average occupied blocks per context
system.cpu.l2cache.occ_blocks::1 1.981153 # Average occupied blocks per context system.cpu.l2cache.occ_blocks::1 1.985212 # Average occupied blocks per context
system.cpu.l2cache.occ_percent::0 0.076203 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::0 0.076208 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::1 0.000060 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::1 0.000061 # Average percentage of cache occupancy
system.cpu.l2cache.ReadReq_hits 2866 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits 2857 # number of ReadReq hits
system.cpu.l2cache.Writeback_hits 14 # number of Writeback hits system.cpu.l2cache.Writeback_hits 14 # number of Writeback hits
system.cpu.l2cache.ReadExReq_hits 8 # number of ReadExReq hits system.cpu.l2cache.ReadExReq_hits 8 # number of ReadExReq hits
system.cpu.l2cache.demand_hits 2874 # number of demand (read+write) hits system.cpu.l2cache.demand_hits 2865 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits 2874 # number of overall hits system.cpu.l2cache.overall_hits 2865 # number of overall hits
system.cpu.l2cache.ReadReq_misses 3757 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses 3759 # number of ReadReq misses
system.cpu.l2cache.UpgradeReq_misses 242 # number of UpgradeReq misses system.cpu.l2cache.UpgradeReq_misses 270 # number of UpgradeReq misses
system.cpu.l2cache.ReadExReq_misses 1557 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_misses 1557 # number of ReadExReq misses
system.cpu.l2cache.demand_misses 5314 # number of demand (read+write) misses system.cpu.l2cache.demand_misses 5316 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses 5314 # number of overall misses system.cpu.l2cache.overall_misses 5316 # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency 128666000 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_latency 128731000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency 53239000 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency 53240500 # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency 181905000 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_latency 181971500 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency 181905000 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency 181971500 # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses 6623 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses 6616 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses 14 # number of Writeback accesses(hits+misses) system.cpu.l2cache.Writeback_accesses 14 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses 242 # number of UpgradeReq accesses(hits+misses) system.cpu.l2cache.UpgradeReq_accesses 270 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses 1565 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses 1565 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses 8188 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses 8181 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses 8188 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses 8181 # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate 0.567266 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate 0.568168 # miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_miss_rate 0.994888 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_miss_rate 0.994888 # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate 0.648999 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate 0.649798 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate 0.648999 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate 0.649798 # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency 34247.005590 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency 34246.076084 # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency 34193.320488 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency 34194.283879 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency 34231.275875 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency 34230.906697 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency 34231.275875 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency 34230.906697 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
@ -446,28 +446,28 @@ system.cpu.l2cache.cache_copies 0 # nu
system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.l2cache.writebacks 0 # number of writebacks
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
system.cpu.l2cache.ReadReq_mshr_misses 3757 # number of ReadReq MSHR misses system.cpu.l2cache.ReadReq_mshr_misses 3759 # number of ReadReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses 242 # number of UpgradeReq MSHR misses system.cpu.l2cache.UpgradeReq_mshr_misses 270 # number of UpgradeReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses 1557 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses 1557 # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses 5314 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses 5316 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses 5314 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses 5316 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
system.cpu.l2cache.ReadReq_mshr_miss_latency 116539500 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_latency 116600500 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency 7502000 # number of UpgradeReq MSHR miss cycles system.cpu.l2cache.UpgradeReq_mshr_miss_latency 8370000 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency 48375000 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency 48374500 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency 164914500 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency 164975000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency 164914500 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency 164975000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.567266 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate 0.568168 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.994888 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.994888 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate 0.648999 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate 0.649798 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate 0.648999 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate 0.649798 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31019.297312 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31019.021016 # average ReadReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31000 # average UpgradeReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31000 # average UpgradeReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31069.364162 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31069.043031 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency 31033.966880 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency 31033.671934 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency 31033.966880 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency 31033.671934 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions