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Merge python and x86 changes with cache branch

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--HG--
extra : convert_revision : e06a950964286604274fba81dcca362d75847233
This commit is contained in:
Nathan Binkert 2007-07-26 23:15:49 -07:00
commit f0fef8f850
171 changed files with 3542 additions and 7047 deletions
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15
SConstruct
View file

@ -435,6 +435,15 @@ all_isa_list.sort()
all_cpu_list.sort()
default_cpus.sort()
def ExtraPathValidator(key, val, env):
if not val:
return
paths = val.split(':')
for path in paths:
path = os.path.expanduser(path)
if not isdir(path):
raise AttributeError, "Invalid path: '%s'" % path
sticky_opts.AddOptions(
EnumOption('TARGET_ISA', 'Target ISA', 'alpha', all_isa_list),
BoolOption('FULL_SYSTEM', 'Full-system support', False),
@ -461,7 +470,9 @@ sticky_opts.AddOptions(
('BATCH_CMD', 'Batch pool submission command name', 'qdo'),
('PYTHONHOME',
'Override the default PYTHONHOME for this system (use with caution)',
'%s:%s' % (sys.prefix, sys.exec_prefix))
'%s:%s' % (sys.prefix, sys.exec_prefix)),
('EXTRAS', 'Add Extra directories to the compilation', '',
ExtraPathValidator)
)
nonsticky_opts.AddOptions(
@ -613,6 +624,8 @@ base_env = env
for build_path in build_paths:
print "Building in", build_path
env['BUILDDIR'] = build_path
# build_dir is the tail component of build path, and is used to
# determine the build parameters (e.g., 'ALPHA_SE')
(build_root, build_dir) = os.path.split(build_path)

326
src/SConscript
View file

@ -26,14 +26,17 @@
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#
# Authors: Steve Reinhardt
# Authors: Nathan Binkert
import imp
import os
import sys
import zipfile
from os.path import basename
from os.path import join as joinpath
from os.path import exists
from os.path import isdir
from os.path import isfile
import SCons
@ -45,47 +48,87 @@ Import('*')
# Children need to see the environment
Export('env')
########################################################################
# Code for adding source files
#
sources = []
def Source(source):
if isinstance(source, SCons.Node.FS.File):
sources.append(source)
def sort_list(_list):
"""return a sorted copy of '_list'"""
if isinstance(_list, list):
_list = _list[:]
else:
sources.append(File(source))
_list = list(_list)
_list.sort()
return _list
class PySourceFile(object):
def __init__(self, package, source):
filename = str(source)
pyname = basename(filename)
assert pyname.endswith('.py')
name = pyname[:-3]
path = package.split('.')
modpath = path
if name != '__init__':
modpath += [name]
modpath = '.'.join(modpath)
arcpath = package.split('.') + [ pyname + 'c' ]
arcname = joinpath(*arcpath)
self.source = source
self.pyname = pyname
self.srcpath = source.srcnode().abspath
self.package = package
self.modpath = modpath
self.arcname = arcname
self.filename = filename
self.compiled = File(filename + 'c')
########################################################################
# Code for adding source files of various types
#
cc_sources = []
def Source(source):
'''Add a C/C++ source file to the build'''
if not isinstance(source, SCons.Node.FS.File):
source = File(source)
cc_sources.append(source)
py_sources = []
def PySource(package, source):
'''Add a python source file to the named package'''
if not isinstance(source, SCons.Node.FS.File):
source = File(source)
source = PySourceFile(package, source)
py_sources.append(source)
sim_objects_fixed = False
sim_object_modfiles = set()
def SimObject(source):
'''Add a SimObject python file as a python source object and add
it to a list of sim object modules'''
if sim_objects_fixed:
raise AttributeError, "Too late to call SimObject now."
if not isinstance(source, SCons.Node.FS.File):
source = File(source)
PySource('m5.objects', source)
modfile = basename(str(source))
assert modfile.endswith('.py')
modname = modfile[:-3]
sim_object_modfiles.add(modname)
swig_sources = []
def SwigSource(package, source):
'''Add a swig file to build'''
if not isinstance(source, SCons.Node.FS.File):
source = File(source)
val = source,package
swig_sources.append(val)
# Children should have access
Export('Source')
########################################################################
# Code for adding python objects
#
py_sources = []
py_source_packages = {}
def PySource(package, source):
if not isinstance(source, SCons.Node.FS.File):
source = File(source)
py_source_packages[source] = package
py_sources.append(source)
sim_objects = []
def SimObject(source):
if not isinstance(source, SCons.Node.FS.File):
source = File(source)
PySource('m5.objects', source)
modname = basename(str(source))
sim_objects.append(modname)
swig_sources = []
swig_source_packages = {}
def SwigSource(package, source):
if not isinstance(source, SCons.Node.FS.File):
source = File(source)
swig_source_packages[source] = package
swig_sources.append(source)
# Children should have access
Export('PySource')
Export('SimObject')
Export('SwigSource')
@ -105,9 +148,9 @@ env.Append(CPPPATH=Dir('.'))
env.Append(CPPDEFINES=[('THE_ISA','%s_ISA' % env['TARGET_ISA'].upper())])
########################################################################
#
# Walk the tree and execute all SConscripts
#
scripts = []
srcdir = env['SRCDIR']
for root, dirs, files in os.walk(srcdir, topdown=True):
if root == srcdir:
@ -120,64 +163,132 @@ for root, dirs, files in os.walk(srcdir, topdown=True):
base = root[len(srcdir) + 1:]
SConscript(joinpath(base, 'SConscript'))
for extra in env['EXTRAS'].split(':'):
extra = os.path.expanduser(extra)
env.Append(CPPPATH=[Dir(extra)])
for root, dirs, files in os.walk(extra, topdown=True):
if 'SConscript' in files:
subdir = root[len(os.path.dirname(extra))+1:]
build_dir = joinpath(env['BUILDDIR'], subdir)
SConscript(joinpath(root, 'SConscript'), build_dir=build_dir)
for opt in env.ExportOptions:
env.ConfigFile(opt)
########################################################################
#
# Deal with python/swig, object code. Collect .py files and
# generating a zip archive that is appended to the m5 binary.
# Prevent any SimObjects from being added after this point, they
# should all have been added in the SConscripts above
#
sim_objects_fixed = True
########################################################################
#
# Manually turn python/generate.py into a python module and import it
#
generate_file = File('python/generate.py')
generate_module = imp.new_module('generate')
sys.modules['generate'] = generate_module
exec file(generate_file.srcnode().abspath, 'r') in generate_module.__dict__
########################################################################
#
# build a generate
#
from generate import Generate
optionDict = dict([(opt, env[opt]) for opt in env.ExportOptions])
generate = Generate(py_sources, sim_object_modfiles, optionDict)
m5 = generate.m5
########################################################################
#
# calculate extra dependencies
#
module_depends = ["m5", "m5.SimObject", "m5.params"]
module_depends = [ File(generate.py_modules[dep]) for dep in module_depends ]
file_depends = [ generate_file ]
depends = module_depends + file_depends
########################################################################
#
# Commands for the basic automatically generated python files
#
# Generate Python file that contains a dict specifying the current
# build_env flags.
def MakeDefinesPyFile(target, source, env):
f = file(str(target[0]), 'w')
print >>f, "m5_build_env = ", source[0]
f.close()
optionDict = dict([(opt, env[opt]) for opt in env.ExportOptions])
env.Command('python/m5/defines.py', Value(optionDict), MakeDefinesPyFile)
# Generate a file with all of the compile options in it
env.Command('python/m5/defines.py', Value(optionDict),
generate.makeDefinesPyFile)
PySource('m5', 'python/m5/defines.py')
def MakeInfoPyFile(target, source, env):
f = file(str(target[0]), 'w')
for src in source:
data = ''.join(file(src.srcnode().abspath, 'r').xreadlines())
print >>f, "%s = %s" % (src, repr(data))
f.close()
# Generate a file that wraps the basic top level files
env.Command('python/m5/info.py',
[ '#/AUTHORS', '#/LICENSE', '#/README', '#/RELEASE_NOTES' ],
MakeInfoPyFile)
generate.makeInfoPyFile)
PySource('m5', 'python/m5/info.py')
def MakeObjectsInitFile(target, source, env):
f = file(str(target[0]), 'w')
print >>f, 'from m5.SimObject import *'
for src_path in source:
src_file = basename(src_path.get_contents())
assert(src_file.endswith('.py'))
src_module = src_file[:-3]
print >>f, 'from %s import *' % src_module
f.close()
# Generate an __init__.py file for the objects package
env.Command('python/m5/objects/__init__.py',
[ Value(o) for o in sim_objects],
MakeObjectsInitFile)
[ Value(o) for o in sort_list(sim_object_modfiles) ],
generate.makeObjectsInitFile)
PySource('m5.objects', 'python/m5/objects/__init__.py')
swig_modules = []
for source in swig_sources:
source.rfile() # Hack to cause the symlink to the .i file to be created
package = swig_source_packages[source]
filename = str(source)
module = basename(filename)
########################################################################
#
# Create all of the SimObject param headers and enum headers
#
assert(module.endswith('.i'))
module = module[:-2]
cc_file = 'swig/%s_wrap.cc' % module
py_file = 'm5/internal/%s.py' % module
# Generate all of the SimObject param struct header files
params_hh_files = []
for name,simobj in generate.sim_objects.iteritems():
extra_deps = [ File(generate.py_modules[simobj.__module__]) ]
hh_file = File('params/%s.hh' % name)
params_hh_files.append(hh_file)
env.Command(hh_file, Value(name), generate.createSimObjectParam)
env.Depends(hh_file, depends + extra_deps)
# Generate any parameter header files needed
for name,param in generate.params.iteritems():
if isinstance(param, m5.params.VectorParamDesc):
ext = 'vptype'
else:
ext = 'ptype'
i_file = File('params/%s_%s.i' % (name, ext))
env.Command(i_file, Value(name), generate.createSwigParam)
env.Depends(i_file, depends)
# Generate all enum header files
for name,enum in generate.enums.iteritems():
extra_deps = [ File(generate.py_modules[enum.__module__]) ]
cc_file = File('enums/%s.cc' % name)
env.Command(cc_file, Value(name), generate.createEnumStrings)
env.Depends(cc_file, depends + extra_deps)
Source(cc_file)
hh_file = File('enums/%s.hh' % name)
env.Command(hh_file, Value(name), generate.createEnumParam)
env.Depends(hh_file, depends + extra_deps)
# Build the big monolithic swigged params module (wraps all SimObject
# param structs and enum structs)
params_file = File('params/params.i')
names = sort_list(generate.sim_objects.keys())
env.Command(params_file, [ Value(v) for v in names ],
generate.buildParams)
env.Depends(params_file, params_hh_files + depends)
SwigSource('m5.objects', params_file)
# Build all swig modules
swig_modules = []
for source,package in swig_sources:
filename = str(source)
assert filename.endswith('.i')
base = '.'.join(filename.split('.')[:-1])
module = basename(base)
cc_file = base + '_wrap.cc'
py_file = base + '.py'
env.Command([cc_file, py_file], source,
'$SWIG $SWIGFLAGS -outdir ${TARGETS[1].dir} '
@ -189,56 +300,25 @@ for source in swig_sources:
Source(cc_file)
PySource(package, py_file)
def MakeSwigInit(target, source, env):
f = file(str(target[0]), 'w')
print >>f, 'extern "C" {'
for module in source:
print >>f, ' void init_%s();' % module.get_contents()
print >>f, '}'
print >>f, 'void init_swig() {'
for module in source:
print >>f, ' init_%s();' % module.get_contents()
print >>f, '}'
f.close()
env.Command('python/swig/init.cc', swig_modules, MakeSwigInit)
def CompilePyFile(target, source, env):
import py_compile
py_compile.compile(str(source[0]), str(target[0]))
# Generate the main swig init file
env.Command('swig/init.cc', swig_modules, generate.makeSwigInit)
Source('swig/init.cc')
# Build the zip file
py_compiled = []
py_arcname = {}
py_zip_depends = []
for source in py_sources:
filename = str(source)
package = py_source_packages[source]
arc_path = package.split('.') + [ basename(filename) + 'c' ]
zip_path = [ 'zip' ] + arc_path
arcname = joinpath(*arc_path)
zipname = joinpath(*zip_path)
f = File(zipname)
env.Command(f, source, CompilePyFile)
py_compiled.append(f)
py_arcname[f] = arcname
env.Command(source.compiled, source.source, generate.compilePyFile)
py_compiled.append(source.compiled)
# make the zipfile depend on the archive name so that the archive
# is rebuilt if the name changes
py_zip_depends.append(Value(arcname))
# Action function to build the zip archive. Uses the PyZipFile module
# included in the standard Python library.
def buildPyZip(target, source, env):
zf = zipfile.ZipFile(str(target[0]), 'w')
for s in source:
arcname = py_arcname[s]
zipname = str(s)
zf.write(zipname, arcname)
zf.close()
py_zip_depends.append(Value(source.arcname))
# Add the zip file target to the environment.
env.Command('m5py.zip', py_compiled, buildPyZip)
env.Depends('m5py.zip', py_zip_depends)
m5zip = File('m5py.zip')
env.Command(m5zip, py_compiled, generate.buildPyZip)
env.Depends(m5zip, py_zip_depends)
########################################################################
#
@ -273,7 +353,7 @@ def makeEnv(label, objsfx, strip = False, **kwargs):
newEnv.Append(**kwargs)
exe = 'm5.' + label # final executable
bin = exe + '.bin' # executable w/o appended Python zip archive
newEnv.Program(bin, make_objs(sources, newEnv))
newEnv.Program(bin, make_objs(cc_sources, newEnv))
if strip:
stripped_bin = bin + '.stripped'
if sys.platform == 'sunos5':

6
src/arch/alpha/AlphaTLB.py
View file

@ -35,8 +35,14 @@ class AlphaTLB(SimObject):
class AlphaDTB(AlphaTLB):
type = 'AlphaDTB'
cxx_namespace = 'AlphaISA'
cxx_class = 'DTB'
size = 64
class AlphaITB(AlphaTLB):
type = 'AlphaITB'
cxx_namespace = 'AlphaISA'
cxx_class = 'ITB'
size = 48

74
src/arch/alpha/freebsd/system.cc
View file

@ -35,16 +35,15 @@
*
*/
#include "arch/alpha/system.hh"
#include "arch/alpha/freebsd/system.hh"
#include "arch/alpha/system.hh"
#include "arch/isa_traits.hh"
#include "arch/vtophys.hh"
#include "base/loader/symtab.hh"
#include "cpu/thread_context.hh"
#include "mem/physical.hh"
#include "mem/port.hh"
#include "arch/isa_traits.hh"
#include "sim/builder.hh"
#include "sim/byteswap.hh"
#include "arch/vtophys.hh"
#define TIMER_FREQUENCY 1193180
@ -77,8 +76,9 @@ FreebsdAlphaSystem::doCalibrateClocks(ThreadContext *tc)
Addr ppc_vaddr = 0;
Addr timer_vaddr = 0;
ppc_vaddr = (Addr)tc->readIntReg(ArgumentReg1);
timer_vaddr = (Addr)tc->readIntReg(ArgumentReg2);
assert(NumArgumentRegs >= 3);
ppc_vaddr = (Addr)tc->readIntReg(ArgumentReg[1]);
timer_vaddr = (Addr)tc->readIntReg(ArgumentReg[2]);
virtPort.write(ppc_vaddr, (uint32_t)Clock::Frequency);
virtPort.write(timer_vaddr, (uint32_t)TIMER_FREQUENCY);
@ -92,64 +92,8 @@ FreebsdAlphaSystem::SkipCalibrateClocksEvent::process(ThreadContext *tc)
((FreebsdAlphaSystem *)tc->getSystemPtr())->doCalibrateClocks(tc);
}
BEGIN_DECLARE_SIM_OBJECT_PARAMS(FreebsdAlphaSystem)
Param<Tick> boot_cpu_frequency;
SimObjectParam<PhysicalMemory *> physmem;
SimpleEnumParam<System::MemoryMode> mem_mode;
Param<string> kernel;
Param<string> console;
Param<string> pal;
Param<string> boot_osflags;
Param<string> readfile;
Param<string> symbolfile;
Param<unsigned int> init_param;
Param<uint64_t> system_type;
Param<uint64_t> system_rev;
END_DECLARE_SIM_OBJECT_PARAMS(FreebsdAlphaSystem)
BEGIN_INIT_SIM_OBJECT_PARAMS(FreebsdAlphaSystem)
INIT_PARAM(boot_cpu_frequency, "Frequency of the boot CPU"),
INIT_PARAM(physmem, "phsyical memory"),
INIT_ENUM_PARAM(mem_mode, "Memory Mode, (1=atomic, 2=timing)",
System::MemoryModeStrings),
INIT_PARAM(kernel, "file that contains the kernel code"),
INIT_PARAM(console, "file that contains the console code"),
INIT_PARAM(pal, "file that contains palcode"),
INIT_PARAM_DFLT(boot_osflags, "flags to pass to the kernel during boot",
"a"),
INIT_PARAM_DFLT(readfile, "file to read startup script from", ""),
INIT_PARAM_DFLT(symbolfile, "file to read symbols from", ""),
INIT_PARAM_DFLT(init_param, "numerical value to pass into simulator", 0),
INIT_PARAM_DFLT(system_type, "Type of system we are emulating", 34),
INIT_PARAM_DFLT(system_rev, "Revision of system we are emulating", 1<<10)
END_INIT_SIM_OBJECT_PARAMS(FreebsdAlphaSystem)
CREATE_SIM_OBJECT(FreebsdAlphaSystem)
FreebsdAlphaSystem *
FreebsdAlphaSystemParams::create()
{
AlphaSystem::Params *p = new AlphaSystem::Params;
p->name = getInstanceName();
p->boot_cpu_frequency = boot_cpu_frequency;
p->physmem = physmem;
p->mem_mode = mem_mode;
p->kernel_path = kernel;
p->console_path = console;
p->palcode = pal;
p->boot_osflags = boot_osflags;
p->init_param = init_param;
p->readfile = readfile;
p->symbolfile = symbolfile;
p->system_type = system_type;
p->system_rev = system_rev;
return new FreebsdAlphaSystem(p);
return new FreebsdAlphaSystem(this);
}
REGISTER_SIM_OBJECT("FreebsdAlphaSystem", FreebsdAlphaSystem)

11
src/arch/alpha/freebsd/system.hh
View file

@ -28,10 +28,13 @@
* Authors: Ben Nash
*/
#ifndef __KERN_FREEBSD_FREEBSD_SYSTEM_HH__
#define __KERN_FREEBSD_FREEBSD_SYSTEM_HH__
#ifndef __ARCH_ALPHA_FREEBSD_SYSTEM_HH__
#define __ARCH_ALPHA_FREEBSD_SYSTEM_HH__
#include "arch/alpha/system.hh"
#include "kern/system_events.hh"
#include "params/FreebsdAlphaSystem.hh"
#include "sim/system.hh"
class FreebsdAlphaSystem : public AlphaSystem
{
@ -49,10 +52,12 @@ class FreebsdAlphaSystem : public AlphaSystem
SkipCalibrateClocksEvent *skipCalibrateClocks;
public:
typedef FreebsdAlphaSystemParams Params;
FreebsdAlphaSystem(Params *p);
~FreebsdAlphaSystem();
void doCalibrateClocks(ThreadContext *tc);
};
#endif // __KERN_FREEBSD_FREEBSD_SYSTEM_HH__
#endif // __ARCH_ALPHA_FREEBSD_SYSTEM_HH__

12
src/arch/alpha/isa_traits.hh
View file

@ -156,14 +156,12 @@ namespace AlphaISA
const int ReturnAddressReg = 26;
const int ReturnValueReg = 0;
const int FramePointerReg = 15;
const int ArgumentReg0 = 16;
const int ArgumentReg1 = 17;
const int ArgumentReg2 = 18;
const int ArgumentReg3 = 19;
const int ArgumentReg4 = 20;
const int ArgumentReg5 = 21;
const int ArgumentReg[] = {16, 17, 18, 19, 20, 21};
const int NumArgumentRegs = sizeof(ArgumentReg) / sizeof(const int);
const int SyscallNumReg = ReturnValueReg;
const int SyscallPseudoReturnReg = ArgumentReg4;
const int SyscallPseudoReturnReg = ArgumentReg[4];
const int SyscallSuccessReg = 19;
const int LogVMPageSize = 13; // 8K bytes

63
src/arch/alpha/linux/system.cc
View file

@ -54,7 +54,6 @@
#include "kern/linux/events.hh"
#include "mem/physical.hh"
#include "mem/port.hh"
#include "sim/builder.hh"
#include "sim/byteswap.hh"
using namespace std;
@ -192,64 +191,8 @@ LinuxAlphaSystem::PrintThreadInfo::process(ThreadContext *tc)
ti.curTaskName(), ti.curTaskPID(), ti.curTaskStart());
}
BEGIN_DECLARE_SIM_OBJECT_PARAMS(LinuxAlphaSystem)
Param<Tick> boot_cpu_frequency;
SimObjectParam<PhysicalMemory *> physmem;
SimpleEnumParam<System::MemoryMode> mem_mode;
Param<string> kernel;
Param<string> console;
Param<string> pal;
Param<string> boot_osflags;
Param<string> readfile;
Param<string> symbolfile;
Param<unsigned int> init_param;
Param<uint64_t> system_type;
Param<uint64_t> system_rev;
END_DECLARE_SIM_OBJECT_PARAMS(LinuxAlphaSystem)
BEGIN_INIT_SIM_OBJECT_PARAMS(LinuxAlphaSystem)
INIT_PARAM(boot_cpu_frequency, "Frequency of the boot CPU"),
INIT_PARAM(physmem, "phsyical memory"),
INIT_ENUM_PARAM(mem_mode, "Memory Mode, (1=atomic, 2=timing)",
System::MemoryModeStrings),
INIT_PARAM(kernel, "file that contains the kernel code"),
INIT_PARAM(console, "file that contains the console code"),
INIT_PARAM(pal, "file that contains palcode"),
INIT_PARAM_DFLT(boot_osflags, "flags to pass to the kernel during boot",
"a"),
INIT_PARAM_DFLT(readfile, "file to read startup script from", ""),
INIT_PARAM_DFLT(symbolfile, "file to read symbols from", ""),
INIT_PARAM_DFLT(init_param, "numerical value to pass into simulator", 0),
INIT_PARAM_DFLT(system_type, "Type of system we are emulating", 34),
INIT_PARAM_DFLT(system_rev, "Revision of system we are emulating", 1<<10)
END_INIT_SIM_OBJECT_PARAMS(LinuxAlphaSystem)
CREATE_SIM_OBJECT(LinuxAlphaSystem)
LinuxAlphaSystem *
LinuxAlphaSystemParams::create()
{
AlphaSystem::Params *p = new AlphaSystem::Params;
p->name = getInstanceName();
p->boot_cpu_frequency = boot_cpu_frequency;
p->physmem = physmem;
p->mem_mode = mem_mode;
p->kernel_path = kernel;
p->console_path = console;
p->palcode = pal;
p->boot_osflags = boot_osflags;
p->init_param = init_param;
p->readfile = readfile;
p->symbolfile = symbolfile;
p->system_type = system_type;
p->system_rev = system_rev;
return new LinuxAlphaSystem(p);
return new LinuxAlphaSystem(this);
}
REGISTER_SIM_OBJECT("LinuxAlphaSystem", LinuxAlphaSystem)

2
src/arch/alpha/linux/system.hh
View file

@ -41,6 +41,7 @@ class IdleStartEvent;
#include "arch/alpha/idle_event.hh"
#include "arch/alpha/system.hh"
#include "kern/linux/events.hh"
#include "params/LinuxAlphaSystem.hh"
using namespace AlphaISA;
using namespace Linux;
@ -129,6 +130,7 @@ class LinuxAlphaSystem : public AlphaSystem
IdleStartEvent *idleStartEvent;
public:
typedef LinuxAlphaSystemParams Params;
LinuxAlphaSystem(Params *p);
~LinuxAlphaSystem();

73
src/arch/alpha/system.cc
View file

@ -39,8 +39,8 @@
#include "base/loader/symtab.hh"
#include "base/trace.hh"
#include "mem/physical.hh"
#include "params/AlphaSystem.hh"
#include "sim/byteswap.hh"
#include "sim/builder.hh"
using namespace LittleEndianGuest;
@ -56,14 +56,14 @@ AlphaSystem::AlphaSystem(Params *p)
* Load the pal, and console code into memory
*/
// Load Console Code
console = createObjectFile(params()->console_path);
console = createObjectFile(params()->console);
if (console == NULL)
fatal("Could not load console file %s", params()->console_path);
fatal("Could not load console file %s", params()->console);
// Load pal file
pal = createObjectFile(params()->palcode);
pal = createObjectFile(params()->pal);
if (pal == NULL)
fatal("Could not load PALcode file %s", params()->palcode);
fatal("Could not load PALcode file %s", params()->pal);
// Load program sections into memory
@ -212,65 +212,8 @@ AlphaSystem::unserialize(Checkpoint *cp, const std::string &section)
palSymtab->unserialize("pal_symtab", cp, section);
}
BEGIN_DECLARE_SIM_OBJECT_PARAMS(AlphaSystem)
Param<Tick> boot_cpu_frequency;
SimObjectParam<PhysicalMemory *> physmem;
SimpleEnumParam<System::MemoryMode> mem_mode;
Param<std::string> kernel;
Param<std::string> console;
Param<std::string> pal;
Param<std::string> boot_osflags;
Param<std::string> readfile;
Param<std::string> symbolfile;
Param<unsigned int> init_param;
Param<uint64_t> system_type;
Param<uint64_t> system_rev;
END_DECLARE_SIM_OBJECT_PARAMS(AlphaSystem)
BEGIN_INIT_SIM_OBJECT_PARAMS(AlphaSystem)
INIT_PARAM(boot_cpu_frequency, "Frequency of the boot CPU"),
INIT_PARAM(physmem, "phsyical memory"),
INIT_ENUM_PARAM(mem_mode, "Memory Mode, (1=atomic, 2=timing)",
System::MemoryModeStrings),
INIT_PARAM(kernel, "file that contains the kernel code"),
INIT_PARAM(console, "file that contains the console code"),
INIT_PARAM(pal, "file that contains palcode"),
INIT_PARAM_DFLT(boot_osflags, "flags to pass to the kernel during boot",
"a"),
INIT_PARAM_DFLT(readfile, "file to read startup script from", ""),
INIT_PARAM_DFLT(symbolfile, "file to read symbols from", ""),
INIT_PARAM_DFLT(init_param, "numerical value to pass into simulator", 0),
INIT_PARAM_DFLT(system_type, "Type of system we are emulating", 34),
INIT_PARAM_DFLT(system_rev, "Revision of system we are emulating", 1<<10)
END_INIT_SIM_OBJECT_PARAMS(AlphaSystem)
CREATE_SIM_OBJECT(AlphaSystem)
AlphaSystem *
AlphaSystemParams::create()
{
AlphaSystem::Params *p = new AlphaSystem::Params;
p->name = getInstanceName();
p->boot_cpu_frequency = boot_cpu_frequency;
p->physmem = physmem;
p->mem_mode = mem_mode;
p->kernel_path = kernel;
p->console_path = console;
p->palcode = pal;
p->boot_osflags = boot_osflags;
p->init_param = init_param;
p->readfile = readfile;
p->symbolfile = symbolfile;
p->system_type = system_type;
p->system_rev = system_rev;
return new AlphaSystem(p);
return new AlphaSystem(this);
}
REGISTER_SIM_OBJECT("AlphaSystem", AlphaSystem)

13
src/arch/alpha/system.hh
View file

@ -35,25 +35,18 @@
#include <string>
#include <vector>
#include "sim/system.hh"
#include "base/loader/symtab.hh"
#include "cpu/pc_event.hh"
#include "kern/system_events.hh"
#include "params/AlphaSystem.hh"
#include "sim/sim_object.hh"
#include "sim/system.hh"
class AlphaSystem : public System
{
public:
struct Params : public System::Params
{
std::string console_path;
std::string palcode;
uint64_t system_type;
uint64_t system_rev;
};
typedef AlphaSystemParams Params;
AlphaSystem(Params *p);
~AlphaSystem();
/**

45
src/arch/alpha/tlb.cc
View file

@ -41,7 +41,8 @@
#include "base/trace.hh"
#include "config/alpha_tlaser.hh"
#include "cpu/thread_context.hh"
#include "sim/builder.hh"
#include "params/AlphaDTB.hh"
#include "params/AlphaITB.hh"
using namespace std;
using namespace EV5;
@ -600,44 +601,14 @@ TLB::index(bool advance)
/* end namespace AlphaISA */ }
DEFINE_SIM_OBJECT_CLASS_NAME("AlphaTLB", TLB)
BEGIN_DECLARE_SIM_OBJECT_PARAMS(ITB)
Param<int> size;
END_DECLARE_SIM_OBJECT_PARAMS(ITB)
BEGIN_INIT_SIM_OBJECT_PARAMS(ITB)
INIT_PARAM_DFLT(size, "TLB size", 48)
END_INIT_SIM_OBJECT_PARAMS(ITB)
CREATE_SIM_OBJECT(ITB)
AlphaISA::ITB *
AlphaITBParams::create()
{
return new ITB(getInstanceName(), size);
return new AlphaISA::ITB(name, size);
}
REGISTER_SIM_OBJECT("AlphaITB", ITB)
BEGIN_DECLARE_SIM_OBJECT_PARAMS(DTB)
Param<int> size;
END_DECLARE_SIM_OBJECT_PARAMS(DTB)
BEGIN_INIT_SIM_OBJECT_PARAMS(DTB)
INIT_PARAM_DFLT(size, "TLB size", 64)
END_INIT_SIM_OBJECT_PARAMS(DTB)
CREATE_SIM_OBJECT(DTB)
AlphaISA::DTB *
AlphaDTBParams::create()
{
return new DTB(getInstanceName(), size);
return new AlphaISA::DTB(name, size);
}
REGISTER_SIM_OBJECT("AlphaDTB", DTB)

62
src/arch/alpha/tru64/system.cc
View file

@ -40,7 +40,6 @@
#include "kern/system_events.hh"
#include "mem/physical.hh"
#include "mem/port.hh"
#include "sim/builder.hh"
using namespace std;
@ -91,63 +90,8 @@ Tru64AlphaSystem::~Tru64AlphaSystem()
#endif
}
BEGIN_DECLARE_SIM_OBJECT_PARAMS(Tru64AlphaSystem)
Param<Tick> boot_cpu_frequency;
SimObjectParam<PhysicalMemory *> physmem;
SimpleEnumParam<System::MemoryMode> mem_mode;
Param<string> kernel;
Param<string> console;
Param<string> pal;
Param<string> boot_osflags;
Param<string> readfile;
Param<string> symbolfile;
Param<unsigned int> init_param;
Param<uint64_t> system_type;
Param<uint64_t> system_rev;
END_DECLARE_SIM_OBJECT_PARAMS(Tru64AlphaSystem)
BEGIN_INIT_SIM_OBJECT_PARAMS(Tru64AlphaSystem)
INIT_PARAM(boot_cpu_frequency, "frequency of the boot cpu"),
INIT_PARAM(physmem, "phsyical memory"),
INIT_ENUM_PARAM(mem_mode, "Memory Mode, (1=atomic, 2=timing)",
System::MemoryModeStrings),
INIT_PARAM(kernel, "file that contains the kernel code"),
INIT_PARAM(console, "file that contains the console code"),
INIT_PARAM(pal, "file that contains palcode"),
INIT_PARAM_DFLT(boot_osflags, "flags to pass to the kernel during boot",
"a"),
INIT_PARAM_DFLT(readfile, "file to read startup script from", ""),
INIT_PARAM_DFLT(symbolfile, "file to read symbols from", ""),
INIT_PARAM_DFLT(init_param, "numerical value to pass into simulator", 0),
INIT_PARAM_DFLT(system_type, "Type of system we are emulating", 12),
INIT_PARAM_DFLT(system_rev, "Revision of system we are emulating", 2<<1)
END_INIT_SIM_OBJECT_PARAMS(Tru64AlphaSystem)
CREATE_SIM_OBJECT(Tru64AlphaSystem)
Tru64AlphaSystem *
Tru64AlphaSystemParams::create()
{
AlphaSystem::Params *p = new AlphaSystem::Params;
p->name = getInstanceName();
p->boot_cpu_frequency = boot_cpu_frequency;
p->physmem = physmem;
p->mem_mode = mem_mode;
p->kernel_path = kernel;
p->console_path = console;
p->palcode = pal;
p->boot_osflags = boot_osflags;
p->init_param = init_param;
p->readfile = readfile;
p->symbolfile = symbolfile;
p->system_type = system_type;
p->system_rev = system_rev;
return new Tru64AlphaSystem(p);
return new Tru64AlphaSystem(this);
}
REGISTER_SIM_OBJECT("Tru64AlphaSystem", Tru64AlphaSystem)

2
src/arch/alpha/tru64/system.hh
View file

@ -34,6 +34,7 @@
#include "arch/alpha/system.hh"
#include "arch/isa_traits.hh"
#include "params/Tru64AlphaSystem.hh"
#include "sim/system.hh"
class ThreadContext;
@ -64,6 +65,7 @@ class Tru64AlphaSystem : public AlphaSystem
DumpMbufEvent *dumpMbufEvent;
public:
typedef Tru64AlphaSystemParams Params;
Tru64AlphaSystem(Params *p);
~Tru64AlphaSystem();

10
src/arch/mips/isa_traits.hh
View file

@ -74,10 +74,10 @@ namespace MipsISA
const int ReturnValueReg = 2;
const int ReturnValueReg1 = 2;
const int ReturnValueReg2 = 3;
const int ArgumentReg0 = 4;
const int ArgumentReg1 = 5;
const int ArgumentReg2 = 6;
const int ArgumentReg3 = 7;
const int ArgumentReg[] = {4, 5, 6, 7};
const int NumArgumentRegs = sizeof(ArgumentReg) / sizeof(const int);
const int KernelReg0 = 26;
const int KernelReg1 = 27;
const int GlobalPointerReg = 28;
@ -87,7 +87,7 @@ namespace MipsISA
const int SyscallNumReg = ReturnValueReg1;
const int SyscallPseudoReturnReg = ReturnValueReg2;
const int SyscallSuccessReg = ArgumentReg3;
const int SyscallSuccessReg = ArgumentReg[3];
const int LogVMPageSize = 13; // 8K bytes
const int VMPageSize = (1 << LogVMPageSize);

6
src/arch/sparc/SparcTLB.py
View file

@ -35,8 +35,14 @@ class SparcTLB(SimObject):
class SparcDTB(SparcTLB):
type = 'SparcDTB'
cxx_namespace = 'SparcISA'
cxx_class = 'DTB'
size = 64
class SparcITB(SparcTLB):
type = 'SparcITB'
cxx_namespace = 'SparcISA'
cxx_class = 'ITB'
size = 64

12
src/arch/sparc/isa_traits.hh
View file

@ -69,14 +69,12 @@ namespace SparcISA
const int ReturnAddressReg = 31; // post call, precall is 15
const int ReturnValueReg = 8; // Post return, 24 is pre-return.
const int FramePointerReg = 30;
const int ArgumentReg0 = 8;
const int ArgumentReg1 = 9;
const int ArgumentReg2 = 10;
const int ArgumentReg3 = 11;
const int ArgumentReg4 = 12;
const int ArgumentReg5 = 13;
const int ArgumentReg[] = {8, 9, 10, 11, 12, 13};
const int NumArgumentRegs = sizeof(ArgumentReg) / sizeof(const int);
// Some OS syscall use a second register (o1) to return a second value
const int SyscallPseudoReturnReg = ArgumentReg1;
const int SyscallPseudoReturnReg = ArgumentReg[1];
//XXX These numbers are bogus
const int MaxInstSrcRegs = 8;

10
src/arch/sparc/process.cc
View file

@ -399,8 +399,9 @@ Sparc64LiveProcess::argsInit(int intSize, int pageSize)
initVirtMem->writeBlob(spillStart, (uint8_t*)spillHandler64, spillSize);
//Set up the thread context to start running the process
threadContexts[0]->setIntReg(ArgumentReg0, argc);
threadContexts[0]->setIntReg(ArgumentReg1, argv_array_base);
assert(NumArgumentRegs >= 2);
threadContexts[0]->setIntReg(ArgumentReg[0], argc);
threadContexts[0]->setIntReg(ArgumentReg[1], argv_array_base);
threadContexts[0]->setIntReg(StackPointerReg, stack_min - StackBias);
Addr prog_entry = objFile->entryPoint();
@ -627,8 +628,9 @@ Sparc32LiveProcess::argsInit(int intSize, int pageSize)
initVirtMem->writeBlob(spillStart, (uint8_t*)spillHandler32, spillSize);
//Set up the thread context to start running the process
//threadContexts[0]->setIntReg(ArgumentReg0, argc);
//threadContexts[0]->setIntReg(ArgumentReg1, argv_array_base);
//assert(NumArgumentRegs >= 2);
//threadContexts[0]->setIntReg(ArgumentReg[0], argc);
//threadContexts[0]->setIntReg(ArgumentReg[1], argv_array_base);
threadContexts[0]->setIntReg(StackPointerReg, stack_min);
uint32_t prog_entry = objFile->entryPoint();

104
src/arch/sparc/system.cc
View file

@ -35,8 +35,8 @@
#include "base/loader/symtab.hh"
#include "base/trace.hh"
#include "mem/physical.hh"
#include "params/SparcSystem.hh"
#include "sim/byteswap.hh"
#include "sim/builder.hh"
using namespace BigEndianGuest;
@ -216,104 +216,8 @@ SparcSystem::unserialize(Checkpoint *cp, const std::string &section)
partitionDescSymtab->unserialize("partition_desc_symtab", cp, section);
}
BEGIN_DECLARE_SIM_OBJECT_PARAMS(SparcSystem)
SimObjectParam<PhysicalMemory *> physmem;
SimObjectParam<PhysicalMemory *> rom;
SimObjectParam<PhysicalMemory *> nvram;
SimObjectParam<PhysicalMemory *> hypervisor_desc;
SimObjectParam<PhysicalMemory *> partition_desc;
SimpleEnumParam<System::MemoryMode> mem_mode;
Param<Addr> reset_addr;
Param<Addr> hypervisor_addr;
Param<Addr> openboot_addr;
Param<Addr> nvram_addr;
Param<Addr> hypervisor_desc_addr;
Param<Addr> partition_desc_addr;
Param<std::string> kernel;
Param<std::string> reset_bin;
Param<std::string> hypervisor_bin;
Param<std::string> openboot_bin;
Param<std::string> nvram_bin;
Param<std::string> hypervisor_desc_bin;
Param<std::string> partition_desc_bin;
Param<Tick> boot_cpu_frequency;
Param<std::string> boot_osflags;
Param<std::string> readfile;
Param<unsigned int> init_param;
END_DECLARE_SIM_OBJECT_PARAMS(SparcSystem)
BEGIN_INIT_SIM_OBJECT_PARAMS(SparcSystem)
INIT_PARAM(physmem, "phsyical memory"),
INIT_PARAM(rom, "ROM for boot code"),
INIT_PARAM(nvram, "Non-volatile RAM for the nvram"),
INIT_PARAM(hypervisor_desc, "ROM for the hypervisor description"),
INIT_PARAM(partition_desc, "ROM for the partition description"),
INIT_ENUM_PARAM(mem_mode, "Memory Mode, (1=atomic, 2=timing)",
System::MemoryModeStrings),
INIT_PARAM(reset_addr, "Address that reset should be loaded at"),
INIT_PARAM(hypervisor_addr, "Address that hypervisor should be loaded at"),
INIT_PARAM(openboot_addr, "Address that openboot should be loaded at"),
INIT_PARAM(nvram_addr, "Address that nvram should be loaded at"),
INIT_PARAM(hypervisor_desc_addr,
"Address that hypervisor description should be loaded at"),
INIT_PARAM(partition_desc_addr,
"Address that partition description should be loaded at"),
INIT_PARAM(kernel, "file that contains the kernel code"),
INIT_PARAM(reset_bin, "file that contains the reset code"),
INIT_PARAM(hypervisor_bin, "file that contains the hypervisor code"),
INIT_PARAM(openboot_bin, "file that contains the openboot code"),
INIT_PARAM(nvram_bin, "file that contains the nvram image"),
INIT_PARAM(hypervisor_desc_bin,
"file that contains the hypervisor description image"),
INIT_PARAM(partition_desc_bin,
"file that contains the partition description image"),
INIT_PARAM(boot_cpu_frequency, "Frequency of the boot CPU"),
INIT_PARAM_DFLT(boot_osflags, "flags to pass to the kernel during boot",
"a"),
INIT_PARAM_DFLT(readfile, "file to read startup script from", ""),
INIT_PARAM_DFLT(init_param, "numerical value to pass into simulator", 0)
END_INIT_SIM_OBJECT_PARAMS(SparcSystem)
CREATE_SIM_OBJECT(SparcSystem)
SparcSystem *
SparcSystemParams::create()
{
SparcSystem::Params *p = new SparcSystem::Params;
p->name = getInstanceName();
p->boot_cpu_frequency = boot_cpu_frequency;
p->physmem = physmem;
p->rom = rom;
p->nvram = nvram;
p->hypervisor_desc = hypervisor_desc;
p->partition_desc = partition_desc;
p->mem_mode = mem_mode;
p->kernel_path = kernel;
p->reset_addr = reset_addr;
p->hypervisor_addr = hypervisor_addr;
p->openboot_addr = openboot_addr;
p->nvram_addr = nvram_addr;
p->hypervisor_desc_addr = hypervisor_desc_addr;
p->partition_desc_addr = partition_desc_addr;
p->reset_bin = reset_bin;
p->hypervisor_bin = hypervisor_bin;
p->openboot_bin = openboot_bin;
p->nvram_bin = nvram_bin;
p->hypervisor_desc_bin = hypervisor_desc_bin;
p->partition_desc_bin = partition_desc_bin;
p->boot_osflags = boot_osflags;
p->init_param = init_param;
p->readfile = readfile;
return new SparcSystem(p);
return new SparcSystem(this);
}
REGISTER_SIM_OBJECT("SparcSystem", SparcSystem)

24
src/arch/sparc/system.hh
View file

@ -37,35 +37,15 @@
#include "base/loader/symtab.hh"
#include "cpu/pc_event.hh"
#include "kern/system_events.hh"
#include "params/SparcSystem.hh"
#include "sim/sim_object.hh"
#include "sim/system.hh"
class SparcSystem : public System
{
public:
struct Params : public System::Params
{
PhysicalMemory *rom;
PhysicalMemory *nvram;
PhysicalMemory *hypervisor_desc;
PhysicalMemory *partition_desc;
Addr reset_addr;
Addr hypervisor_addr;
Addr openboot_addr;
Addr nvram_addr;
Addr hypervisor_desc_addr;
Addr partition_desc_addr;
std::string reset_bin;
std::string hypervisor_bin;
std::string openboot_bin;
std::string nvram_bin;
std::string hypervisor_desc_bin;
std::string partition_desc_bin;
std::string boot_osflags;
};
typedef SparcSystemParams Params;
SparcSystem(Params *p);
~SparcSystem();
/**

47
src/arch/sparc/tlb.cc
View file

@ -39,7 +39,8 @@
#include "cpu/base.hh"
#include "mem/packet_access.hh"
#include "mem/request.hh"
#include "sim/builder.hh"
#include "params/SparcDTB.hh"
#include "params/SparcITB.hh"
#include "sim/system.hh"
/* @todo remove some of the magic constants. -- ali
@ -1386,46 +1387,14 @@ TLB::unserialize(Checkpoint *cp, const std::string &section)
/* end namespace SparcISA */ }
using namespace SparcISA;
DEFINE_SIM_OBJECT_CLASS_NAME("SparcTLB", TLB)
BEGIN_DECLARE_SIM_OBJECT_PARAMS(ITB)
Param<int> size;
END_DECLARE_SIM_OBJECT_PARAMS(ITB)
BEGIN_INIT_SIM_OBJECT_PARAMS(ITB)
INIT_PARAM_DFLT(size, "TLB size", 48)
END_INIT_SIM_OBJECT_PARAMS(ITB)
CREATE_SIM_OBJECT(ITB)
SparcISA::ITB *
SparcITBParams::create()
{
return new ITB(getInstanceName(), size);
return new SparcISA::ITB(name, size);
}
REGISTER_SIM_OBJECT("SparcITB", ITB)
BEGIN_DECLARE_SIM_OBJECT_PARAMS(DTB)
Param<int> size;
END_DECLARE_SIM_OBJECT_PARAMS(DTB)
BEGIN_INIT_SIM_OBJECT_PARAMS(DTB)
INIT_PARAM_DFLT(size, "TLB size", 64)
END_INIT_SIM_OBJECT_PARAMS(DTB)
CREATE_SIM_OBJECT(DTB)
SparcISA::DTB *
SparcDTBParams::create()
{
return new DTB(getInstanceName(), size);
return new SparcISA::DTB(name, size);
}
REGISTER_SIM_OBJECT("SparcDTB", DTB)

56
src/arch/x86/insts/microldstop.hh
View file

@ -96,6 +96,62 @@ namespace X86ISA
std::string generateDisassembly(Addr pc,
const SymbolTable *symtab) const;
template<class Context, class MemType>
Fault read(Context *xc, Addr EA, MemType & Mem, unsigned flags) const
{
Fault fault = NoFault;
int size = dataSize;
Addr alignedEA = EA & ~(dataSize - 1);
if (EA != alignedEA)
size *= 2;
switch(size)
{
case 1:
fault = xc->read(alignedEA, (uint8_t&)Mem, flags);
break;
case 2:
fault = xc->read(alignedEA, (uint16_t&)Mem, flags);
break;
case 4:
fault = xc->read(alignedEA, (uint32_t&)Mem, flags);
break;
case 8:
fault = xc->read(alignedEA, (uint64_t&)Mem, flags);
break;
default:
panic("Bad operand size %d!\n", size);
}
return fault;
}
template<class Context, class MemType>
Fault write(Context *xc, MemType & Mem, Addr EA, unsigned flags) const
{
Fault fault = NoFault;
int size = dataSize;
Addr alignedEA = EA & ~(dataSize - 1);
if (EA != alignedEA)
size *= 2;
switch(size)
{
case 1:
fault = xc->write((uint8_t&)Mem, alignedEA, flags, 0);
break;
case 2:
fault = xc->write((uint16_t&)Mem, alignedEA, flags, 0);
break;
case 4:
fault = xc->write((uint32_t&)Mem, alignedEA, flags, 0);
break;
case 8:
fault = xc->write((uint64_t&)Mem, alignedEA, flags, 0);
break;
default:
panic("Bad operand size %d!\n", size);
}
return fault;
}
};
}

132
src/arch/x86/isa/decoder/one_byte_opcodes.isa
View file

@ -72,7 +72,7 @@
default: MultiInst::ADD(OPCODE_OP_BOTTOM3,
[Eb,Gb], [Ev,Gv],
[Gb,Eb], [Gv,Ev],
[rAl,Ib], [rAx,Iz]);
[rAb,Ib], [rAv,Iz]);
}
0x01: decode OPCODE_OP_BOTTOM3 {
0x6: decode MODE_SUBMODE {
@ -85,7 +85,7 @@
default: MultiInst::OR(OPCODE_OP_BOTTOM3,
[Eb,Gb], [Ev,Gv],
[Gb,Eb], [Gv,Ev],
[rAl,Ib], [rAx,Iz]);
[rAb,Ib], [rAv,Iz]);
}
0x02: decode OPCODE_OP_BOTTOM3 {
0x6: decode MODE_SUBMODE {
@ -99,7 +99,7 @@
default: MultiInst::ADC(OPCODE_OP_BOTTOM3,
[Eb,Gb], [Ev,Gv],
[Gb,Eb], [Gv,Ev],
[rAl,Ib], [rAx,Iz]);
[rAb,Ib], [rAv,Iz]);
}
0x03: decode OPCODE_OP_BOTTOM3 {
0x6: decode MODE_SUBMODE {
@ -113,7 +113,7 @@
default: MultiInst::SBB(OPCODE_OP_BOTTOM3,
[Eb,Gb], [Ev,Gv],
[Gb,Eb], [Gv,Ev],
[rAl,Ib], [rAx,Iz]);
[rAb,Ib], [rAv,Iz]);
}
0x04: decode OPCODE_OP_BOTTOM3 {
0x6: M5InternalError::error(
@ -125,7 +125,7 @@
default: MultiInst::AND(OPCODE_OP_BOTTOM3,
[Eb,Gb], [Ev,Gv],
[Gb,Eb], [Gv,Ev],
[rAl,Ib], [rAx,Iz]);
[rAb,Ib], [rAv,Iz]);
}
0x05: decode OPCODE_OP_BOTTOM3 {
0x6: M5InternalError::error(
@ -134,7 +134,7 @@
default: MultiInst::SUB(OPCODE_OP_BOTTOM3,
[Eb,Gb], [Ev,Gv],
[Gb,Eb], [Gv,Ev],
[rAl,Ib], [rAx,Iz]);
[rAb,Ib], [rAv,Iz]);
}
0x06: decode OPCODE_OP_BOTTOM3 {
0x6: M5InternalError::error(
@ -146,7 +146,7 @@
default: MultiInst::XOR(OPCODE_OP_BOTTOM3,
[Eb,Gb], [Ev,Gv],
[Gb,Eb], [Gv,Ev],
[rAl,Ib], [rAx,Iz]);
[rAb,Ib], [rAv,Iz]);
}
0x07: decode OPCODE_OP_BOTTOM3 {
0x6: M5InternalError::error(
@ -158,37 +158,40 @@
default: MultiInst::CMP(OPCODE_OP_BOTTOM3,
[Eb,Gb], [Ev,Gv],
[Gb,Eb], [Gv,Ev],
[rAl,Ib], [rAx,Iz]);
[rAb,Ib], [rAv,Iz]);
}
format Inst {
0x08: decode MODE_SUBMODE {
0x0: M5InternalError::error (
{{"Tried to execute an REX prefix!"}});
default: Inst::INC(B);
default: INC(Bv);
}
0x09: decode MODE_SUBMODE {
0x0: M5InternalError::error (
{{"Tried to execute an REX prefix!"}});
default: Inst::DEC(B);
default: DEC(Bv);
}
format Inst {
0x0A: PUSH(B);
0x0B: POP(B);
0x0A: PUSH(Bv);
0x0B: POP(Bv);
}
0x0C: decode OPCODE_OP_BOTTOM3 {
0x0: decode MODE_SUBMODE {
0x0: Inst::UD2();
default: pusha();
default: Inst::PUSHA();
}
0x1: decode MODE_SUBMODE {
0x0: Inst::UD2();
default: popa();
default: Inst::POPA();
}
0x2: decode MODE_SUBMODE {
0x0: Inst::UD2();
default: bound_Gv_Ma();
}
0x3: decode MODE_SUBMODE {
0x0: Inst::MOVSXD(Gv,Ed);
//The second operand should really be of size "d", but it's
//set to "v" in order to have a consistent register size.
//This shouldn't affect behavior.
0x0: Inst::MOVSXD(Gv,Ev);
default: arpl_Ew_Gw();
}
0x4: M5InternalError::error(
@ -201,10 +204,10 @@
{{"Tried to execute the DS address size override prefix!"}});
}
0x0D: decode OPCODE_OP_BOTTOM3 {
0x0: push_Iz();
0x1: imul_Gv_Ev_Iz();
0x2: push_Ib();
0x3: imul_Gv_Ev_Ib();
0x0: Inst::PUSH(Iz);
0x1: Inst::IMUL(Gv,Ev,Iz);
0x2: Inst::PUSH(Ib);
0x3: Inst::IMUL(Gv,Ev,Ib);
0x4: ins_Yb_Dx();
0x5: ins_Yz_Dx();
0x6: outs_Dx_Xb();
@ -302,8 +305,8 @@
default: xchg_B_rAX();
}
0x13: decode OPCODE_OP_BOTTOM3 {
0x0: cbw_or_cwde_or_cdqe_rAX();
0x1: cwd_or_cdq_or_cqo_rAX_rDX();
0x0: Inst::CDQE(rAv);
0x1: Inst::CQO(rAv,rDv);
0x2: decode MODE_SUBMODE {
0x0: Inst::UD2();
default: call_far_Ap();
@ -333,8 +336,8 @@
0x7: cmps_Yv_Xv();
}
0x15: decode OPCODE_OP_BOTTOM3 {
0x0: Inst::TEST(rAl,Ib);
0x1: Inst::TEST(rAX,Iz);
0x0: Inst::TEST(rAb,Ib);
0x1: Inst::TEST(rAv,Iz);
0x2: stos_Yb_Al();
0x3: stos_Yv_rAX();
0x4: lods_Al_Xb();
@ -343,8 +346,8 @@
0x7: scas_Yv_rAX();
}
format Inst {
0x16: MOV(B,Ib);
0x17: MOV(B,Iv);
0x16: MOV(Bb,Ib);
0x17: MOV(Bv,Iv);
0x18: decode OPCODE_OP_BOTTOM3 {
//0x0: group2_Eb_Ib();
0x0: decode MODRM_REG {
@ -404,10 +407,55 @@
0x7: iret();
}
0x1A: decode OPCODE_OP_BOTTOM3 {
0x0: group2_Eb_1();
0x1: group2_Ev_1();
0x2: group2_Eb_Cl();
0x3: group2_Ev_Cl();
format Inst {
//0x0: group2_Eb_1();
0x0: decode MODRM_REG {
0x0: ROL_1(Eb);
0x1: ROR_1(Eb);
0x2: RCL_1(Eb);
0x3: RCR_1(Eb);
0x4: SAL_1(Eb);
0x5: SHR_1(Eb);
0x6: SAL_1(Eb);
0x7: SAR_1(Eb);
}
//0x1: group2_Ev_1();
0x1: decode MODRM_REG {
0x0: ROL_1(Ev);
0x1: ROR_1(Ev);
0x2: RCL_1(Ev);
0x3: RCR_1(Ev);
0x4: SAL_1(Ev);
0x5: SHR_1(Ev);
0x6: SAL_1(Ev);
0x7: SAR_1(Ev);
}
//0x2: group2_Eb_Cl();
0x2: decode MODRM_REG {
0x0: ROL(Eb,rCb);
0x1: ROR(Eb,rCb);
0x2: RCL(Eb,rCb);
0x3: RCR(Eb,rCb);
0x4: SAL(Eb,rCb);
0x5: SHR(Eb,rCb);
0x6: SAL(Eb,rCb);
0x7: SAR(Eb,rCb);
}
//The second operand should have size "b", but to have
//consistent register sizes it's "v". This shouldn't have
//any affect on functionality.
//0x3: group2_Ev_Cl();
0x3: decode MODRM_REG {
0x0: ROL(Ev,rCv);
0x1: ROR(Ev,rCv);
0x2: RCL(Ev,rCv);
0x3: RCR(Ev,rCv);
0x4: SAL(Ev,rCv);
0x5: SHR(Ev,rCv);
0x6: SAL(Ev,rCv);
0x7: SAR(Ev,rCv);
}
}
0x4: decode MODE_SUBMODE {
0x0: Inst::UD2();
default: aam_Ib();
@ -465,8 +513,28 @@
{{"Tried to execute the rep/repe prefix!"}});
0x4: hlt();
0x5: cmc();
0x6: group3_Eb();
0x7: group3_Ev();
//0x6: group3_Eb();
0x6: decode MODRM_REG {
0x0: Inst::TEST(Eb,Iz);
0x1: Inst::TEST(Eb,Iz);
0x2: Inst::NOT(Eb);
0x3: Inst::NEG(Eb);
0x4: mul_Eb();
0x5: imul_Eb();
0x6: div_Eb();
0x7: idiv_Eb();
}
//0x7: group3_Ev();
0x7: decode MODRM_REG {
0x0: Inst::TEST(Ev,Iz);
0x1: Inst::TEST(Ev,Iz);
0x2: Inst::NOT(Ev);
0x3: Inst::NEG(Ev);
0x4: mul_Ev();
0x5: imul_Ev();
0x6: div_Ev();
0x7: idiv_Ev();
}
}
0x1F: decode OPCODE_OP_BOTTOM3 {
0x0: clc();

123
src/arch/x86/isa/decoder/two_byte_opcodes.isa
View file

@ -81,13 +81,15 @@
0x0: invd();
0x1: wbinvd();
0x2: Inst::UD2();
0x3: UD2();
0x3: Inst::UD2();
0x4: Inst::UD2();
0x5: threednow();
0x6: threednow();
0x7: threednow();
}
0x02: decode OPCODE_OP_BOTTOM3 {
0x02: decode LEGACY_DECODEVAL {
// no prefix
0x0: decode OPCODE_OP_BOTTOM3 {
0x0: holder();
0x1: holder();
0x2: holder();
@ -97,6 +99,41 @@
0x6: holder();
0x7: holder();
}
// repe (0xF3)
0x4: decode OPCODE_OP_BOTTOM3 {
0x0: holder();
0x1: holder();
0x2: holder();
0x3: holder();
0x4: holder();
0x5: holder();
0x6: holder();
0x7: holder();
}
// operand size (0x66)
0x1: decode OPCODE_OP_BOTTOM3 {
0x0: holder();
0x1: holder();
0x2: holder();
0x3: holder();
0x4: holder();
0x5: holder();
0x6: holder();
0x7: holder();
}
// repne (0xF2)
0x8: decode OPCODE_OP_BOTTOM3 {
0x0: holder();
0x1: holder();
0x2: holder();
0x3: holder();
0x4: holder();
0x5: holder();
0x6: holder();
0x7: holder();
}
default: Inst::UD2();
}
0x03: decode OPCODE_OP_BOTTOM3 {
0x0: group17();
0x1: group17();
@ -147,25 +184,27 @@
0x6: three_byte_opcode();
0x7: three_byte_opcode();
}
format Inst {
0x08: decode OPCODE_OP_BOTTOM3 {
0x0: cmovo_Gv_Ev();
0x1: cmovno_Gv_Ev();
0x2: cmovb_Gv_Ev();
0x3: cmovnb_Gv_Ev();
0x4: cmovz_Gv_Ev();
0x5: cmovnz_Gv_Ev();
0x6: cmovbe_Gv_Ev();
0x7: cmovnbe_Gv_Ev();
0x0: CMOVO(Gv,Ev);
0x1: CMOVNO(Gv,Ev);
0x2: CMOVB(Gv,Ev);
0x3: CMOVNB(Gv,Ev);
0x4: CMOVZ(Gv,Ev);
0x5: CMOVNZ(Gv,Ev);
0x6: CMOVBE(Gv,Ev);
0x7: CMOVNBE(Gv,Ev);
}
0x09: decode OPCODE_OP_BOTTOM3 {
0x0: cmovs_Gv_Ev();
0x1: cmovns_Gv_Ev();
0x2: cmovp_Gv_Ev();
0x3: cmovnp_Gv_Ev();
0x4: cmovl_Gv_Ev();
0x5: cmovnl_Gv_Ev();
0x6: cmovle_Gv_Ev();
0x7: cmovnle_Gv_Ev();
0x0: CMOVS(Gv,Ev);
0x1: CMOVNS(Gv,Ev);
0x2: CMOVP(Gv,Ev);
0x3: CMOVNP(Gv,Ev);
0x4: CMOVL(Gv,Ev);
0x5: CMOVNL(Gv,Ev);
0x6: CMOVLE(Gv,Ev);
0x7: CMOVNLE(Gv,Ev);
}
}
0x0A: decode OPCODE_OP_BOTTOM3 {
0x0: holder();
@ -248,26 +287,26 @@
0x6: JLE(Jz);
0x7: JNLE(Jz);
}
}
0x12: decode OPCODE_OP_BOTTOM3 {
0x0: seto_Eb();
0x1: setno_Eb();
0x2: setb_Eb();
0x3: setnb_Eb();
0x4: setz_Eb();
0x5: setnz_Eb();
0x6: setbe_Eb();
0x7: setnbe_Eb();
0x0: SETO(Eb);
0x1: SETNO(Eb);
0x2: SETB(Eb);
0x3: SETNB(Eb);
0x4: SETZ(Eb);
0x5: SETNZ(Eb);
0x6: SETBE(Eb);
0x7: SETNBE(Eb);
}
0x13: decode OPCODE_OP_BOTTOM3 {
0x0: sets_Eb();
0x1: setns_Eb();
0x2: setp_Eb();
0x3: setnp_Eb();
0x4: setl_Eb();
0x5: setnl_Eb();
0x6: setle_Eb();
0x7: setnle_Eb();
0x0: SETS(Eb);
0x1: SETNS(Eb);
0x2: SETP(Eb);
0x3: SETNP(Eb);
0x4: SETL(Eb);
0x5: SETNL(Eb);
0x6: SETLE(Eb);
0x7: SETNLE(Eb);
}
}
0x14: decode OPCODE_OP_BOTTOM3 {
0x0: push_fs();
@ -296,8 +335,11 @@
0x3: btr_Ev_Gv();
0x4: lfs_Gz_Mp();
0x5: lgs_Gz_Mp();
0x6: Inst::MOVZX_B(Gv,Eb);
0x7: Inst::MOVZX_W(Gv,Ew);
//The size of the second operand in these instructions should
//really be "b" or "w", but it's set to v in order to have a
//consistent register size. This shouldn't affect behavior.
0x6: Inst::MOVZX_B(Gv,Ev);
0x7: Inst::MOVZX_W(Gv,Ev);
}
0x17: decode OPCODE_OP_BOTTOM3 {
0x0: jmpe_Jz(); // IA-64?
@ -306,8 +348,11 @@
0x3: btc_Ev_Gv();
0x4: bsf_Gv_Ev();
0x5: bsr_Gv_Ev();
0x6: Inst::MOVSX_B(Gv,Eb);
0x7: Inst::MOVSX_W(Gv,Ew);
//The size of the second operand in these instructions should
//really be "b" or "w", but it's set to v in order to have a
//consistent register size. This shouldn't affect behavior.
0x6: Inst::MOVSX_B(Gv,Ev);
0x7: Inst::MOVSX_W(Gv,Ev);
}
0x18: decode OPCODE_OP_BOTTOM3 {
0x0: holder();

70
src/arch/x86/isa/insts/arithmetic/add_and_subtract.py
View file

@ -77,9 +77,9 @@ def macroop ADD_P_I
{
rdip t7
limm t2, imm
ld t1, ds, [scale, index, base], disp
ld t1, ds, [0, t0, t7], disp
add t1, t1, t2
st t1, ds, [scale, index, base], disp
st t1, ds, [0, t0, t7], disp
};
def macroop ADD_M_R
@ -92,9 +92,9 @@ def macroop ADD_M_R
def macroop ADD_P_R
{
rdip t7
ld t1, ds, [scale, index, base], disp
ld t1, ds, [0, t0, t7], disp
add t1, t1, reg
st t1, ds, [scale, index, base], disp
st t1, ds, [0, t0, t7], disp
};
def macroop ADD_R_M
@ -106,7 +106,7 @@ def macroop ADD_R_M
def macroop ADD_R_P
{
rdip t7
ld t1, ds, [scale, index, base], disp
ld t1, ds, [0, t0, t7], disp
add reg, reg, t1
};
@ -130,7 +130,7 @@ def macroop SUB_R_M
def macroop SUB_R_P
{
rdip t7
ld t1, ds, [scale, index, base], disp
ld t1, ds, [0, t0, t7], disp
sub reg, reg, t1
};
@ -146,9 +146,9 @@ def macroop SUB_P_I
{
rdip t7
limm t2, imm
ld t1, ds, [scale, index, base], disp
ld t1, ds, [0, t0, t7], disp
sub t1, t1, t2
st t1, ds, [scale, index, base], disp
st t1, ds, [0, t0, t7], disp
};
def macroop SUB_M_R
@ -161,9 +161,9 @@ def macroop SUB_M_R
def macroop SUB_P_R
{
rdip t7
ld t1, ds, [scale, index, base], disp
ld t1, ds, [0, t0, t7], disp
sub t1, t1, reg
st t1, ds, [scale, index, base], disp
st t1, ds, [0, t0, t7], disp
};
def macroop ADC_R_R
@ -189,9 +189,9 @@ def macroop ADC_P_I
{
rdip t7
limm t2, imm
ld t1, ds, [scale, index, base], disp
ld t1, ds, [0, t0, t7], disp
adc t1, t1, t2
st t1, ds, [scale, index, base], disp
st t1, ds, [0, t0, t7], disp
};
def macroop ADC_M_R
@ -204,9 +204,9 @@ def macroop ADC_M_R
def macroop ADC_P_R
{
rdip t7
ld t1, ds, [scale, index, base], disp
ld t1, ds, [0, t0, t7], disp
adc t1, t1, reg
st t1, ds, [scale, index, base], disp
st t1, ds, [0, t0, t7], disp
};
def macroop ADC_R_M
@ -218,7 +218,7 @@ def macroop ADC_R_M
def macroop ADC_R_P
{
rdip t7
ld t1, ds, [scale, index, base], disp
ld t1, ds, [0, t0, t7], disp
adc reg, reg, t1
};
@ -242,7 +242,7 @@ def macroop SBB_R_M
def macroop SBB_R_P
{
rdip t7
ld t1, ds, [scale, index, base], disp
ld t1, ds, [0, t0, t7], disp
sbb reg, reg, t1
};
@ -258,9 +258,9 @@ def macroop SBB_P_I
{
rdip t7
limm t2, imm
ld t1, ds, [scale, index, base], disp
ld t1, ds, [0, t0, t7], disp
sbb t1, t1, t2
st t1, ds, [scale, index, base], disp
st t1, ds, [0, t0, t7], disp
};
def macroop SBB_M_R
@ -273,20 +273,28 @@ def macroop SBB_M_R
def macroop SBB_P_R
{
rdip t7
ld t1, ds, [scale, index, base], disp
ld t1, ds, [0, t0, t7], disp
sbb t1, t1, reg
st t1, ds, [0, t0, t7], disp
};
def macroop NEG_R
{
sub reg, t0, reg, flags=(CF,OF,SF,ZF,AF,PF)
};
def macroop NEG_M
{
ld t1, ds, [scale, index, base], disp
sub t1, t0, t1, flags=(CF,OF,SF,ZF,AF,PF)
st t1, ds, [scale, index, base], disp
};
def macroop NEG_P
{
rdip t7
ld t1, ds, [0, t0, t7], disp
sub t1, t0, t1, flags=(CF,OF,SF,ZF,AF,PF)
st t1, ds, [0, t0, t7], disp
};
'''
#let {{
# class ADC(Inst):
# "Adc ^0 ^0 ^1"
# class ADD(Inst):
# "Add ^0 ^0 ^1"
# class SBB(Inst):
# "Sbb ^0 ^0 ^1"
# class SUB(Inst):
# "Sub ^0 ^0 ^1"
# class NEG(Inst):
# "Sub ^0 $0 ^0"
#}};

6
src/arch/x86/isa/insts/arithmetic/increment_and_decrement.py
View file

@ -94,9 +94,3 @@ def macroop DEC_P
st t1, ds, [0, t0, t7], disp
};
'''
#let {{
# class DEC(Inst):
# "GenFault ${new UnimpInstFault}"
# class INC(Inst):
# "GenFault ${new UnimpInstFault}"
#}};

21
src/arch/x86/isa/insts/arithmetic/multiply_and_divide.py
View file

@ -77,6 +77,27 @@ def macroop IMUL_R_P
ld t1, ds, [scale, index, base], disp
mul1s reg, reg, t1
};
def macroop IMUL_R_R_I
{
limm t1, imm
mul1s reg, regm, t1
};
def macroop IMUL_R_M_I
{
limm t1, imm
ld t2, ds, [scale, index, base], disp
mul1s reg, t2, t1
};
def macroop IMUL_R_P_I
{
rdip t7
limm t1, imm
ld t2, ds, [0, t0, t7]
mul1s reg, t2, t1
};
'''
#let {{
# class MUL(Inst):

342
src/arch/x86/isa/insts/compare_and_test/set_byte_on_condition.py
View file

@ -53,8 +53,340 @@
#
# Authors: Gabe Black
microcode = ""
#let {{
# class SETcc(Inst):
# "GenFault ${new UnimpInstFault}"
#}};
microcode = '''
def macroop SETZ_R
{
movi reg, reg, 1, flags=(CZF,)
movi reg, reg, 0, flags=(nCZF,)
};
def macroop SETZ_M
{
movi t1, t1, 1, flags=(CZF,)
movi t1, t1, 0, flags=(nCZF,)
st t1, ds, [scale, index, base], disp
};
def macroop SETZ_P
{
rdip t7
movi t1, t1, 1, flags=(CZF,)
movi t1, t1, 0, flags=(nCZF,)
st t1, ds, [0, t0, t7], disp
};
def macroop SETNZ_R
{
movi reg, reg, 1, flags=(nCZF,)
movi reg, reg, 0, flags=(CZF,)
};
def macroop SETNZ_M
{
movi t1, t1, 1, flags=(nCZF,)
movi t1, t1, 0, flags=(CZF,)
st t1, ds, [scale, index, base], disp
};
def macroop SETNZ_P
{
rdip t7
movi t1, t1, 1, flags=(nCZF,)
movi t1, t1, 0, flags=(CZF,)
st t1, ds, [0, t0, t7], disp
};
def macroop SETB_R
{
movi reg, reg, 1, flags=(CCF,)
movi reg, reg, 0, flags=(nCCF,)
};
def macroop SETB_M
{
movi t1, t1, 1, flags=(CCF,)
movi t1, t1, 0, flags=(nCCF,)
st t1, ds, [scale, index, base], disp
};
def macroop SETB_P
{
rdip t7
movi t1, t1, 1, flags=(CCF,)
movi t1, t1, 0, flags=(nCCF,)
st t1, ds, [0, t0, t7], disp
};
def macroop SETNB_R
{
movi reg, reg, 1, flags=(nCCF,)
movi reg, reg, 0, flags=(CCF,)
};
def macroop SETNB_M
{
movi t1, t1, 1, flags=(nCCF,)
movi t1, t1, 0, flags=(CCF,)
st t1, ds, [scale, index, base], disp
};
def macroop SETNB_P
{
rdip t7
movi t1, t1, 1, flags=(nCCF,)
movi t1, t1, 0, flags=(CCF,)
st t1, ds, [0, t0, t7], disp
};
def macroop SETBE_R
{
movi reg, reg, 1, flags=(CCvZF,)
movi reg, reg, 0, flags=(nCCvZF,)
};
def macroop SETBE_M
{
movi t1, t1, 1, flags=(CCvZF,)
movi t1, t1, 0, flags=(nCCvZF,)
st t1, ds, [scale, index, base], disp
};
def macroop SETBE_P
{
rdip t7
movi t1, t1, 1, flags=(CCvZF,)
movi t1, t1, 0, flags=(nCCvZF,)
st t1, ds, [0, t0, t7], disp
};
def macroop SETNBE_R
{
movi reg, reg, 1, flags=(nCCvZF,)
movi reg, reg, 0, flags=(CCvZF,)
};
def macroop SETNBE_M
{
movi t1, t1, 1, flags=(nCCvZF,)
movi t1, t1, 0, flags=(CCvZF,)
st t1, ds, [scale, index, base], disp
};
def macroop SETNBE_P
{
rdip t7
movi t1, t1, 1, flags=(nCCvZF,)
movi t1, t1, 0, flags=(CCvZF,)
st t1, ds, [0, t0, t7], disp
};
def macroop SETS_R
{
movi reg, reg, 1, flags=(CSF,)
movi reg, reg, 0, flags=(nCSF,)
};
def macroop SETS_M
{
movi t1, t1, 1, flags=(CSF,)
movi t1, t1, 0, flags=(nCSF,)
st t1, ds, [scale, index, base], disp
};
def macroop SETS_P
{
rdip t7
movi t1, t1, 1, flags=(CSF,)
movi t1, t1, 0, flags=(nCSF,)
st t1, ds, [0, t0, t7], disp
};
def macroop SETNS_R
{
movi reg, reg, 1, flags=(nCSF,)
movi reg, reg, 0, flags=(CSF,)
};
def macroop SETNS_M
{
movi t1, t1, 1, flags=(nCSF,)
movi t1, t1, 0, flags=(CSF,)
st t1, ds, [scale, index, base], disp
};
def macroop SETNS_P
{
rdip t7
movi t1, t1, 1, flags=(nCSF,)
movi t1, t1, 0, flags=(CSF,)
st t1, ds, [0, t0, t7], disp
};
def macroop SETP_R
{
movi reg, reg, 1, flags=(CPF,)
movi reg, reg, 0, flags=(nCPF,)
};
def macroop SETP_M
{
movi t1, t1, 1, flags=(CPF,)
movi t1, t1, 0, flags=(nCPF,)
st t1, ds, [scale, index, base], disp
};
def macroop SETP_P
{
rdip t7
movi t1, t1, 1, flags=(CPF,)
movi t1, t1, 0, flags=(nCPF,)
st t1, ds, [0, t0, t7], disp
};
def macroop SETNP_R
{
movi reg, reg, 1, flags=(nCPF,)
movi reg, reg, 0, flags=(CPF,)
};
def macroop SETNP_M
{
movi t1, t1, 1, flags=(nCPF,)
movi t1, t1, 0, flags=(CPF,)
st t1, ds, [scale, index, base], disp
};
def macroop SETNP_P
{
rdip t7
movi t1, t1, 1, flags=(nCPF,)
movi t1, t1, 0, flags=(CPF,)
st t1, ds, [0, t0, t7], disp
};
def macroop SETL_R
{
movi reg, reg, 1, flags=(CSxOF,)
movi reg, reg, 0, flags=(nCSxOF,)
};
def macroop SETL_M
{
movi t1, t1, 1, flags=(CSxOF,)
movi t1, t1, 0, flags=(nCSxOF,)
st t1, ds, [scale, index, base], disp
};
def macroop SETL_P
{
rdip t7
movi t1, t1, 1, flags=(CSxOF,)
movi t1, t1, 0, flags=(nCSxOF,)
st t1, ds, [0, t0, t7], disp
};
def macroop SETNL_R
{
movi reg, reg, 1, flags=(nCSxOF,)
movi reg, reg, 0, flags=(CSxOF,)
};
def macroop SETNL_M
{
movi t1, t1, 1, flags=(nCSxOF,)
movi t1, t1, 0, flags=(CSxOF,)
st t1, ds, [scale, index, base], disp
};
def macroop SETNL_P
{
rdip t7
movi t1, t1, 1, flags=(nCSxOF,)
movi t1, t1, 0, flags=(CSxOF,)
st t1, ds, [0, t0, t7], disp
};
def macroop SETLE_R
{
movi reg, reg, 1, flags=(CSxOvZF,)
movi reg, reg, 0, flags=(nCSxOvZF,)
};
def macroop SETLE_M
{
movi t1, t1, 1, flags=(CSxOvZF,)
movi t1, t1, 0, flags=(nCSxOvZF,)
st t1, ds, [scale, index, base], disp
};
def macroop SETLE_P
{
rdip t7
movi t1, t1, 1, flags=(CSxOvZF,)
movi t1, t1, 0, flags=(nCSxOvZF,)
st t1, ds, [0, t0, t7], disp
};
def macroop SETNLE_R
{
movi reg, reg, 1, flags=(nCSxOvZF,)
movi reg, reg, 0, flags=(CSxOvZF,)
};
def macroop SETNLE_M
{
movi t1, t1, 1, flags=(nCSxOvZF,)
movi t1, t1, 0, flags=(CSxOvZF,)
st t1, ds, [scale, index, base], disp
};
def macroop SETNLE_P
{
rdip t7
movi t1, t1, 1, flags=(nCSxOvZF,)
movi t1, t1, 0, flags=(CSxOvZF,)
st t1, ds, [0, t0, t7], disp
};
def macroop SETO_R
{
movi reg, reg, 1, flags=(COF,)
movi reg, reg, 0, flags=(nCOF,)
};
def macroop SETO_M
{
movi t1, t1, 1, flags=(COF,)
movi t1, t1, 0, flags=(nCOF,)
st t1, ds, [scale, index, base], disp
};
def macroop SETO_P
{
rdip t7
movi t1, t1, 1, flags=(COF,)
movi t1, t1, 0, flags=(nCOF,)
st t1, ds, [0, t0, t7], disp
};
def macroop SETNO_R
{
movi reg, reg, 1, flags=(nCOF,)
movi reg, reg, 0, flags=(COF,)
};
def macroop SETNO_M
{
movi t1, t1, 1, flags=(nCOF,)
movi t1, t1, 0, flags=(COF,)
st t1, ds, [scale, index, base], disp
};
def macroop SETNO_P
{
rdip t7
movi t1, t1, 1, flags=(nCOF,)
movi t1, t1, 0, flags=(COF,)
st t1, ds, [0, t0, t7], disp
};
'''

13
src/arch/x86/isa/insts/data_conversion/sign_extension.py
View file

@ -53,7 +53,18 @@
#
# Authors: Gabe Black
microcode = ""
microcode = '''
def macroop CDQE_R {
sext reg, reg, "env.dataSize << 2"
};
def macroop CQO_R_R {
# A shift might be slower than, for example, an explicit sign extension,
# so it might be worthwhile to try to find an alternative.
mov regm, regm, reg
sra regm, regm, "env.dataSize * 8 - 1"
};
'''
#let {{
# class CBW(Inst):
# "GenFault ${new UnimpInstFault}"

294
src/arch/x86/isa/insts/data_transfer/conditional_move.py
View file

@ -53,8 +53,292 @@
#
# Authors: Gabe Black
microcode = ""
#let {{
# class CMOVcc(Inst):
# "GenFault ${new UnimpInstFault}"
#}};
microcode = '''
def macroop CMOVZ_R_R
{
mov reg, reg, regm, flags=(CZF,)
};
def macroop CMOVZ_R_M
{
ld t1, ds, [scale, index, base], disp
mov reg, reg, t1, flags=(CZF,)
};
def macroop CMOVZ_R_P
{
rdip t7
ld t1, ds, [0, t0, t7], disp
mov reg, reg, t1, flags=(CZF,)
};
def macroop CMOVNZ_R_R
{
mov reg, reg, regm, flags=(nCZF,)
};
def macroop CMOVNZ_R_M
{
ld t1, ds, [scale, index, base], disp
mov reg, reg, t1, flags=(nCZF,)
};
def macroop CMOVNZ_R_P
{
rdip t7
ld t1, ds, [0, t0, t7], disp
mov reg, reg, t1, flags=(nCZF,)
};
def macroop CMOVB_R_R
{
mov reg, reg, regm, flags=(CCF,)
};
def macroop CMOVB_R_M
{
ld t1, ds, [scale, index, base], disp
mov reg, reg, t1, flags=(CCF,)
};
def macroop CMOVB_R_P
{
rdip t7
ld t1, ds, [0, t0, t7], disp
mov reg, reg, t1, flags=(CCF,)
};
def macroop CMOVNB_R_R
{
mov reg, reg, regm, flags=(nCCF,)
};
def macroop CMOVNB_R_M
{
ld t1, ds, [scale, index, base], disp
mov reg, reg, t1, flags=(nCCF,)
};
def macroop CMOVNB_R_P
{
rdip t7
ld t1, ds, [0, t0, t7], disp
mov reg, reg, t1, flags=(nCCF,)
};
def macroop CMOVBE_R_R
{
mov reg, reg, regm, flags=(CCvZF,)
};
def macroop CMOVBE_R_M
{
ld t1, ds, [scale, index, base], disp
mov reg, reg, t1, flags=(CCvZF,)
};
def macroop CMOVBE_R_P
{
rdip t7
ld t1, ds, [0, t0, t7], disp
mov reg, reg, t1, flags=(CCvZF,)
};
def macroop CMOVNBE_R_R
{
mov reg, reg, regm, flags=(nCCvZF,)
};
def macroop CMOVNBE_R_M
{
ld t1, ds, [scale, index, base], disp
mov reg, reg, t1, flags=(nCCvZF,)
};
def macroop CMOVNBE_R_P
{
rdip t7
ld t1, ds, [0, t0, t7], disp
mov reg, reg, t1, flags=(nCCvZF,)
};
def macroop CMOVS_R_R
{
mov reg, reg, regm, flags=(CSF,)
};
def macroop CMOVS_R_M
{
ld t1, ds, [scale, index, base], disp
mov reg, reg, t1, flags=(CSF,)
};
def macroop CMOVS_R_P
{
rdip t7
ld t1, ds, [0, t0, t7], disp
mov reg, reg, t1, flags=(CSF,)
};
def macroop CMOVNS_R_R
{
mov reg, reg, regm, flags=(nCSF,)
};
def macroop CMOVNS_R_M
{
ld t1, ds, [scale, index, base], disp
mov reg, reg, t1, flags=(nCSF,)
};
def macroop CMOVNS_R_P
{
rdip t7
ld t1, ds, [0, t0, t7], disp
mov reg, reg, t1, flags=(nCSF,)
};
def macroop CMOVP_R_R
{
mov reg, reg, regm, flags=(CPF,)
};
def macroop CMOVP_R_M
{
ld t1, ds, [scale, index, base], disp
mov reg, reg, t1, flags=(CPF,)
};
def macroop CMOVP_R_P
{
rdip t7
ld t1, ds, [0, t0, t7], disp
mov reg, reg, t1, flags=(CPF,)
};
def macroop CMOVNP_R_R
{
mov reg, reg, regm, flags=(nCPF,)
};
def macroop CMOVNP_R_M
{
ld t1, ds, [scale, index, base], disp
mov reg, reg, regm, flags=(nCPF,)
};
def macroop CMOVNP_R_P
{
rdip t7
ld t1, ds, [0, t0, t7], disp
mov reg, reg, regm, flags=(nCPF,)
};
def macroop CMOVL_R_R
{
mov reg, reg, regm, flags=(CSxOF,)
};
def macroop CMOVL_R_M
{
ld t1, ds, [scale, index, base], disp
mov reg, reg, t1, flags=(CSxOF,)
};
def macroop CMOVL_R_P
{
rdip t7
ld t1, ds, [0, t0, t7], disp
mov reg, reg, t1, flags=(CSxOF,)
};
def macroop CMOVNL_R_R
{
mov reg, reg, regm, flags=(nCSxOF,)
};
def macroop CMOVNL_R_M
{
ld t1, ds, [scale, index, base], disp
mov reg, reg, t1, flags=(nCSxOF,)
};
def macroop CMOVNL_R_P
{
rdip t7
ld t1, ds, [0, t0, t7], disp
mov reg, reg, t1, flags=(nCSxOF,)
};
def macroop CMOVLE_R_R
{
mov reg, reg, regm, flags=(CSxOvZF,)
};
def macroop CMOVLE_R_M
{
ld t1, ds, [scale, index, base], disp
mov reg, reg, t1, flags=(CSxOvZF,)
};
def macroop CMOVLE_R_P
{
rdip t7
ld t1, ds, [0, t0, t7], disp
mov reg, reg, t1, flags=(CSxOvZF,)
};
def macroop CMOVNLE_R_R
{
mov reg, reg, regm, flags=(nCSxOvZF,)
};
def macroop CMOVNLE_R_M
{
ld t1, ds, [scale, index, base], disp
mov reg, reg, t1, flags=(nCSxOvZF,)
};
def macroop CMOVNLE_R_P
{
rdip t7
ld t1, ds, [0, t0, t7], disp
mov reg, reg, t1, flags=(nCSxOvZF,)
};
def macroop CMOVO_R_R
{
mov reg, reg, regm, flags=(COF,)
};
def macroop CMOVO_R_M
{
ld t1, ds, [scale, index, base], disp
mov reg, reg, t1, flags=(COF,)
};
def macroop CMOVO_R_P
{
rdip t7
ld t1, ds, [0, t0, t7], disp
mov reg, reg, t1, flags=(COF,)
};
def macroop CMOVNO_R_R
{
mov reg, reg, regm, flags=(nCOF,)
};
def macroop CMOVNO_R_M
{
ld t1, ds, [scale, index, base], disp
mov reg, reg, t1, flags=(nCOF,)
};
def macroop CMOVNO_R_P
{
rdip t7
ld t1, ds, [0, t0, t7], disp
mov reg, reg, t1, flags=(nCOF,)
};
'''

60
src/arch/x86/isa/insts/data_transfer/stack_operations.py
View file

@ -62,6 +62,25 @@ def macroop POP_R {
addi rsp, rsp, dsz
};
def macroop POP_M {
# Make the default data size of pops 64 bits in 64 bit mode
.adjust_env oszIn64Override
ld t1, ss, [0, t0, rsp]
addi rsp, rsp, dsz
st t1, ds, [scale, index, base], disp
};
def macroop POP_P {
# Make the default data size of pops 64 bits in 64 bit mode
.adjust_env oszIn64Override
rdip t7
ld t1, ss, [0, t0, rsp]
addi rsp, rsp, dsz
st t1, ds, [0, t0, t7]
};
def macroop PUSH_R {
# Make the default data size of pops 64 bits in 64 bit mode
.adjust_env oszIn64Override
@ -70,6 +89,15 @@ def macroop PUSH_R {
st reg, ss, [0, t0, rsp]
};
def macroop PUSH_I {
# Make the default data size of pops 64 bits in 64 bit mode
.adjust_env oszIn64Override
limm t1, imm
subi rsp, rsp, dsz
st t1, ss, [0, t0, rsp]
};
def macroop PUSH_M {
# Make the default data size of pops 64 bits in 64 bit mode
.adjust_env oszIn64Override
@ -88,16 +116,32 @@ def macroop PUSH_P {
subi rsp, rsp, dsz
st t1, ss, [0, t0, rsp]
};
def macroop PUSHA {
st rax, ss, [0, t0, rsp], "-0 * env.dataSize"
st rcx, ss, [0, t0, rsp], "-1 * env.dataSize"
st rdx, ss, [0, t0, rsp], "-2 * env.dataSize"
st rbx, ss, [0, t0, rsp], "-3 * env.dataSize"
st rsp, ss, [0, t0, rsp], "-4 * env.dataSize"
st rbp, ss, [0, t0, rsp], "-5 * env.dataSize"
st rsi, ss, [0, t0, rsp], "-6 * env.dataSize"
st rdi, ss, [0, t0, rsp], "-7 * env.dataSize"
subi rsp, rsp, "8 * env.dataSize"
};
def macroop POPA {
st rdi, ss, [0, t0, rsp], "0 * env.dataSize"
st rsi, ss, [0, t0, rsp], "1 * env.dataSize"
st rbp, ss, [0, t0, rsp], "2 * env.dataSize"
st rsp, ss, [0, t0, rsp], "3 * env.dataSize"
st rbx, ss, [0, t0, rsp], "4 * env.dataSize"
st rdx, ss, [0, t0, rsp], "5 * env.dataSize"
st rcx, ss, [0, t0, rsp], "6 * env.dataSize"
st rax, ss, [0, t0, rsp], "7 * env.dataSize"
addi rsp, rsp, "8 * env.dataSize"
};
'''
#let {{
# class POPA(Inst):
# "GenFault ${new UnimpInstFault}"
# class POPAD(Inst):
# "GenFault ${new UnimpInstFault}"
# class PUSHA(Inst):
# "GenFault ${new UnimpInstFault}"
# class PUSHAD(Inst):
# "GenFault ${new UnimpInstFault}"
# class ENTER(Inst):
# "GenFault ${new UnimpInstFault}"
# class LEAVE(Inst):

35
src/arch/x86/isa/insts/logical.py
View file

@ -221,16 +221,27 @@ def macroop AND_P_R
and t1, t1, reg
st t1, ds, [scale, index, base], disp
};
def macroop NOT_R
{
limm t1, -1
xor reg, reg, t1
};
def macroop NOT_M
{
limm t1, -1
ld t2, ds, [scale, index, base], disp
xor t2, t2, t1
st t2, ds, [scale, index, base], disp
};
def macroop NOT_P
{
limm t1, -1
rdip t7
ld t2, ds, [0, t0, t7], disp
xor t2, t2, t1
st t2, ds, [0, t0, t7], disp
};
'''
#let {{
#microcodeString = '''
# def macroop OR
# {
# Or reg reg regm
# };
# def macroop NOT
# {
# Xor reg reg "0xFFFFFFFFFFFFFFFFULL"
# };
#'''
#}};

190
src/arch/x86/isa/insts/rotate_and_shift/rotate.py
View file

@ -56,13 +56,13 @@
microcode = '''
def macroop ROL_R_I
{
rol reg, reg, imm
roli reg, reg, imm
};
def macroop ROL_M_I
{
ld t1, ds, [scale, index, base], disp
rol t1, t1, imm
roli t1, t1, imm
st t1, ds, [scale, index, base], disp
};
@ -70,19 +70,59 @@ def macroop ROL_P_I
{
rdip t7
ld t1, ds, [0, t0, t7], disp
rol t1, t1, imm
roli t1, t1, imm
st t1, ds, [0, t0, t7], disp
};
def macroop ROL_1_R
{
roli reg, reg, 1
};
def macroop ROL_1_M
{
ld t1, ds, [scale, index, base], disp
roli t1, t1, 1
st t1, ds, [scale, index, base], disp
};
def macroop ROL_1_P
{
rdip t7
ld t1, ds, [0, t0, t7], disp
roli t1, t1, 1
st t1, ds, [0, t0, t7], disp
};
def macroop ROL_R_R
{
rol reg, reg, regm
};
def macroop ROL_M_R
{
ld t1, ds, [scale, index, base], disp
rol t1, t1, reg
st t1, ds, [scale, index, base], disp
};
def macroop ROL_P_R
{
rdip t7
ld t1, ds, [0, t0, t7], disp
rol t1, t1, reg
st t1, ds, [0, t0, t7], disp
};
def macroop ROR_R_I
{
ror reg, reg, imm
rori reg, reg, imm
};
def macroop ROR_M_I
{
ld t1, ds, [scale, index, base], disp
ror t1, t1, imm
rori t1, t1, imm
st t1, ds, [scale, index, base], disp
};
@ -90,19 +130,59 @@ def macroop ROR_P_I
{
rdip t7
ld t1, ds, [0, t0, t7], disp
ror t1, t1, imm
rori t1, t1, imm
st t1, ds, [0, t0, t7], disp
};
def macroop ROR_1_R
{
rori reg, reg, 1
};
def macroop ROR_1_M
{
ld t1, ds, [scale, index, base], disp
rori t1, t1, 1
st t1, ds, [scale, index, base], disp
};
def macroop ROR_1_P
{
rdip t7
ld t1, ds, [0, t0, t7], disp
rori t1, t1, 1
st t1, ds, [0, t0, t7], disp
};
def macroop ROR_R_R
{
ror reg, reg, regm
};
def macroop ROR_M_R
{
ld t1, ds, [scale, index, base], disp
ror t1, t1, reg
st t1, ds, [scale, index, base], disp
};
def macroop ROR_P_R
{
rdip t7
ld t1, ds, [0, t0, t7], disp
ror t1, t1, reg
st t1, ds, [0, t0, t7], disp
};
def macroop RCL_R_I
{
rcl reg, reg, imm
rcli reg, reg, imm
};
def macroop RCL_M_I
{
ld t1, ds, [scale, index, base], disp
rcl t1, t1, imm
rcli t1, t1, imm
st t1, ds, [scale, index, base], disp
};
@ -110,19 +190,59 @@ def macroop RCL_P_I
{
rdip t7
ld t1, ds, [0, t0, t7], disp
rcl t1, t1, imm
rcli t1, t1, imm
st t1, ds, [0, t0, t7], disp
};
def macroop RCL_1_R
{
rcli reg, reg, 1
};
def macroop RCL_1_M
{
ld t1, ds, [scale, index, base], disp
rcli t1, t1, 1
st t1, ds, [scale, index, base], disp
};
def macroop RCL_1_P
{
rdip t7
ld t1, ds, [0, t0, t7], disp
rcli t1, t1, 1
st t1, ds, [0, t0, t7], disp
};
def macroop RCL_R_R
{
rcl reg, reg, regm
};
def macroop RCL_M_R
{
ld t1, ds, [scale, index, base], disp
rcl t1, t1, reg
st t1, ds, [scale, index, base], disp
};
def macroop RCL_P_R
{
rdip t7
ld t1, ds, [0, t0, t7], disp
rcl t1, t1, reg
st t1, ds, [0, t0, t7], disp
};
def macroop RCR_R_I
{
rcr reg, reg, imm
rcri reg, reg, imm
};
def macroop RCR_M_I
{
ld t1, ds, [scale, index, base], disp
rcr t1, t1, imm
rcri t1, t1, imm
st t1, ds, [scale, index, base], disp
};
@ -130,13 +250,47 @@ def macroop RCR_P_I
{
rdip t7
ld t1, ds, [0, t0, t7], disp
rcr t1, t1, imm
rcri t1, t1, imm
st t1, ds, [0, t0, t7], disp
};
def macroop RCR_1_R
{
rcri reg, reg, 1
};
def macroop RCR_1_M
{
ld t1, ds, [scale, index, base], disp
rcri t1, t1, 1
st t1, ds, [scale, index, base], disp
};
def macroop RCR_1_P
{
rdip t7
ld t1, ds, [0, t0, t7], disp
rcri t1, t1, 1
st t1, ds, [0, t0, t7], disp
};
def macroop RCR_R_R
{
rcr reg, reg, regm
};
def macroop RCR_M_R
{
ld t1, ds, [scale, index, base], disp
rcr t1, t1, reg
st t1, ds, [scale, index, base], disp
};
def macroop RCR_P_R
{
rdip t7
ld t1, ds, [0, t0, t7], disp
rcr t1, t1, reg
st t1, ds, [0, t0, t7], disp
};
'''
#let {{
# class RCL(Inst):
# "GenFault ${new UnimpInstFault}"
# class RCR(Inst):
# "GenFault ${new UnimpInstFault}"
#}};

152
src/arch/x86/isa/insts/rotate_and_shift/shift.py
View file

@ -56,13 +56,13 @@
microcode = '''
def macroop SAL_R_I
{
sll reg, reg, imm
slli reg, reg, imm
};
def macroop SAL_M_I
{
ld t1, ds, [scale, index, base], disp
sll t1, t1, imm
slli t1, t1, imm
st t1, ds, [scale, index, base], disp
};
@ -70,19 +70,59 @@ def macroop SAL_P_I
{
rdip t7
ld t1, ds, [0, t0, t7], disp
sll t1, t1, imm
slli t1, t1, imm
st t1, ds, [0, t0, t7], disp
};
def macroop SAL_1_R
{
slli reg, reg, 1
};
def macroop SAL_1_M
{
ld t1, ds, [scale, index, base], disp
slli t1, t1, 1
st t1, ds, [scale, index, base], disp
};
def macroop SAL_1_P
{
rdip t7
ld t1, ds, [0, t0, t7], disp
slli t1, t1, 1
st t1, ds, [0, t0, t7], disp
};
def macroop SAL_R_R
{
sll reg, reg, regm
};
def macroop SAL_M_R
{
ld t1, ds, [scale, index, base], disp
sll t1, t1, reg
st t1, ds, [scale, index, base], disp
};
def macroop SAL_P_R
{
rdip t7
ld t1, ds, [0, t0, t7], disp
sll t1, t1, reg
st t1, ds, [0, t0, t7], disp
};
def macroop SHR_R_I
{
srl reg, reg, imm
srli reg, reg, imm
};
def macroop SHR_M_I
{
ld t1, ds, [scale, index, base], disp
srl t1, t1, imm
srli t1, t1, imm
st t1, ds, [scale, index, base], disp
};
@ -90,19 +130,59 @@ def macroop SHR_P_I
{
rdip t7
ld t1, ds, [0, t0, t7], disp
srl t1, t1, imm
srli t1, t1, imm
st t1, ds, [0, t0, t7], disp
};
def macroop SHR_1_R
{
srli reg, reg, 1
};
def macroop SHR_1_M
{
ld t1, ds, [scale, index, base], disp
srli t1, t1, 1
st t1, ds, [scale, index, base], disp
};
def macroop SHR_1_P
{
rdip t7
ld t1, ds, [0, t0, t7], disp
srli t1, t1, 1
st t1, ds, [0, t0, t7], disp
};
def macroop SHR_R_R
{
srl reg, reg, regm
};
def macroop SHR_M_R
{
ld t1, ds, [scale, index, base], disp
srl t1, t1, reg
st t1, ds, [scale, index, base], disp
};
def macroop SHR_P_R
{
rdip t7
ld t1, ds, [0, t0, t7], disp
srl t1, t1, reg
st t1, ds, [0, t0, t7], disp
};
def macroop SAR_R_I
{
sra reg, reg, imm
srai reg, reg, imm
};
def macroop SAR_M_I
{
ld t1, ds, [scale, index, base], disp
sra t1, t1, imm
srai t1, t1, imm
st t1, ds, [scale, index, base], disp
};
@ -110,21 +190,47 @@ def macroop SAR_P_I
{
rdip t7
ld t1, ds, [0, t0, t7], disp
sra t1, t1, imm
srai t1, t1, imm
st t1, ds, [0, t0, t7], disp
};
def macroop SAR_1_R
{
srai reg, reg, 1
};
def macroop SAR_1_M
{
ld t1, ds, [scale, index, base], disp
srai t1, t1, 1
st t1, ds, [scale, index, base], disp
};
def macroop SAR_1_P
{
rdip t7
ld t1, ds, [0, t0, t7], disp
srai t1, t1, 1
st t1, ds, [0, t0, t7], disp
};
def macroop SAR_R_R
{
sra reg, reg, regm
};
def macroop SAR_M_R
{
ld t1, ds, [scale, index, base], disp
sra t1, t1, reg
st t1, ds, [scale, index, base], disp
};
def macroop SAR_P_R
{
rdip t7
ld t1, ds, [0, t0, t7], disp
sra t1, t1, reg
st t1, ds, [0, t0, t7], disp
};
'''
#let {{
# class SAL(Inst):
# "GenFault ${new UnimpInstFault}"
# class SAR(Inst):
# "GenFault ${new UnimpInstFault}"
# class SHL(Inst):
# "GenFault ${new UnimpInstFault}"
# class SHR(Inst):
# "GenFault ${new UnimpInstFault}"
# class SHLD(Inst):
# "GenFault ${new UnimpInstFault}"
# class SHRD(Inst):
# "GenFault ${new UnimpInstFault}"
#}};

23
src/arch/x86/isa/macroop.isa
View file

@ -196,18 +196,34 @@ let {{
self.regUsed = False
self.regm = "0"
self.regmUsed = False
self.size = None
self.addressSize = "ADDRSIZE"
self.dataSize = "OPSIZE"
self.stackSize = "STACKSIZE"
self.doModRM = False
def getAllocator(self):
if self.size == 'b':
self.dataSize = 1
elif self.size == 'd':
self.dataSize = 4
elif self.size == 'q':
self.dataSize = 8
elif self.size == 'v':
self.dataSize = "OPSIZE"
elif self.size == 'w':
self.dataSize = 2
elif self.size == 'z':
self.dataSize = "((OPSIZE == 8) ? 4 : OPSIZE)"
elif self.size:
raise Exception, "Unrecognized size type %s!" % self.size
return '''EmulEnv(%(reg)s,
%(regm)s,
%(dataSize)s,
%(addressSize)s,
%(stackSize)s)''' % \
self.__dict__
def addReg(self, reg):
if not self.regUsed:
self.reg = reg
@ -217,6 +233,13 @@ let {{
self.regmUsed = True
else:
raise Exception, "EmulEnv is out of register specialization spots."
def setSize(self, size):
if not self.size:
self.size = size
else:
if self.size is not size:
raise Exception, "Conflicting register sizes %s and %s!" %\
(self.size, size)
}};
let {{

89
src/arch/x86/isa/microops/ldstop.isa
View file

@ -123,24 +123,9 @@ def template MicroLoadExecute {{
%(ea_code)s;
DPRINTF(X86, "%s : %s: The address is %#x\n", instMnem, mnemonic, EA);
unsigned flags = 0;
switch(dataSize)
{
case 1:
fault = xc->read(EA, (uint8_t&)Mem, flags);
break;
case 2:
fault = xc->read(EA, (uint16_t&)Mem, flags);
break;
case 4:
fault = xc->read(EA, (uint32_t&)Mem, flags);
break;
case 8:
fault = xc->read(EA, (uint64_t&)Mem, flags);
break;
default:
panic("Bad operand size!\n");
}
fault = read(xc, EA, Mem, 0);
int offset = EA & (dataSize - 1);
Mem = bits(Mem, (offset + dataSize) * 8 - 1, offset * 8);
if(fault == NoFault)
{
@ -167,24 +152,8 @@ def template MicroLoadInitiateAcc {{
%(ea_code)s;
DPRINTF(X86, "%s : %s: The address is %#x\n", instMnem, mnemonic, EA);
unsigned flags = 0;
switch(dataSize)
{
case 1:
fault = xc->read(EA, (uint8_t&)Mem, flags);
break;
case 2:
fault = xc->read(EA, (uint16_t&)Mem, flags);
break;
case 4:
fault = xc->read(EA, (uint32_t&)Mem, flags);
break;
case 8:
fault = xc->read(EA, (uint64_t&)Mem, flags);
break;
default:
panic("Bad operand size!\n");
}
int offset = EA & (dataSize - 1);
fault = read(xc, EA, Mem, offset);
return fault;
}
@ -201,6 +170,8 @@ def template MicroLoadCompleteAcc {{
%(op_rd)s;
Mem = pkt->get<typeof(Mem)>();
int offset = pkt->flags;
Mem = bits(Mem, (offset + dataSize) * 8 - 1, offset * 8);
%(code)s;
if(fault == NoFault)
@ -230,30 +201,13 @@ def template MicroStoreExecute {{
if(fault == NoFault)
{
unsigned flags = 0;
uint64_t *res = 0;
switch(dataSize)
{
case 1:
fault = xc->write((uint8_t&)Mem, EA, flags, res);
break;
case 2:
fault = xc->write((uint16_t&)Mem, EA, flags, res);
break;
case 4:
fault = xc->write((uint32_t&)Mem, EA, flags, res);
break;
case 8:
fault = xc->write((uint64_t&)Mem, EA, flags, res);
break;
default:
panic("Bad operand size!\n");
}
}
Mem = Mem << ((EA & (dataSize - 1)) * 8);
fault = write(xc, Mem, EA, 0);
if(fault == NoFault)
{
%(op_wb)s;
}
}
return fault;
}
@ -275,30 +229,13 @@ def template MicroStoreInitiateAcc {{
if(fault == NoFault)
{
unsigned flags = 0;
uint64_t *res = 0;
switch(dataSize)
{
case 1:
fault = xc->write((uint8_t&)Mem, EA, flags, res);
break;
case 2:
fault = xc->write((uint16_t&)Mem, EA, flags, res);
break;
case 4:
fault = xc->write((uint32_t&)Mem, EA, flags, res);
break;
case 8:
fault = xc->write((uint64_t&)Mem, EA, flags, res);
break;
default:
panic("Bad operand size!\n");
}
}
Mem = Mem << ((EA & (dataSize - 1)) * 8);
fault = write(xc, Mem, EA, 0);
if(fault == NoFault)
{
%(op_wb)s;
}
}
return fault;
}
}};

16
src/arch/x86/isa/microops/regop.isa
View file

@ -343,7 +343,7 @@ let {{
immCode = matcher.sub("imm8", code)
if subtract:
secondSrc = "-op2, true"
secondSrc = "~op2, true"
else:
secondSrc = "op2"
@ -466,11 +466,11 @@ let {{
# Shift instructions
defineMicroRegOp('Sll', '''
uint8_t shiftAmt = (op2 & ((dataSize == 8) ? mask(4) : mask(3)));
uint8_t shiftAmt = (op2 & ((dataSize == 8) ? mask(6) : mask(5)));
DestReg = merge(DestReg, SrcReg1 << shiftAmt, dataSize);
''')
defineMicroRegOp('Srl', '''
uint8_t shiftAmt = (op2 & ((dataSize == 8) ? mask(4) : mask(3)));
uint8_t shiftAmt = (op2 & ((dataSize == 8) ? mask(6) : mask(5)));
// Because what happens to the bits shift -in- on a right shift
// is not defined in the C/C++ standard, we have to mask them out
// to be sure they're zero.
@ -478,7 +478,7 @@ let {{
DestReg = merge(DestReg, (SrcReg1 >> shiftAmt) & logicalMask, dataSize);
''')
defineMicroRegOp('Sra', '''
uint8_t shiftAmt = (op2 & ((dataSize == 8) ? mask(4) : mask(3)));
uint8_t shiftAmt = (op2 & ((dataSize == 8) ? mask(6) : mask(5)));
// Because what happens to the bits shift -in- on a right shift
// is not defined in the C/C++ standard, we have to sign extend
// them manually to be sure.
@ -488,7 +488,7 @@ let {{
''')
defineMicroRegOp('Ror', '''
uint8_t shiftAmt =
(op2 & ((dataSize == 8) ? mask(4) : mask(3)));
(op2 & ((dataSize == 8) ? mask(6) : mask(5)));
if(shiftAmt)
{
uint64_t top = SrcReg1 << (dataSize * 8 - shiftAmt);
@ -500,7 +500,7 @@ let {{
''')
defineMicroRegOp('Rcr', '''
uint8_t shiftAmt =
(op2 & ((dataSize == 8) ? mask(4) : mask(3)));
(op2 & ((dataSize == 8) ? mask(6) : mask(5)));
if(shiftAmt)
{
CCFlagBits flags = ccFlagBits;
@ -515,7 +515,7 @@ let {{
''')
defineMicroRegOp('Rol', '''
uint8_t shiftAmt =
(op2 & ((dataSize == 8) ? mask(4) : mask(3)));
(op2 & ((dataSize == 8) ? mask(6) : mask(5)));
if(shiftAmt)
{
uint64_t top = SrcReg1 << shiftAmt;
@ -528,7 +528,7 @@ let {{
''')
defineMicroRegOp('Rcl', '''
uint8_t shiftAmt =
(op2 & ((dataSize == 8) ? mask(4) : mask(3)));
(op2 & ((dataSize == 8) ? mask(6) : mask(5)));
if(shiftAmt)
{
CCFlagBits flags = ccFlagBits;

14
src/arch/x86/isa/specialize.isa
View file

@ -114,7 +114,8 @@ let {{
self.reg = match.group("reg")
self.tag = match.group("tag")
self.size = match.group("size")
self.rsize = match.group("rsize")
if not self.size:
self.size = match.group("rsize")
ModRMRegIndex = "(MODRM_REG | (REX_R << 3))"
ModRMRMIndex = "(MODRM_RM | (REX_B << 3))"
@ -129,6 +130,10 @@ let {{
opType = OpType(opTypes[0])
opTypes.pop(0)
if opType.tag not in ("I", "J"):
if opType.size:
env.setSize(opType.size)
if opType.reg:
#Figure out what to do with fixed register operands
#This is the index to use, so we should stick it some place.
@ -136,13 +141,6 @@ let {{
env.addReg("INTREG_R%sX | (REX_B << 3)" % opType.reg)
else:
env.addReg("INTREG_R%s | (REX_B << 3)" % opType.reg)
if opType.size:
if opType.rsize in ("l", "h", "b"):
print "byte"
elif opType.rsize == "x":
print "word"
else:
print "Didn't recognize fixed register size %s!" % opType.rsize
Name += "_R"
elif opType.tag == "B":
# This refers to registers whose index is encoded as part of the opcode

17
src/arch/x86/isa_traits.hh
View file

@ -99,12 +99,17 @@ namespace X86ISA
const int ReturnAddressReg = 0;
const int ReturnValueReg = INTREG_RAX;
const int FramePointerReg = INTREG_RBP;
const int ArgumentReg0 = INTREG_RDI;
const int ArgumentReg1 = INTREG_RSI;
const int ArgumentReg2 = INTREG_RDX;
const int ArgumentReg3 = INTREG_RCX;
const int ArgumentReg4 = INTREG_R8W;
const int ArgumentReg5 = INTREG_R9W;
const int ArgumentReg[] = {
INTREG_RDI,
INTREG_RSI,
INTREG_RDX,
//This argument register is r10 for syscalls and rcx for C.
INTREG_R10W,
//INTREG_RCX,
INTREG_R8W,
INTREG_R9W
};
const int NumArgumentRegs = sizeof(ArgumentReg) / sizeof(const int);
// Some OS syscalls use a second register (rdx) to return a second
// value

7
src/arch/x86/linux/linux.cc
View file

@ -59,7 +59,7 @@
#include <fcntl.h>
// open(2) flags translation table
OpenFlagTransTable X86Linux::openFlagTable[] = {
OpenFlagTransTable X86Linux64::openFlagTable[] = {
#ifdef _MSC_VER
{ TGT_O_RDONLY, _O_RDONLY },
{ TGT_O_WRONLY, _O_WRONLY },
@ -93,6 +93,7 @@ OpenFlagTransTable X86Linux::openFlagTable[] = {
#endif /* _MSC_VER */
};
const int X86Linux::NUM_OPEN_FLAGS =
(sizeof(X86Linux::openFlagTable)/sizeof(X86Linux::openFlagTable[0]));
const int X86Linux64::NUM_OPEN_FLAGS =
sizeof(X86Linux64::openFlagTable) /
sizeof(X86Linux64::openFlagTable[0]);

7
src/arch/x86/linux/linux.hh
View file

@ -60,7 +60,7 @@
#include "kern/linux/linux.hh"
class X86Linux : public Linux
class X86Linux64 : public Linux
{
public:
@ -104,6 +104,11 @@ class X86Linux : public Linux
static const int NUM_OPEN_FLAGS;
static const unsigned TGT_MAP_ANONYMOUS = 0x20;
typedef struct {
uint64_t iov_base; // void *
uint64_t iov_len; // size_t
} tgt_iovec;
};
#endif

16
src/arch/x86/linux/syscalls.cc
View file

@ -83,17 +83,17 @@ unameFunc(SyscallDesc *desc, int callnum, LiveProcess *process,
SyscallDesc X86LinuxProcess::syscallDescs[] = {
/* 0 */ SyscallDesc("read", unimplementedFunc),
/* 1 */ SyscallDesc("write", unimplementedFunc),
/* 2 */ SyscallDesc("open", openFunc<X86Linux>),
/* 2 */ SyscallDesc("open", openFunc<X86Linux64>),
/* 3 */ SyscallDesc("close", unimplementedFunc),
/* 4 */ SyscallDesc("stat", unimplementedFunc),
/* 5 */ SyscallDesc("fstat", unimplementedFunc),
/* 6 */ SyscallDesc("lstat", unimplementedFunc),
/* 7 */ SyscallDesc("poll", unimplementedFunc),
/* 8 */ SyscallDesc("lseek", unimplementedFunc),
/* 9 */ SyscallDesc("mmap", unimplementedFunc),
/* 9 */ SyscallDesc("mmap", mmapFunc<X86Linux64>),
/* 10 */ SyscallDesc("mprotect", unimplementedFunc),
/* 11 */ SyscallDesc("munmap", unimplementedFunc),
/* 12 */ SyscallDesc("brk", unimplementedFunc),
/* 12 */ SyscallDesc("brk", obreakFunc),
/* 13 */ SyscallDesc("rt_sigaction", unimplementedFunc),
/* 14 */ SyscallDesc("rt_sigprocmask", unimplementedFunc),
/* 15 */ SyscallDesc("rt_sigreturn", unimplementedFunc),
@ -101,7 +101,7 @@ SyscallDesc X86LinuxProcess::syscallDescs[] = {
/* 17 */ SyscallDesc("pread64", unimplementedFunc),
/* 18 */ SyscallDesc("pwrite64", unimplementedFunc),
/* 19 */ SyscallDesc("readv", unimplementedFunc),
/* 20 */ SyscallDesc("writev", unimplementedFunc),
/* 20 */ SyscallDesc("writev", writevFunc<X86Linux64>),
/* 21 */ SyscallDesc("access", unimplementedFunc),
/* 22 */ SyscallDesc("pipe", unimplementedFunc),
/* 23 */ SyscallDesc("select", unimplementedFunc),
@ -183,13 +183,13 @@ SyscallDesc X86LinuxProcess::syscallDescs[] = {
/* 99 */ SyscallDesc("sysinfo", unimplementedFunc),
/* 100 */ SyscallDesc("times", unimplementedFunc),
/* 101 */ SyscallDesc("ptrace", unimplementedFunc),
/* 102 */ SyscallDesc("getuid", unimplementedFunc),
/* 102 */ SyscallDesc("getuid", getuidFunc),
/* 103 */ SyscallDesc("syslog", unimplementedFunc),
/* 104 */ SyscallDesc("getgid", unimplementedFunc),
/* 104 */ SyscallDesc("getgid", getgidFunc),
/* 105 */ SyscallDesc("setuid", unimplementedFunc),
/* 106 */ SyscallDesc("setgid", unimplementedFunc),
/* 107 */ SyscallDesc("geteuid", unimplementedFunc),
/* 108 */ SyscallDesc("getegid", unimplementedFunc),
/* 107 */ SyscallDesc("geteuid", geteuidFunc),
/* 108 */ SyscallDesc("getegid", getegidFunc),
/* 109 */ SyscallDesc("setpgid", unimplementedFunc),
/* 110 */ SyscallDesc("getppid", unimplementedFunc),
/* 111 */ SyscallDesc("getpgrp", unimplementedFunc),

10
src/arch/x86/predecoder.cc
View file

@ -311,6 +311,16 @@ namespace X86ISA
else
displacementSize = 0;
}
// The "test" instruction in group 3 needs an immediate, even though
// the other instructions with the same actual opcode don't.
if (emi.opcode.num == 1 && (modRM.reg & 0x6) == 0) {
if (emi.opcode.op == 0xF6)
immediateSize = 1;
else if (emi.opcode.op == 0xF7)
immediateSize = (emi.opSize == 8) ? 4 : emi.opSize;
}
//If there's an SIB, get that next.
//There is no SIB in 16 bit mode.
if (modRM.rm == 4 && modRM.mod != 3) {

2
src/arch/x86/predecoder_tables.cc
View file

@ -208,7 +208,7 @@ namespace X86ISA
/* 4 */ 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 ,
/* 5 */ 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 ,
/* 6 */ 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 ,
/* 7 */ BY, 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 ,
/* 7 */ BY, BY, BY, BY, 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 ,
/* 8 */ ZW, ZW, ZW, ZW, ZW, ZW, ZW, ZW, ZW, ZW, ZW, ZW, ZW, ZW, ZW, ZW,
/* 9 */ 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 , 0 ,
/* A */ 0 , 0 , 0 , 0 , BY, 0 , 0 , 0 , 0 , 0 , 0 , 0 , BY, 0 , 0 , 0 ,

5
src/arch/x86/process.cc
View file

@ -338,8 +338,9 @@ X86LiveProcess::argsInit(int intSize, int pageSize)
initVirtMem->writeBlob(argc_base, (uint8_t*)&guestArgc, intSize);
//Set up the thread context to start running the process
threadContexts[0]->setIntReg(ArgumentReg0, argc);
threadContexts[0]->setIntReg(ArgumentReg1, argv_array_base);
assert(NumArgumentRegs >= 2);
threadContexts[0]->setIntReg(ArgumentReg[0], argc);
threadContexts[0]->setIntReg(ArgumentReg[1], argv_array_base);
threadContexts[0]->setIntReg(StackPointerReg, stack_min);
Addr prog_entry = objFile->entryPoint();

1
src/cpu/SConscript
View file

@ -111,7 +111,6 @@ Source('base.cc')
Source('cpuevent.cc')
Source('exetrace.cc')
Source('func_unit.cc')
Source('op_class.cc')
Source('pc_event.cc')
Source('quiesce_event.cc')
Source('static_inst.cc')

4
src/cpu/base.cc
View file

@ -42,7 +42,6 @@
#include "cpu/thread_context.hh"
#include "cpu/profile.hh"
#include "sim/sim_exit.hh"
#include "sim/param.hh"
#include "sim/process.hh"
#include "sim/sim_events.hh"
#include "sim/system.hh"
@ -455,6 +454,3 @@ BaseCPU::traceFunctionsInternal(Addr pc)
functionEntryTick = curTick;
}
}
DEFINE_SIM_OBJECT_CLASS_NAME("BaseCPU", BaseCPU)

4
src/cpu/exetrace.cc
View file

@ -46,7 +46,7 @@
#include "cpu/base.hh"
#include "cpu/exetrace.hh"
#include "cpu/static_inst.hh"
#include "sim/param.hh"
#include "enums/OpClass.hh"
#include "sim/system.hh"
#if FULL_SYSTEM
@ -355,7 +355,7 @@ Trace::InstRecord::dump()
outs << " : ";
if (IsOn(ExecOpClass)) {
outs << opClassStrings[staticInst->opClass()] << " : ";
outs << Enums::OpClassStrings[staticInst->opClass()] << " : ";
}
if (IsOn(ExecResult) && data_status != DataInvalid) {

54
src/cpu/func_unit.cc
View file

@ -32,7 +32,8 @@
#include "base/misc.hh"
#include "cpu/func_unit.hh"
#include "sim/builder.hh"
#include "params/OpDesc.hh"
#include "params/FUDesc.hh"
using namespace std;
@ -116,56 +117,17 @@ FuncUnit::issueLatency(OpClass capability)
//
// The operation-class description object
//
BEGIN_DECLARE_SIM_OBJECT_PARAMS(OpDesc)
SimpleEnumParam<OpClass> opClass;
Param<unsigned> opLat;
Param<unsigned> issueLat;
END_DECLARE_SIM_OBJECT_PARAMS(OpDesc)
BEGIN_INIT_SIM_OBJECT_PARAMS(OpDesc)
INIT_ENUM_PARAM(opClass, "type of operation", opClassStrings),
INIT_PARAM(opLat, "cycles until result is available"),
INIT_PARAM(issueLat, "cycles until another can be issued")
END_INIT_SIM_OBJECT_PARAMS(OpDesc)
CREATE_SIM_OBJECT(OpDesc)
OpDesc *
OpDescParams::create()
{
return new OpDesc(getInstanceName(), opClass, opLat, issueLat);
return new OpDesc(name, opClass, opLat, issueLat);
}
REGISTER_SIM_OBJECT("OpDesc", OpDesc)
//
// The FuDesc object
//
BEGIN_DECLARE_SIM_OBJECT_PARAMS(FUDesc)
SimObjectVectorParam<OpDesc *> opList;
Param<unsigned> count;
END_DECLARE_SIM_OBJECT_PARAMS(FUDesc)
BEGIN_INIT_SIM_OBJECT_PARAMS(FUDesc)
INIT_PARAM(opList, "list of operation classes for this FU type"),
INIT_PARAM(count, "number of these FU's available")
END_INIT_SIM_OBJECT_PARAMS(FUDesc)
CREATE_SIM_OBJECT(FUDesc)
FUDesc *
FUDescParams::create()
{
return new FUDesc(getInstanceName(), opList, count);
return new FUDesc(name, opList, count);
}
REGISTER_SIM_OBJECT("FUDesc", FUDesc)

21
src/cpu/intr_control.cc
View file

@ -35,7 +35,7 @@
#include "cpu/base.hh"
#include "cpu/thread_context.hh"
#include "cpu/intr_control.hh"
#include "sim/builder.hh"
#include "params/IntrControl.hh"
#include "sim/sim_object.hh"
using namespace std;
@ -76,21 +76,8 @@ IntrControl::clear(int cpu_id, int int_num, int index)
temp->clear_interrupt(int_num, index);
}
BEGIN_DECLARE_SIM_OBJECT_PARAMS(IntrControl)
SimObjectParam<System *> sys;
END_DECLARE_SIM_OBJECT_PARAMS(IntrControl)
BEGIN_INIT_SIM_OBJECT_PARAMS(IntrControl)
INIT_PARAM(sys, "the system we are part of")
END_INIT_SIM_OBJECT_PARAMS(IntrControl)
CREATE_SIM_OBJECT(IntrControl)
IntrControl *
IntrControlParams::create()
{
return new IntrControl(getInstanceName(), sys);
return new IntrControl(name, sys);
}
REGISTER_SIM_OBJECT("IntrControl", IntrControl)

54
src/cpu/memtest/memtest.cc
View file

@ -46,7 +46,7 @@
#include "mem/packet.hh"
//#include "mem/physical.hh"
#include "mem/request.hh"
#include "sim/builder.hh"
#include "params/MemTest.hh"
#include "sim/sim_events.hh"
#include "sim/stats.hh"
@ -410,53 +410,15 @@ MemTest::doRetry()
}
}
BEGIN_DECLARE_SIM_OBJECT_PARAMS(MemTest)
// SimObjectParam<BaseCache *> cache;
// SimObjectParam<PhysicalMemory *> main_mem;
// SimObjectParam<PhysicalMemory *> check_mem;
Param<unsigned> memory_size;
Param<unsigned> percent_reads;
Param<unsigned> percent_functional;
Param<unsigned> percent_uncacheable;
Param<unsigned> progress_interval;
Param<unsigned> percent_source_unaligned;
Param<unsigned> percent_dest_unaligned;
Param<Addr> trace_addr;
Param<Counter> max_loads;
Param<bool> atomic;
END_DECLARE_SIM_OBJECT_PARAMS(MemTest)
BEGIN_INIT_SIM_OBJECT_PARAMS(MemTest)
// INIT_PARAM(cache, "L1 cache"),
// INIT_PARAM(main_mem, "hierarchical memory"),
// INIT_PARAM(check_mem, "check memory"),
INIT_PARAM(memory_size, "memory size"),
INIT_PARAM(percent_reads, "target read percentage"),
INIT_PARAM(percent_functional, "percentage of access that are functional"),
INIT_PARAM(percent_uncacheable, "target uncacheable percentage"),
INIT_PARAM(progress_interval, "progress report interval (in accesses)"),
INIT_PARAM(percent_source_unaligned,
"percent of copy source address that are unaligned"),
INIT_PARAM(percent_dest_unaligned,
"percent of copy dest address that are unaligned"),
INIT_PARAM(trace_addr, "address to trace"),
INIT_PARAM(max_loads, "terminate when we have reached this load count"),
INIT_PARAM(atomic, "Is the tester testing atomic mode (or timing)")
END_INIT_SIM_OBJECT_PARAMS(MemTest)
CREATE_SIM_OBJECT(MemTest)
MemTest *
MemTestParams::create()
{
return new MemTest(getInstanceName(), /*cache->getInterface(),*/ /*main_mem,*/
/*check_mem,*/ memory_size, percent_reads, percent_functional,
return new MemTest(name,
#if 0
cache->getInterface(), main_mem, check_mem,
#endif
memory_size, percent_reads, percent_functional,
percent_uncacheable, progress_interval,
percent_source_unaligned, percent_dest_unaligned,
trace_addr, max_loads, atomic);
}
REGISTER_SIM_OBJECT("MemTest", MemTest)

254
src/cpu/o3/alpha/cpu_builder.cc
View file

@ -30,12 +30,13 @@
#include <string>
#include "config/use_checker.hh"
#include "cpu/base.hh"
#include "cpu/o3/alpha/cpu.hh"
#include "cpu/o3/alpha/impl.hh"
#include "cpu/o3/alpha/params.hh"
#include "cpu/o3/fu_pool.hh"
#include "sim/builder.hh"
#include "params/DerivO3CPU.hh"
class DerivO3CPU : public AlphaO3CPU<AlphaSimpleImpl>
{
@ -45,245 +46,8 @@ class DerivO3CPU : public AlphaO3CPU<AlphaSimpleImpl>
{ }
};
BEGIN_DECLARE_SIM_OBJECT_PARAMS(DerivO3CPU)
Param<int> clock;
Param<int> phase;
Param<int> numThreads;
Param<int> cpu_id;
Param<int> activity;
#if FULL_SYSTEM
SimObjectParam<System *> system;
SimObjectParam<AlphaISA::ITB *> itb;
SimObjectParam<AlphaISA::DTB *> dtb;
Param<Tick> profile;
Param<bool> do_quiesce;
Param<bool> do_checkpoint_insts;
Param<bool> do_statistics_insts;
#else
SimObjectVectorParam<Process *> workload;
#endif // FULL_SYSTEM
SimObjectParam<BaseCPU *> checker;
Param<Counter> max_insts_any_thread;
Param<Counter> max_insts_all_threads;
Param<Counter> max_loads_any_thread;
Param<Counter> max_loads_all_threads;
Param<Tick> progress_interval;
Param<unsigned> cachePorts;
Param<unsigned> decodeToFetchDelay;
Param<unsigned> renameToFetchDelay;
Param<unsigned> iewToFetchDelay;
Param<unsigned> commitToFetchDelay;
Param<unsigned> fetchWidth;
Param<unsigned> renameToDecodeDelay;
Param<unsigned> iewToDecodeDelay;
Param<unsigned> commitToDecodeDelay;
Param<unsigned> fetchToDecodeDelay;
Param<unsigned> decodeWidth;
Param<unsigned> iewToRenameDelay;
Param<unsigned> commitToRenameDelay;
Param<unsigned> decodeToRenameDelay;
Param<unsigned> renameWidth;
Param<unsigned> commitToIEWDelay;
Param<unsigned> renameToIEWDelay;
Param<unsigned> issueToExecuteDelay;
Param<unsigned> dispatchWidth;
Param<unsigned> issueWidth;
Param<unsigned> wbWidth;
Param<unsigned> wbDepth;
SimObjectParam<FUPool *> fuPool;
Param<unsigned> iewToCommitDelay;
Param<unsigned> renameToROBDelay;
Param<unsigned> commitWidth;
Param<unsigned> squashWidth;
Param<Tick> trapLatency;
Param<unsigned> backComSize;
Param<unsigned> forwardComSize;
Param<std::string> predType;
Param<unsigned> localPredictorSize;
Param<unsigned> localCtrBits;
Param<unsigned> localHistoryTableSize;
Param<unsigned> localHistoryBits;
Param<unsigned> globalPredictorSize;
Param<unsigned> globalCtrBits;
Param<unsigned> globalHistoryBits;
Param<unsigned> choicePredictorSize;
Param<unsigned> choiceCtrBits;
Param<unsigned> BTBEntries;
Param<unsigned> BTBTagSize;
Param<unsigned> RASSize;
Param<unsigned> LQEntries;
Param<unsigned> SQEntries;
Param<unsigned> LFSTSize;
Param<unsigned> SSITSize;
Param<unsigned> numPhysIntRegs;
Param<unsigned> numPhysFloatRegs;
Param<unsigned> numIQEntries;
Param<unsigned> numROBEntries;
Param<unsigned> smtNumFetchingThreads;
Param<std::string> smtFetchPolicy;
Param<std::string> smtLSQPolicy;
Param<unsigned> smtLSQThreshold;
Param<std::string> smtIQPolicy;
Param<unsigned> smtIQThreshold;
Param<std::string> smtROBPolicy;
Param<unsigned> smtROBThreshold;
Param<std::string> smtCommitPolicy;
Param<unsigned> instShiftAmt;
Param<bool> defer_registration;
Param<bool> function_trace;
Param<Tick> function_trace_start;
END_DECLARE_SIM_OBJECT_PARAMS(DerivO3CPU)
BEGIN_INIT_SIM_OBJECT_PARAMS(DerivO3CPU)
INIT_PARAM(clock, "clock speed"),
INIT_PARAM_DFLT(phase, "clock phase", 0),
INIT_PARAM(numThreads, "number of HW thread contexts"),
INIT_PARAM(cpu_id, "processor ID"),
INIT_PARAM_DFLT(activity, "Initial activity count", 0),
#if FULL_SYSTEM
INIT_PARAM(system, "System object"),
INIT_PARAM(itb, "Instruction translation buffer"),
INIT_PARAM(dtb, "Data translation buffer"),
INIT_PARAM(profile, ""),
INIT_PARAM(do_quiesce, ""),
INIT_PARAM(do_checkpoint_insts, ""),
INIT_PARAM(do_statistics_insts, ""),
#else
INIT_PARAM(workload, "Processes to run"),
#endif // FULL_SYSTEM
INIT_PARAM_DFLT(checker, "Checker CPU", NULL),
INIT_PARAM_DFLT(max_insts_any_thread,
"Terminate when any thread reaches this inst count",
0),
INIT_PARAM_DFLT(max_insts_all_threads,
"Terminate when all threads have reached"
"this inst count",
0),
INIT_PARAM_DFLT(max_loads_any_thread,
"Terminate when any thread reaches this load count",
0),
INIT_PARAM_DFLT(max_loads_all_threads,
"Terminate when all threads have reached this load"
"count",
0),
INIT_PARAM_DFLT(progress_interval, "Progress interval", 0),
INIT_PARAM_DFLT(cachePorts, "Cache Ports", 200),
INIT_PARAM(decodeToFetchDelay, "Decode to fetch delay"),
INIT_PARAM(renameToFetchDelay, "Rename to fetch delay"),
INIT_PARAM(iewToFetchDelay, "Issue/Execute/Writeback to fetch"
"delay"),
INIT_PARAM(commitToFetchDelay, "Commit to fetch delay"),
INIT_PARAM(fetchWidth, "Fetch width"),
INIT_PARAM(renameToDecodeDelay, "Rename to decode delay"),
INIT_PARAM(iewToDecodeDelay, "Issue/Execute/Writeback to decode"
"delay"),
INIT_PARAM(commitToDecodeDelay, "Commit to decode delay"),
INIT_PARAM(fetchToDecodeDelay, "Fetch to decode delay"),
INIT_PARAM(decodeWidth, "Decode width"),
INIT_PARAM(iewToRenameDelay, "Issue/Execute/Writeback to rename"
"delay"),
INIT_PARAM(commitToRenameDelay, "Commit to rename delay"),
INIT_PARAM(decodeToRenameDelay, "Decode to rename delay"),
INIT_PARAM(renameWidth, "Rename width"),
INIT_PARAM(commitToIEWDelay, "Commit to "
"Issue/Execute/Writeback delay"),
INIT_PARAM(renameToIEWDelay, "Rename to "
"Issue/Execute/Writeback delay"),
INIT_PARAM(issueToExecuteDelay, "Issue to execute delay (internal"
"to the IEW stage)"),
INIT_PARAM(dispatchWidth, "Dispatch width"),
INIT_PARAM(issueWidth, "Issue width"),
INIT_PARAM(wbWidth, "Writeback width"),
INIT_PARAM(wbDepth, "Writeback depth (number of cycles it can buffer)"),
INIT_PARAM_DFLT(fuPool, "Functional unit pool", NULL),
INIT_PARAM(iewToCommitDelay, "Issue/Execute/Writeback to commit "
"delay"),
INIT_PARAM(renameToROBDelay, "Rename to reorder buffer delay"),
INIT_PARAM(commitWidth, "Commit width"),
INIT_PARAM(squashWidth, "Squash width"),
INIT_PARAM_DFLT(trapLatency, "Number of cycles before the trap is handled", 6),
INIT_PARAM(backComSize, "Time buffer size for backwards communication"),
INIT_PARAM(forwardComSize, "Time buffer size for forward communication"),
INIT_PARAM(predType, "Type of branch predictor ('local', 'tournament')"),
INIT_PARAM(localPredictorSize, "Size of local predictor"),
INIT_PARAM(localCtrBits, "Bits per counter"),
INIT_PARAM(localHistoryTableSize, "Size of local history table"),
INIT_PARAM(localHistoryBits, "Bits for the local history"),
INIT_PARAM(globalPredictorSize, "Size of global predictor"),
INIT_PARAM(globalCtrBits, "Bits per counter"),
INIT_PARAM(globalHistoryBits, "Bits of history"),
INIT_PARAM(choicePredictorSize, "Size of choice predictor"),
INIT_PARAM(choiceCtrBits, "Bits of choice counters"),
INIT_PARAM(BTBEntries, "Number of BTB entries"),
INIT_PARAM(BTBTagSize, "Size of the BTB tags, in bits"),
INIT_PARAM(RASSize, "RAS size"),
INIT_PARAM(LQEntries, "Number of load queue entries"),
INIT_PARAM(SQEntries, "Number of store queue entries"),
INIT_PARAM(LFSTSize, "Last fetched store table size"),
INIT_PARAM(SSITSize, "Store set ID table size"),
INIT_PARAM(numPhysIntRegs, "Number of physical integer registers"),
INIT_PARAM(numPhysFloatRegs, "Number of physical floating point "
"registers"),
INIT_PARAM(numIQEntries, "Number of instruction queue entries"),
INIT_PARAM(numROBEntries, "Number of reorder buffer entries"),
INIT_PARAM_DFLT(smtNumFetchingThreads, "SMT Number of Fetching Threads", 1),
INIT_PARAM_DFLT(smtFetchPolicy, "SMT Fetch Policy", "SingleThread"),
INIT_PARAM_DFLT(smtLSQPolicy, "SMT LSQ Sharing Policy", "Partitioned"),
INIT_PARAM_DFLT(smtLSQThreshold,"SMT LSQ Threshold", 100),
INIT_PARAM_DFLT(smtIQPolicy, "SMT IQ Policy", "Partitioned"),
INIT_PARAM_DFLT(smtIQThreshold, "SMT IQ Threshold", 100),
INIT_PARAM_DFLT(smtROBPolicy, "SMT ROB Sharing Policy", "Partitioned"),
INIT_PARAM_DFLT(smtROBThreshold,"SMT ROB Threshold", 100),
INIT_PARAM_DFLT(smtCommitPolicy,"SMT Commit Fetch Policy", "RoundRobin"),
INIT_PARAM(instShiftAmt, "Number of bits to shift instructions by"),
INIT_PARAM(defer_registration, "defer system registration (for sampling)"),
INIT_PARAM(function_trace, "Enable function trace"),
INIT_PARAM(function_trace_start, "Cycle to start function trace")
END_INIT_SIM_OBJECT_PARAMS(DerivO3CPU)
CREATE_SIM_OBJECT(DerivO3CPU)
DerivO3CPU *
DerivO3CPUParams::create()
{
DerivO3CPU *cpu;
@ -294,8 +58,7 @@ CREATE_SIM_OBJECT(DerivO3CPU)
// In non-full-system mode, we infer the number of threads from
// the workload if it's not explicitly specified.
int actual_num_threads =
(numThreads.isValid() && numThreads >= workload.size()) ?
numThreads : workload.size();
(numThreads >= workload.size()) ? numThreads : workload.size();
if (workload.size() == 0) {
fatal("Must specify at least one workload!");
@ -307,7 +70,7 @@ CREATE_SIM_OBJECT(DerivO3CPU)
params->clock = clock;
params->phase = phase;
params->name = getInstanceName();
params->name = name;
params->numberOfThreads = actual_num_threads;
params->cpu_id = cpu_id;
params->activity = activity;
@ -325,7 +88,9 @@ CREATE_SIM_OBJECT(DerivO3CPU)
params->workload = workload;
#endif // FULL_SYSTEM
#if USE_CHECKER
params->checker = checker;
#endif
params->max_insts_any_thread = max_insts_any_thread;
params->max_insts_all_threads = max_insts_all_threads;
@ -429,6 +194,3 @@ CREATE_SIM_OBJECT(DerivO3CPU)
return cpu;
}
REGISTER_SIM_OBJECT("DerivO3CPU", DerivO3CPU)

6
src/cpu/o3/alpha/cpu_impl.hh
View file

@ -293,14 +293,16 @@ template <class Impl>
TheISA::IntReg
AlphaO3CPU<Impl>::getSyscallArg(int i, int tid)
{
return this->readArchIntReg(AlphaISA::ArgumentReg0 + i, tid);
assert(i < TheISA::NumArgumentRegs);
return this->readArchIntReg(AlphaISA::ArgumentReg[i], tid);
}
template <class Impl>
void
AlphaO3CPU<Impl>::setSyscallArg(int i, TheISA::IntReg val, int tid)
{
this->setArchIntReg(AlphaISA::ArgumentReg0 + i, val, tid);
assert(i < TheISA::NumArgumentRegs);
this->setArchIntReg(AlphaISA::ArgumentReg[i], val, tid);
}
template <class Impl>

72
src/cpu/o3/checker_builder.cc
View file

@ -34,7 +34,7 @@
#include "cpu/inst_seq.hh"
#include "cpu/o3/alpha/dyn_inst.hh"
#include "cpu/o3/alpha/impl.hh"
#include "sim/builder.hh"
#include "params/O3Checker.hh"
#include "sim/process.hh"
#include "sim/sim_object.hh"
@ -58,73 +58,11 @@ class O3Checker : public Checker<RefCountingPtr<AlphaDynInst<AlphaSimpleImpl> >
//
// CheckerCPU Simulation Object
//
BEGIN_DECLARE_SIM_OBJECT_PARAMS(O3Checker)
Param<Counter> max_insts_any_thread;
Param<Counter> max_insts_all_threads;
Param<Counter> max_loads_any_thread;
Param<Counter> max_loads_all_threads;
Param<Tick> progress_interval;
#if FULL_SYSTEM
SimObjectParam<TheISA::ITB *> itb;
SimObjectParam<TheISA::DTB *> dtb;
SimObjectParam<System *> system;
Param<int> cpu_id;
Param<Tick> profile;
#else
SimObjectParam<Process *> workload;
#endif // FULL_SYSTEM
Param<int> clock;
Param<bool> defer_registration;
Param<bool> exitOnError;
Param<bool> updateOnError;
Param<bool> warnOnlyOnLoadError;
Param<bool> function_trace;
Param<Tick> function_trace_start;
END_DECLARE_SIM_OBJECT_PARAMS(O3Checker)
BEGIN_INIT_SIM_OBJECT_PARAMS(O3Checker)
INIT_PARAM(max_insts_any_thread,
"terminate when any thread reaches this inst count"),
INIT_PARAM(max_insts_all_threads,
"terminate when all threads have reached this inst count"),
INIT_PARAM(max_loads_any_thread,
"terminate when any thread reaches this load count"),
INIT_PARAM(max_loads_all_threads,
"terminate when all threads have reached this load count"),
INIT_PARAM_DFLT(progress_interval, "CPU Progress Interval", 0),
#if FULL_SYSTEM
INIT_PARAM(itb, "Instruction TLB"),
INIT_PARAM(dtb, "Data TLB"),
INIT_PARAM(system, "system object"),
INIT_PARAM(cpu_id, "processor ID"),
INIT_PARAM(profile, ""),
#else
INIT_PARAM(workload, "processes to run"),
#endif // FULL_SYSTEM
INIT_PARAM(clock, "clock speed"),
INIT_PARAM(defer_registration, "defer system registration (for sampling)"),
INIT_PARAM(exitOnError, "exit on error"),
INIT_PARAM(updateOnError, "Update the checker with the main CPU's state on error"),
INIT_PARAM_DFLT(warnOnlyOnLoadError, "warn, but don't exit, if a load "
"result errors", false),
INIT_PARAM(function_trace, "Enable function trace"),
INIT_PARAM(function_trace_start, "Cycle to start function trace")
END_INIT_SIM_OBJECT_PARAMS(O3Checker)
CREATE_SIM_OBJECT(O3Checker)
O3Checker *
O3CheckerParams::create()
{
O3Checker::Params *params = new O3Checker::Params();
params->name = getInstanceName();
params->name = name;
params->numberOfThreads = 1;
params->max_insts_any_thread = 0;
params->max_insts_all_threads = 0;
@ -161,5 +99,3 @@ CREATE_SIM_OBJECT(O3Checker)
O3Checker *cpu = new O3Checker(params);
return cpu;
}
REGISTER_SIM_OBJECT("O3Checker", O3Checker)

20
src/cpu/o3/cpu.cc
View file

@ -32,6 +32,15 @@
#include "config/full_system.hh"
#include "config/use_checker.hh"
#include "cpu/activity.hh"
#include "cpu/simple_thread.hh"
#include "cpu/thread_context.hh"
#include "cpu/o3/isa_specific.hh"
#include "cpu/o3/cpu.hh"
#include "enums/MemoryMode.hh"
#include "sim/core.hh"
#include "sim/stat_control.hh"
#if FULL_SYSTEM
#include "cpu/quiesce_event.hh"
#include "sim/system.hh"
@ -39,15 +48,6 @@
#include "sim/process.hh"
#endif
#include "cpu/activity.hh"
#include "cpu/simple_thread.hh"
#include "cpu/thread_context.hh"
#include "cpu/o3/isa_specific.hh"
#include "cpu/o3/cpu.hh"
#include "sim/core.hh"
#include "sim/stat_control.hh"
#if USE_CHECKER
#include "cpu/checker/cpu.hh"
#endif
@ -882,7 +882,7 @@ FullO3CPU<Impl>::resume()
return;
#if FULL_SYSTEM
assert(system->getMemoryMode() == System::Timing);
assert(system->getMemoryMode() == Enums::timing);
#endif
if (!tickEvent.scheduled())

25
src/cpu/o3/fu_pool.cc
View file

@ -32,7 +32,7 @@
#include "cpu/o3/fu_pool.hh"
#include "cpu/func_unit.hh"
#include "sim/builder.hh"
#include "params/FUPool.hh"
using namespace std;
@ -275,25 +275,8 @@ FUPool::takeOverFrom()
//
// The FuPool object
//
BEGIN_DECLARE_SIM_OBJECT_PARAMS(FUPool)
SimObjectVectorParam<FUDesc *> FUList;
END_DECLARE_SIM_OBJECT_PARAMS(FUPool)
BEGIN_INIT_SIM_OBJECT_PARAMS(FUPool)
INIT_PARAM(FUList, "list of FU's for this pool")
END_INIT_SIM_OBJECT_PARAMS(FUPool)
CREATE_SIM_OBJECT(FUPool)
FUPool *
FUPoolParams::create()
{
return new FUPool(getInstanceName(), FUList);
return new FUPool(name, FUList);
}
REGISTER_SIM_OBJECT("FUPool", FUPool)

10
src/cpu/o3/inst_queue_impl.hh
View file

@ -32,10 +32,10 @@
#include <limits>
#include <vector>
#include "sim/core.hh"
#include "cpu/o3/fu_pool.hh"
#include "cpu/o3/inst_queue.hh"
#include "enums/OpClass.hh"
#include "sim/core.hh"
template <class Impl>
InstructionQueue<Impl>::FUCompletion::FUCompletion(DynInstPtr &_inst,
@ -259,12 +259,12 @@ InstructionQueue<Impl>::regStats()
}
*/
statIssuedInstType
.init(numThreads,Num_OpClasses)
.init(numThreads,Enums::Num_OpClass)
.name(name() + ".ISSUE:FU_type")
.desc("Type of FU issued")
.flags(total | pdf | dist)
;
statIssuedInstType.ysubnames(opClassStrings);
statIssuedInstType.ysubnames(Enums::OpClassStrings);
//
// How long did instructions for a particular FU type wait prior to issue
@ -297,7 +297,7 @@ InstructionQueue<Impl>::regStats()
.flags(pdf | dist)
;
for (int i=0; i < Num_OpClasses; ++i) {
statFuBusy.subname(i, opClassStrings[i]);
statFuBusy.subname(i, Enums::OpClassStrings[i]);
}
fuBusy

230
src/cpu/o3/mips/cpu_builder.cc
View file

@ -31,12 +31,13 @@
#include <string>
#include "config/use_checker.hh"
#include "cpu/base.hh"
#include "cpu/o3/mips/cpu.hh"
#include "cpu/o3/mips/impl.hh"
#include "cpu/o3/mips/params.hh"
#include "cpu/o3/fu_pool.hh"
#include "sim/builder.hh"
#include "params/DerivO3CPU.hh"
class DerivO3CPU : public MipsO3CPU<MipsSimpleImpl>
{
@ -46,229 +47,15 @@ class DerivO3CPU : public MipsO3CPU<MipsSimpleImpl>
{ }
};
BEGIN_DECLARE_SIM_OBJECT_PARAMS(DerivO3CPU)
Param<int> clock;
Param<int> phase;
Param<int> numThreads;
Param<int> cpu_id;
Param<int> activity;
SimObjectVectorParam<Process *> workload;
SimObjectParam<BaseCPU *> checker;
Param<Counter> max_insts_any_thread;
Param<Counter> max_insts_all_threads;
Param<Counter> max_loads_any_thread;
Param<Counter> max_loads_all_threads;
Param<unsigned> cachePorts;
Param<unsigned> decodeToFetchDelay;
Param<unsigned> renameToFetchDelay;
Param<unsigned> iewToFetchDelay;
Param<unsigned> commitToFetchDelay;
Param<unsigned> fetchWidth;
Param<unsigned> renameToDecodeDelay;
Param<unsigned> iewToDecodeDelay;
Param<unsigned> commitToDecodeDelay;
Param<unsigned> fetchToDecodeDelay;
Param<unsigned> decodeWidth;
Param<unsigned> iewToRenameDelay;
Param<unsigned> commitToRenameDelay;
Param<unsigned> decodeToRenameDelay;
Param<unsigned> renameWidth;
Param<unsigned> commitToIEWDelay;
Param<unsigned> renameToIEWDelay;
Param<unsigned> issueToExecuteDelay;
Param<unsigned> dispatchWidth;
Param<unsigned> issueWidth;
Param<unsigned> wbWidth;
Param<unsigned> wbDepth;
SimObjectParam<FUPool *> fuPool;
Param<unsigned> iewToCommitDelay;
Param<unsigned> renameToROBDelay;
Param<unsigned> commitWidth;
Param<unsigned> squashWidth;
Param<Tick> trapLatency;
Param<unsigned> backComSize;
Param<unsigned> forwardComSize;
Param<std::string> predType;
Param<unsigned> localPredictorSize;
Param<unsigned> localCtrBits;
Param<unsigned> localHistoryTableSize;
Param<unsigned> localHistoryBits;
Param<unsigned> globalPredictorSize;
Param<unsigned> globalCtrBits;
Param<unsigned> globalHistoryBits;
Param<unsigned> choicePredictorSize;
Param<unsigned> choiceCtrBits;
Param<unsigned> BTBEntries;
Param<unsigned> BTBTagSize;
Param<unsigned> RASSize;
Param<unsigned> LQEntries;
Param<unsigned> SQEntries;
Param<unsigned> LFSTSize;
Param<unsigned> SSITSize;
Param<unsigned> numPhysIntRegs;
Param<unsigned> numPhysFloatRegs;
Param<unsigned> numIQEntries;
Param<unsigned> numROBEntries;
Param<unsigned> smtNumFetchingThreads;
Param<std::string> smtFetchPolicy;
Param<std::string> smtLSQPolicy;
Param<unsigned> smtLSQThreshold;
Param<std::string> smtIQPolicy;
Param<unsigned> smtIQThreshold;
Param<std::string> smtROBPolicy;
Param<unsigned> smtROBThreshold;
Param<std::string> smtCommitPolicy;
Param<unsigned> instShiftAmt;
Param<bool> defer_registration;
Param<bool> function_trace;
Param<Tick> function_trace_start;
END_DECLARE_SIM_OBJECT_PARAMS(DerivO3CPU)
BEGIN_INIT_SIM_OBJECT_PARAMS(DerivO3CPU)
INIT_PARAM(clock, "clock speed"),
INIT_PARAM_DFLT(phase, "clock phase", 0),
INIT_PARAM(numThreads, "number of HW thread contexts"),
INIT_PARAM(cpu_id, "processor ID"),
INIT_PARAM_DFLT(activity, "Initial activity count", 0),
INIT_PARAM(workload, "Processes to run"),
INIT_PARAM_DFLT(checker, "Checker CPU", NULL),
INIT_PARAM_DFLT(max_insts_any_thread,
"Terminate when any thread reaches this inst count",
0),
INIT_PARAM_DFLT(max_insts_all_threads,
"Terminate when all threads have reached"
"this inst count",
0),
INIT_PARAM_DFLT(max_loads_any_thread,
"Terminate when any thread reaches this load count",
0),
INIT_PARAM_DFLT(max_loads_all_threads,
"Terminate when all threads have reached this load"
"count",
0),
INIT_PARAM_DFLT(cachePorts, "Cache Ports", 200),
INIT_PARAM(decodeToFetchDelay, "Decode to fetch delay"),
INIT_PARAM(renameToFetchDelay, "Rename to fetch delay"),
INIT_PARAM(iewToFetchDelay, "Issue/Execute/Writeback to fetch"
"delay"),
INIT_PARAM(commitToFetchDelay, "Commit to fetch delay"),
INIT_PARAM(fetchWidth, "Fetch width"),
INIT_PARAM(renameToDecodeDelay, "Rename to decode delay"),
INIT_PARAM(iewToDecodeDelay, "Issue/Execute/Writeback to decode"
"delay"),
INIT_PARAM(commitToDecodeDelay, "Commit to decode delay"),
INIT_PARAM(fetchToDecodeDelay, "Fetch to decode delay"),
INIT_PARAM(decodeWidth, "Decode width"),
INIT_PARAM(iewToRenameDelay, "Issue/Execute/Writeback to rename"
"delay"),
INIT_PARAM(commitToRenameDelay, "Commit to rename delay"),
INIT_PARAM(decodeToRenameDelay, "Decode to rename delay"),
INIT_PARAM(renameWidth, "Rename width"),
INIT_PARAM(commitToIEWDelay, "Commit to "
"Issue/Execute/Writeback delay"),
INIT_PARAM(renameToIEWDelay, "Rename to "
"Issue/Execute/Writeback delay"),
INIT_PARAM(issueToExecuteDelay, "Issue to execute delay (internal"
"to the IEW stage)"),
INIT_PARAM(dispatchWidth, "Dispatch width"),
INIT_PARAM(issueWidth, "Issue width"),
INIT_PARAM(wbWidth, "Writeback width"),
INIT_PARAM(wbDepth, "Writeback depth (number of cycles it can buffer)"),
INIT_PARAM_DFLT(fuPool, "Functional unit pool", NULL),
INIT_PARAM(iewToCommitDelay, "Issue/Execute/Writeback to commit "
"delay"),
INIT_PARAM(renameToROBDelay, "Rename to reorder buffer delay"),
INIT_PARAM(commitWidth, "Commit width"),
INIT_PARAM(squashWidth, "Squash width"),
INIT_PARAM_DFLT(trapLatency, "Number of cycles before the trap is handled", 6),
INIT_PARAM(backComSize, "Time buffer size for backwards communication"),
INIT_PARAM(forwardComSize, "Time buffer size for forward communication"),
INIT_PARAM(predType, "Type of branch predictor ('local', 'tournament')"),
INIT_PARAM(localPredictorSize, "Size of local predictor"),
INIT_PARAM(localCtrBits, "Bits per counter"),
INIT_PARAM(localHistoryTableSize, "Size of local history table"),
INIT_PARAM(localHistoryBits, "Bits for the local history"),
INIT_PARAM(globalPredictorSize, "Size of global predictor"),
INIT_PARAM(globalCtrBits, "Bits per counter"),
INIT_PARAM(globalHistoryBits, "Bits of history"),
INIT_PARAM(choicePredictorSize, "Size of choice predictor"),
INIT_PARAM(choiceCtrBits, "Bits of choice counters"),
INIT_PARAM(BTBEntries, "Number of BTB entries"),
INIT_PARAM(BTBTagSize, "Size of the BTB tags, in bits"),
INIT_PARAM(RASSize, "RAS size"),
INIT_PARAM(LQEntries, "Number of load queue entries"),
INIT_PARAM(SQEntries, "Number of store queue entries"),
INIT_PARAM(LFSTSize, "Last fetched store table size"),
INIT_PARAM(SSITSize, "Store set ID table size"),
INIT_PARAM(numPhysIntRegs, "Number of physical integer registers"),
INIT_PARAM(numPhysFloatRegs, "Number of physical floating point "
"registers"),
INIT_PARAM(numIQEntries, "Number of instruction queue entries"),
INIT_PARAM(numROBEntries, "Number of reorder buffer entries"),
INIT_PARAM_DFLT(smtNumFetchingThreads, "SMT Number of Fetching Threads", 1),
INIT_PARAM_DFLT(smtFetchPolicy, "SMT Fetch Policy", "SingleThread"),
INIT_PARAM_DFLT(smtLSQPolicy, "SMT LSQ Sharing Policy", "Partitioned"),
INIT_PARAM_DFLT(smtLSQThreshold,"SMT LSQ Threshold", 100),
INIT_PARAM_DFLT(smtIQPolicy, "SMT IQ Policy", "Partitioned"),
INIT_PARAM_DFLT(smtIQThreshold, "SMT IQ Threshold", 100),
INIT_PARAM_DFLT(smtROBPolicy, "SMT ROB Sharing Policy", "Partitioned"),
INIT_PARAM_DFLT(smtROBThreshold,"SMT ROB Threshold", 100),
INIT_PARAM_DFLT(smtCommitPolicy,"SMT Commit Fetch Policy", "RoundRobin"),
INIT_PARAM(instShiftAmt, "Number of bits to shift instructions by"),
INIT_PARAM(defer_registration, "defer system registration (for sampling)"),
INIT_PARAM(function_trace, "Enable function trace"),
INIT_PARAM(function_trace_start, "Cycle to start function trace")
END_INIT_SIM_OBJECT_PARAMS(DerivO3CPU)
CREATE_SIM_OBJECT(DerivO3CPU)
DerivO3CPU *
DerivO3CPUParams::create()
{
DerivO3CPU *cpu;
// In non-full-system mode, we infer the number of threads from
// the workload if it's not explicitly specified.
int actual_num_threads =
(numThreads.isValid() && numThreads >= workload.size()) ?
numThreads : workload.size();
(numThreads >= workload.size()) ? numThreads : workload.size();
if (workload.size() == 0) {
fatal("Must specify at least one workload!");
@ -279,14 +66,16 @@ CREATE_SIM_OBJECT(DerivO3CPU)
params->clock = clock;
params->phase = phase;
params->name = getInstanceName();
params->name = name;
params->numberOfThreads = actual_num_threads;
params->cpu_id = cpu_id;
params->activity = activity;
params->workload = workload;
#if USE_CHECKER
params->checker = checker;
#endif
params->max_insts_any_thread = max_insts_any_thread;
params->max_insts_all_threads = max_insts_all_threads;
@ -389,6 +178,3 @@ CREATE_SIM_OBJECT(DerivO3CPU)
return cpu;
}
REGISTER_SIM_OBJECT("DerivO3CPU", DerivO3CPU)

6
src/cpu/o3/mips/cpu_impl.hh
View file

@ -196,14 +196,16 @@ template <class Impl>
TheISA::IntReg
MipsO3CPU<Impl>::getSyscallArg(int i, int tid)
{
return this->readArchIntReg(MipsISA::ArgumentReg0 + i, tid);
assert(i < TheISA::NumArgumentRegs);
return this->readArchIntReg(MipsISA::ArgumentReg[i], tid);
}
template <class Impl>
void
MipsO3CPU<Impl>::setSyscallArg(int i, IntReg val, int tid)
{
this->setArchIntReg(MipsISA::ArgumentReg0 + i, val, tid);
assert(i < TheISA::NumArgumentRegs);
this->setArchIntReg(MipsISA::ArgumentReg[i], val, tid);
}
template <class Impl>

255
src/cpu/o3/sparc/cpu_builder.cc
View file

@ -30,12 +30,14 @@
#include <string>
#include "config/full_system.hh"
#include "config/use_checker.hh"
#include "cpu/base.hh"
#include "cpu/o3/sparc/cpu.hh"
#include "cpu/o3/sparc/impl.hh"
#include "cpu/o3/sparc/params.hh"
#include "cpu/o3/fu_pool.hh"
#include "sim/builder.hh"
#include "params/DerivO3CPU.hh"
class DerivO3CPU : public SparcO3CPU<SparcSimpleImpl>
{
@ -45,245 +47,8 @@ class DerivO3CPU : public SparcO3CPU<SparcSimpleImpl>
{ }
};
BEGIN_DECLARE_SIM_OBJECT_PARAMS(DerivO3CPU)
Param<int> clock;
Param<int> phase;
Param<int> numThreads;
Param<int> cpu_id;
Param<int> activity;
#if FULL_SYSTEM
SimObjectParam<System *> system;
SimObjectParam<SparcISA::ITB *> itb;
SimObjectParam<SparcISA::DTB *> dtb;
Param<Tick> profile;
Param<bool> do_quiesce;
Param<bool> do_checkpoint_insts;
Param<bool> do_statistics_insts;
#else
SimObjectVectorParam<Process *> workload;
#endif // FULL_SYSTEM
SimObjectParam<BaseCPU *> checker;
Param<Counter> max_insts_any_thread;
Param<Counter> max_insts_all_threads;
Param<Counter> max_loads_any_thread;
Param<Counter> max_loads_all_threads;
Param<Tick> progress_interval;
Param<unsigned> cachePorts;
Param<unsigned> decodeToFetchDelay;
Param<unsigned> renameToFetchDelay;
Param<unsigned> iewToFetchDelay;
Param<unsigned> commitToFetchDelay;
Param<unsigned> fetchWidth;
Param<unsigned> renameToDecodeDelay;
Param<unsigned> iewToDecodeDelay;
Param<unsigned> commitToDecodeDelay;
Param<unsigned> fetchToDecodeDelay;
Param<unsigned> decodeWidth;
Param<unsigned> iewToRenameDelay;
Param<unsigned> commitToRenameDelay;
Param<unsigned> decodeToRenameDelay;
Param<unsigned> renameWidth;
Param<unsigned> commitToIEWDelay;
Param<unsigned> renameToIEWDelay;
Param<unsigned> issueToExecuteDelay;
Param<unsigned> dispatchWidth;
Param<unsigned> issueWidth;
Param<unsigned> wbWidth;
Param<unsigned> wbDepth;
SimObjectParam<FUPool *> fuPool;
Param<unsigned> iewToCommitDelay;
Param<unsigned> renameToROBDelay;
Param<unsigned> commitWidth;
Param<unsigned> squashWidth;
Param<Tick> trapLatency;
Param<unsigned> backComSize;
Param<unsigned> forwardComSize;
Param<std::string> predType;
Param<unsigned> localPredictorSize;
Param<unsigned> localCtrBits;
Param<unsigned> localHistoryTableSize;
Param<unsigned> localHistoryBits;
Param<unsigned> globalPredictorSize;
Param<unsigned> globalCtrBits;
Param<unsigned> globalHistoryBits;
Param<unsigned> choicePredictorSize;
Param<unsigned> choiceCtrBits;
Param<unsigned> BTBEntries;
Param<unsigned> BTBTagSize;
Param<unsigned> RASSize;
Param<unsigned> LQEntries;
Param<unsigned> SQEntries;
Param<unsigned> LFSTSize;
Param<unsigned> SSITSize;
Param<unsigned> numPhysIntRegs;
Param<unsigned> numPhysFloatRegs;
Param<unsigned> numIQEntries;
Param<unsigned> numROBEntries;
Param<unsigned> smtNumFetchingThreads;
Param<std::string> smtFetchPolicy;
Param<std::string> smtLSQPolicy;
Param<unsigned> smtLSQThreshold;
Param<std::string> smtIQPolicy;
Param<unsigned> smtIQThreshold;
Param<std::string> smtROBPolicy;
Param<unsigned> smtROBThreshold;
Param<std::string> smtCommitPolicy;
Param<unsigned> instShiftAmt;
Param<bool> defer_registration;
Param<bool> function_trace;
Param<Tick> function_trace_start;
END_DECLARE_SIM_OBJECT_PARAMS(DerivO3CPU)
BEGIN_INIT_SIM_OBJECT_PARAMS(DerivO3CPU)
INIT_PARAM(clock, "clock speed"),
INIT_PARAM_DFLT(phase, "clock phase", 0),
INIT_PARAM(numThreads, "number of HW thread contexts"),
INIT_PARAM(cpu_id, "processor ID"),
INIT_PARAM_DFLT(activity, "Initial activity count", 0),
#if FULL_SYSTEM
INIT_PARAM(system, "System object"),
INIT_PARAM(itb, "Instruction translation buffer"),
INIT_PARAM(dtb, "Data translation buffer"),
INIT_PARAM(profile, ""),
INIT_PARAM(do_quiesce, ""),
INIT_PARAM(do_checkpoint_insts, ""),
INIT_PARAM(do_statistics_insts, ""),
#else
INIT_PARAM(workload, "Processes to run"),
#endif // FULL_SYSTEM
INIT_PARAM_DFLT(checker, "Checker CPU", NULL),
INIT_PARAM_DFLT(max_insts_any_thread,
"Terminate when any thread reaches this inst count",
0),
INIT_PARAM_DFLT(max_insts_all_threads,
"Terminate when all threads have reached"
"this inst count",
0),
INIT_PARAM_DFLT(max_loads_any_thread,
"Terminate when any thread reaches this load count",
0),
INIT_PARAM_DFLT(max_loads_all_threads,
"Terminate when all threads have reached this load"
"count",
0),
INIT_PARAM_DFLT(progress_interval, "Progress interval", 0),
INIT_PARAM_DFLT(cachePorts, "Cache Ports", 200),
INIT_PARAM(decodeToFetchDelay, "Decode to fetch delay"),
INIT_PARAM(renameToFetchDelay, "Rename to fetch delay"),
INIT_PARAM(iewToFetchDelay, "Issue/Execute/Writeback to fetch"
"delay"),
INIT_PARAM(commitToFetchDelay, "Commit to fetch delay"),
INIT_PARAM(fetchWidth, "Fetch width"),
INIT_PARAM(renameToDecodeDelay, "Rename to decode delay"),
INIT_PARAM(iewToDecodeDelay, "Issue/Execute/Writeback to decode"
"delay"),
INIT_PARAM(commitToDecodeDelay, "Commit to decode delay"),
INIT_PARAM(fetchToDecodeDelay, "Fetch to decode delay"),
INIT_PARAM(decodeWidth, "Decode width"),
INIT_PARAM(iewToRenameDelay, "Issue/Execute/Writeback to rename"
"delay"),
INIT_PARAM(commitToRenameDelay, "Commit to rename delay"),
INIT_PARAM(decodeToRenameDelay, "Decode to rename delay"),
INIT_PARAM(renameWidth, "Rename width"),
INIT_PARAM(commitToIEWDelay, "Commit to "
"Issue/Execute/Writeback delay"),
INIT_PARAM(renameToIEWDelay, "Rename to "
"Issue/Execute/Writeback delay"),
INIT_PARAM(issueToExecuteDelay, "Issue to execute delay (internal"
"to the IEW stage)"),
INIT_PARAM(dispatchWidth, "Dispatch width"),
INIT_PARAM(issueWidth, "Issue width"),
INIT_PARAM(wbWidth, "Writeback width"),
INIT_PARAM(wbDepth, "Writeback depth (number of cycles it can buffer)"),
INIT_PARAM_DFLT(fuPool, "Functional unit pool", NULL),
INIT_PARAM(iewToCommitDelay, "Issue/Execute/Writeback to commit "
"delay"),
INIT_PARAM(renameToROBDelay, "Rename to reorder buffer delay"),
INIT_PARAM(commitWidth, "Commit width"),
INIT_PARAM(squashWidth, "Squash width"),
INIT_PARAM_DFLT(trapLatency, "Number of cycles before the trap is handled", 6),
INIT_PARAM(backComSize, "Time buffer size for backwards communication"),
INIT_PARAM(forwardComSize, "Time buffer size for forward communication"),
INIT_PARAM(predType, "Type of branch predictor ('local', 'tournament')"),
INIT_PARAM(localPredictorSize, "Size of local predictor"),
INIT_PARAM(localCtrBits, "Bits per counter"),
INIT_PARAM(localHistoryTableSize, "Size of local history table"),
INIT_PARAM(localHistoryBits, "Bits for the local history"),
INIT_PARAM(globalPredictorSize, "Size of global predictor"),
INIT_PARAM(globalCtrBits, "Bits per counter"),
INIT_PARAM(globalHistoryBits, "Bits of history"),
INIT_PARAM(choicePredictorSize, "Size of choice predictor"),
INIT_PARAM(choiceCtrBits, "Bits of choice counters"),
INIT_PARAM(BTBEntries, "Number of BTB entries"),
INIT_PARAM(BTBTagSize, "Size of the BTB tags, in bits"),
INIT_PARAM(RASSize, "RAS size"),
INIT_PARAM(LQEntries, "Number of load queue entries"),
INIT_PARAM(SQEntries, "Number of store queue entries"),
INIT_PARAM(LFSTSize, "Last fetched store table size"),
INIT_PARAM(SSITSize, "Store set ID table size"),
INIT_PARAM(numPhysIntRegs, "Number of physical integer registers"),
INIT_PARAM(numPhysFloatRegs, "Number of physical floating point "
"registers"),
INIT_PARAM(numIQEntries, "Number of instruction queue entries"),
INIT_PARAM(numROBEntries, "Number of reorder buffer entries"),
INIT_PARAM_DFLT(smtNumFetchingThreads, "SMT Number of Fetching Threads", 1),
INIT_PARAM_DFLT(smtFetchPolicy, "SMT Fetch Policy", "SingleThread"),
INIT_PARAM_DFLT(smtLSQPolicy, "SMT LSQ Sharing Policy", "Partitioned"),
INIT_PARAM_DFLT(smtLSQThreshold,"SMT LSQ Threshold", 100),
INIT_PARAM_DFLT(smtIQPolicy, "SMT IQ Policy", "Partitioned"),
INIT_PARAM_DFLT(smtIQThreshold, "SMT IQ Threshold", 100),
INIT_PARAM_DFLT(smtROBPolicy, "SMT ROB Sharing Policy", "Partitioned"),
INIT_PARAM_DFLT(smtROBThreshold,"SMT ROB Threshold", 100),
INIT_PARAM_DFLT(smtCommitPolicy,"SMT Commit Fetch Policy", "RoundRobin"),
INIT_PARAM(instShiftAmt, "Number of bits to shift instructions by"),
INIT_PARAM(defer_registration, "defer system registration (for sampling)"),
INIT_PARAM(function_trace, "Enable function trace"),
INIT_PARAM(function_trace_start, "Cycle to start function trace")
END_INIT_SIM_OBJECT_PARAMS(DerivO3CPU)
CREATE_SIM_OBJECT(DerivO3CPU)
DerivO3CPU *
DerivO3CPUParams::create()
{
DerivO3CPU *cpu;
@ -294,8 +59,7 @@ CREATE_SIM_OBJECT(DerivO3CPU)
// In non-full-system mode, we infer the number of threads from
// the workload if it's not explicitly specified.
int actual_num_threads =
(numThreads.isValid() && numThreads >= workload.size()) ?
numThreads : workload.size();
(numThreads >= workload.size()) ? numThreads : workload.size();
if (workload.size() == 0) {
fatal("Must specify at least one workload!");
@ -307,7 +71,7 @@ CREATE_SIM_OBJECT(DerivO3CPU)
params->clock = clock;
params->phase = phase;
params->name = getInstanceName();
params->name = name;
params->numberOfThreads = actual_num_threads;
params->cpu_id = cpu_id;
params->activity = activity;
@ -325,7 +89,9 @@ CREATE_SIM_OBJECT(DerivO3CPU)
params->workload = workload;
#endif // FULL_SYSTEM
#if USE_CHECKER
params->checker = checker;
#endif
params->max_insts_any_thread = max_insts_any_thread;
params->max_insts_all_threads = max_insts_all_threads;
@ -429,6 +195,3 @@ CREATE_SIM_OBJECT(DerivO3CPU)
return cpu;
}
REGISTER_SIM_OBJECT("DerivO3CPU", DerivO3CPU)

6
src/cpu/o3/sparc/cpu_impl.hh
View file

@ -270,8 +270,9 @@ template <class Impl>
TheISA::IntReg
SparcO3CPU<Impl>::getSyscallArg(int i, int tid)
{
assert(i < TheISA::NumArgumentRegs);
TheISA::IntReg idx = TheISA::flattenIntIndex(this->tcBase(tid),
SparcISA::ArgumentReg0 + i);
SparcISA::ArgumentReg[i]);
TheISA::IntReg val = this->readArchIntReg(idx, tid);
if (bits(this->readMiscRegNoEffect(SparcISA::MISCREG_PSTATE, tid), 3, 3))
val = bits(val, 31, 0);
@ -282,8 +283,9 @@ template <class Impl>
void
SparcO3CPU<Impl>::setSyscallArg(int i, TheISA::IntReg val, int tid)
{
assert(i < TheISA::NumArgumentRegs);
TheISA::IntReg idx = TheISA::flattenIntIndex(this->tcBase(tid),
SparcISA::ArgumentReg0 + i);
SparcISA::ArgumentReg[i]);
this->setArchIntReg(idx, val, tid);
}

52
src/cpu/op_class.hh
View file

@ -25,43 +25,35 @@
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* Authors: Steve Reinhardt
* Nathan Binkert
* Authors: Nathan Binkert
*/
#ifndef __CPU__OP_CLASS_HH__
#define __CPU__OP_CLASS_HH__
/**
* @file
* Definition of operation classes.
*/
#include "enums/OpClass.hh"
/**
* Instruction operation classes. These classes are used for
* assigning instructions to functional units.
/*
* Do a bunch of wonky stuff to maintain backward compatability so I
* don't have to change code in a zillion places.
*/
enum OpClass {
No_OpClass = 0, ///< Instruction does not use a functional unit
IntAluOp, ///< Integer ALU operaton (add/sub/logical)
IntMultOp, ///< Integer multiply
IntDivOp, ///< Integer divide
FloatAddOp, ///< Floating point add/subtract
FloatCmpOp, ///< Floating point comparison
FloatCvtOp, ///< Floating point<->integer conversion
FloatMultOp, ///< Floating point multiply
FloatDivOp, ///< Floating point divide
FloatSqrtOp, ///< Floating point square root
MemReadOp, ///< Memory read port
MemWriteOp, ///< Memory write port
IprAccessOp, ///< Internal Processor Register read/write port
InstPrefetchOp, ///< Instruction prefetch port (on I-cache)
Num_OpClasses ///< Total number of operation classes
};
using Enums::OpClass;
using Enums::No_OpClass;
using Enums::Num_OpClass;
/**
* Array mapping OpClass enum values to strings. Defined in op_class.cc.
*/
extern const char *opClassStrings[Num_OpClasses];
const OpClass IntAluOp = Enums::IntAlu;
const OpClass IntMultOp = Enums::IntMult;
const OpClass IntDivOp = Enums::IntDiv;
const OpClass FloatAddOp = Enums::FloatAdd;
const OpClass FloatCmpOp = Enums::FloatCmp;
const OpClass FloatCvtOp = Enums::FloatCvt;
const OpClass FloatMultOp = Enums::FloatMult;
const OpClass FloatDivOp = Enums::FloatDiv;
const OpClass FloatSqrtOp = Enums::FloatSqrt;
const OpClass MemReadOp = Enums::MemRead;
const OpClass MemWriteOp = Enums::MemWrite;
const OpClass IprAccessOp = Enums::IprAccess;
const OpClass InstPrefetchOp = Enums::InstPrefetch;
const OpClass Num_OpClasses = Num_OpClass;
#endif // __CPU__OP_CLASS_HH__

72
src/cpu/ozone/checker_builder.cc
View file

@ -34,7 +34,7 @@
#include "cpu/inst_seq.hh"
#include "cpu/ozone/dyn_inst.hh"
#include "cpu/ozone/ozone_impl.hh"
#include "sim/builder.hh"
#include "params/OzoneChecker.hh"
#include "sim/process.hh"
#include "sim/sim_object.hh"
@ -59,73 +59,11 @@ class OzoneChecker :
//
// CheckerCPU Simulation Object
//
BEGIN_DECLARE_SIM_OBJECT_PARAMS(OzoneChecker)
Param<Counter> max_insts_any_thread;
Param<Counter> max_insts_all_threads;
Param<Counter> max_loads_any_thread;
Param<Counter> max_loads_all_threads;
Param<Tick> progress_interval;
#if FULL_SYSTEM
SimObjectParam<TheISA::ITB *> itb;
SimObjectParam<TheISA::DTB *> dtb;
SimObjectParam<System *> system;
Param<int> cpu_id;
Param<Tick> profile;
#else
SimObjectParam<Process *> workload;
#endif // FULL_SYSTEM
Param<int> clock;
Param<bool> defer_registration;
Param<bool> exitOnError;
Param<bool> updateOnError;
Param<bool> warnOnlyOnLoadError;
Param<bool> function_trace;
Param<Tick> function_trace_start;
END_DECLARE_SIM_OBJECT_PARAMS(OzoneChecker)
BEGIN_INIT_SIM_OBJECT_PARAMS(OzoneChecker)
INIT_PARAM(max_insts_any_thread,
"terminate when any thread reaches this inst count"),
INIT_PARAM(max_insts_all_threads,
"terminate when all threads have reached this inst count"),
INIT_PARAM(max_loads_any_thread,
"terminate when any thread reaches this load count"),
INIT_PARAM(max_loads_all_threads,
"terminate when all threads have reached this load count"),
INIT_PARAM_DFLT(progress_interval, "CPU Progress Interval", 0),
#if FULL_SYSTEM
INIT_PARAM(itb, "Instruction TLB"),
INIT_PARAM(dtb, "Data TLB"),
INIT_PARAM(system, "system object"),
INIT_PARAM(cpu_id, "processor ID"),
INIT_PARAM(profile, ""),
#else
INIT_PARAM(workload, "processes to run"),
#endif // FULL_SYSTEM
INIT_PARAM(clock, "clock speed"),
INIT_PARAM(defer_registration, "defer system registration (for sampling)"),
INIT_PARAM(exitOnError, "exit on error"),
INIT_PARAM(updateOnError, "Update the checker with the main CPU's state on error"),
INIT_PARAM_DFLT(warnOnlyOnLoadError, "warn, but don't exit, if a load "
"result errors", false),
INIT_PARAM(function_trace, "Enable function trace"),
INIT_PARAM(function_trace_start, "Cycle to start function trace")
END_INIT_SIM_OBJECT_PARAMS(OzoneChecker)
CREATE_SIM_OBJECT(OzoneChecker)
OzoneChecker *
OzoneCheckerParams::create()
{
OzoneChecker::Params *params = new OzoneChecker::Params();
params->name = getInstanceName();
params->name = name;
params->numberOfThreads = 1;
params->max_insts_any_thread = 0;
params->max_insts_all_threads = 0;
@ -162,5 +100,3 @@ CREATE_SIM_OBJECT(OzoneChecker)
OzoneChecker *cpu = new OzoneChecker(params);
return cpu;
}
REGISTER_SIM_OBJECT("OzoneChecker", OzoneChecker)

10
src/cpu/ozone/cpu.hh
View file

@ -253,11 +253,17 @@ class OzoneCPU : public BaseCPU
#if !FULL_SYSTEM
TheISA::IntReg getSyscallArg(int i)
{ return thread->renameTable[TheISA::ArgumentReg0 + i]->readIntResult(); }
{
assert(i < TheISA::NumArgumentRegs);
return thread->renameTable[TheISA::ArgumentReg[i]]->readIntResult();
}
// used to shift args for indirect syscall
void setSyscallArg(int i, TheISA::IntReg val)
{ thread->renameTable[TheISA::ArgumentReg0 + i]->setIntResult(i); }
{
assert(i < TheISA::NumArgumentRegs);
thread->renameTable[TheISA::ArgumentReg[i]]->setIntResult(i);
}
void setSyscallReturn(SyscallReturn return_value)
{ cpu->setSyscallReturn(return_value, thread->readTid()); }

273
src/cpu/ozone/cpu_builder.cc
View file

@ -35,7 +35,7 @@
#include "cpu/ozone/cpu.hh"
#include "cpu/ozone/ozone_impl.hh"
#include "cpu/ozone/simple_params.hh"
#include "sim/builder.hh"
#include "params/DerivOzoneCPU.hh"
#include "sim/process.hh"
#include "sim/sim_object.hh"
@ -52,271 +52,8 @@ class DerivOzoneCPU : public OzoneCPU<OzoneImpl>
//
// OzoneCPU Simulation Object
//
BEGIN_DECLARE_SIM_OBJECT_PARAMS(DerivOzoneCPU)
Param<int> clock;
Param<int> numThreads;
#if FULL_SYSTEM
SimObjectParam<System *> system;
Param<int> cpu_id;
SimObjectParam<TheISA::ITB *> itb;
SimObjectParam<TheISA::DTB *> dtb;
Param<Tick> profile;
Param<bool> do_quiesce;
Param<bool> do_checkpoint_insts;
Param<bool> do_statistics_insts;
#else
SimObjectVectorParam<Process *> workload;
//SimObjectParam<PageTable *> page_table;
#endif // FULL_SYSTEM
SimObjectParam<BaseCPU *> checker;
Param<Counter> max_insts_any_thread;
Param<Counter> max_insts_all_threads;
Param<Counter> max_loads_any_thread;
Param<Counter> max_loads_all_threads;
Param<Tick> progress_interval;
//SimObjectParam<BaseCache *> icache;
//SimObjectParam<BaseCache *> dcache;
Param<unsigned> cachePorts;
Param<unsigned> width;
Param<unsigned> frontEndLatency;
Param<unsigned> frontEndWidth;
Param<unsigned> backEndLatency;
Param<unsigned> backEndWidth;
Param<unsigned> backEndSquashLatency;
Param<unsigned> maxInstBufferSize;
Param<unsigned> numPhysicalRegs;
Param<unsigned> maxOutstandingMemOps;
Param<unsigned> decodeToFetchDelay;
Param<unsigned> renameToFetchDelay;
Param<unsigned> iewToFetchDelay;
Param<unsigned> commitToFetchDelay;
Param<unsigned> fetchWidth;
Param<unsigned> renameToDecodeDelay;
Param<unsigned> iewToDecodeDelay;
Param<unsigned> commitToDecodeDelay;
Param<unsigned> fetchToDecodeDelay;
Param<unsigned> decodeWidth;
Param<unsigned> iewToRenameDelay;
Param<unsigned> commitToRenameDelay;
Param<unsigned> decodeToRenameDelay;
Param<unsigned> renameWidth;
Param<unsigned> commitToIEWDelay;
Param<unsigned> renameToIEWDelay;
Param<unsigned> issueToExecuteDelay;
Param<unsigned> issueWidth;
Param<unsigned> executeWidth;
Param<unsigned> executeIntWidth;
Param<unsigned> executeFloatWidth;
Param<unsigned> executeBranchWidth;
Param<unsigned> executeMemoryWidth;
Param<unsigned> iewToCommitDelay;
Param<unsigned> renameToROBDelay;
Param<unsigned> commitWidth;
Param<unsigned> squashWidth;
Param<std::string> predType;
Param<unsigned> localPredictorSize;
Param<unsigned> localCtrBits;
Param<unsigned> localHistoryTableSize;
Param<unsigned> localHistoryBits;
Param<unsigned> globalPredictorSize;
Param<unsigned> globalCtrBits;
Param<unsigned> globalHistoryBits;
Param<unsigned> choicePredictorSize;
Param<unsigned> choiceCtrBits;
Param<unsigned> BTBEntries;
Param<unsigned> BTBTagSize;
Param<unsigned> RASSize;
Param<unsigned> LQEntries;
Param<unsigned> SQEntries;
Param<bool> lsqLimits;
Param<unsigned> LFSTSize;
Param<unsigned> SSITSize;
Param<unsigned> numPhysIntRegs;
Param<unsigned> numPhysFloatRegs;
Param<unsigned> numIQEntries;
Param<unsigned> numROBEntries;
Param<bool> decoupledFrontEnd;
Param<int> dispatchWidth;
Param<int> wbWidth;
Param<unsigned> smtNumFetchingThreads;
Param<std::string> smtFetchPolicy;
Param<std::string> smtLSQPolicy;
Param<unsigned> smtLSQThreshold;
Param<std::string> smtIQPolicy;
Param<unsigned> smtIQThreshold;
Param<std::string> smtROBPolicy;
Param<unsigned> smtROBThreshold;
Param<std::string> smtCommitPolicy;
Param<unsigned> instShiftAmt;
Param<bool> defer_registration;
Param<bool> function_trace;
Param<Tick> function_trace_start;
END_DECLARE_SIM_OBJECT_PARAMS(DerivOzoneCPU)
BEGIN_INIT_SIM_OBJECT_PARAMS(DerivOzoneCPU)
INIT_PARAM(clock, "clock speed"),
INIT_PARAM(numThreads, "number of HW thread contexts"),
#if FULL_SYSTEM
INIT_PARAM(system, "System object"),
INIT_PARAM(cpu_id, "processor ID"),
INIT_PARAM(itb, "Instruction translation buffer"),
INIT_PARAM(dtb, "Data translation buffer"),
INIT_PARAM(profile, ""),
INIT_PARAM(do_quiesce, ""),
INIT_PARAM(do_checkpoint_insts, ""),
INIT_PARAM(do_statistics_insts, ""),
#else
INIT_PARAM(workload, "Processes to run"),
// INIT_PARAM(page_table, "Page table"),
#endif // FULL_SYSTEM
INIT_PARAM_DFLT(checker, "Checker CPU", NULL),
INIT_PARAM_DFLT(max_insts_any_thread,
"Terminate when any thread reaches this inst count",
0),
INIT_PARAM_DFLT(max_insts_all_threads,
"Terminate when all threads have reached"
"this inst count",
0),
INIT_PARAM_DFLT(max_loads_any_thread,
"Terminate when any thread reaches this load count",
0),
INIT_PARAM_DFLT(max_loads_all_threads,
"Terminate when all threads have reached this load"
"count",
0),
INIT_PARAM_DFLT(progress_interval, "Progress interval", 0),
// INIT_PARAM_DFLT(icache, "L1 instruction cache", NULL),
// INIT_PARAM_DFLT(dcache, "L1 data cache", NULL),
INIT_PARAM_DFLT(cachePorts, "Cache Ports", 200),
INIT_PARAM_DFLT(width, "Width", 1),
INIT_PARAM_DFLT(frontEndLatency, "Front end latency", 1),
INIT_PARAM_DFLT(frontEndWidth, "Front end width", 1),
INIT_PARAM_DFLT(backEndLatency, "Back end latency", 1),
INIT_PARAM_DFLT(backEndWidth, "Back end width", 1),
INIT_PARAM_DFLT(backEndSquashLatency, "Back end squash latency", 1),
INIT_PARAM_DFLT(maxInstBufferSize, "Maximum instruction buffer size", 16),
INIT_PARAM(numPhysicalRegs, "Number of physical registers"),
INIT_PARAM_DFLT(maxOutstandingMemOps, "Maximum outstanding memory operations", 4),
INIT_PARAM(decodeToFetchDelay, "Decode to fetch delay"),
INIT_PARAM(renameToFetchDelay, "Rename to fetch delay"),
INIT_PARAM(iewToFetchDelay, "Issue/Execute/Writeback to fetch"
"delay"),
INIT_PARAM(commitToFetchDelay, "Commit to fetch delay"),
INIT_PARAM(fetchWidth, "Fetch width"),
INIT_PARAM(renameToDecodeDelay, "Rename to decode delay"),
INIT_PARAM(iewToDecodeDelay, "Issue/Execute/Writeback to decode"
"delay"),
INIT_PARAM(commitToDecodeDelay, "Commit to decode delay"),
INIT_PARAM(fetchToDecodeDelay, "Fetch to decode delay"),
INIT_PARAM(decodeWidth, "Decode width"),
INIT_PARAM(iewToRenameDelay, "Issue/Execute/Writeback to rename"
"delay"),
INIT_PARAM(commitToRenameDelay, "Commit to rename delay"),
INIT_PARAM(decodeToRenameDelay, "Decode to rename delay"),
INIT_PARAM(renameWidth, "Rename width"),
INIT_PARAM(commitToIEWDelay, "Commit to "
"Issue/Execute/Writeback delay"),
INIT_PARAM(renameToIEWDelay, "Rename to "
"Issue/Execute/Writeback delay"),
INIT_PARAM(issueToExecuteDelay, "Issue to execute delay (internal"
"to the IEW stage)"),
INIT_PARAM(issueWidth, "Issue width"),
INIT_PARAM(executeWidth, "Execute width"),
INIT_PARAM(executeIntWidth, "Integer execute width"),
INIT_PARAM(executeFloatWidth, "Floating point execute width"),
INIT_PARAM(executeBranchWidth, "Branch execute width"),
INIT_PARAM(executeMemoryWidth, "Memory execute width"),
INIT_PARAM(iewToCommitDelay, "Issue/Execute/Writeback to commit "
"delay"),
INIT_PARAM(renameToROBDelay, "Rename to reorder buffer delay"),
INIT_PARAM(commitWidth, "Commit width"),
INIT_PARAM(squashWidth, "Squash width"),
INIT_PARAM(predType, "Type of branch predictor ('local', 'tournament')"),
INIT_PARAM(localPredictorSize, "Size of local predictor"),
INIT_PARAM(localCtrBits, "Bits per counter"),
INIT_PARAM(localHistoryTableSize, "Size of local history table"),
INIT_PARAM(localHistoryBits, "Bits for the local history"),
INIT_PARAM(globalPredictorSize, "Size of global predictor"),
INIT_PARAM(globalCtrBits, "Bits per counter"),
INIT_PARAM(globalHistoryBits, "Bits of history"),
INIT_PARAM(choicePredictorSize, "Size of choice predictor"),
INIT_PARAM(choiceCtrBits, "Bits of choice counters"),
INIT_PARAM(BTBEntries, "Number of BTB entries"),
INIT_PARAM(BTBTagSize, "Size of the BTB tags, in bits"),
INIT_PARAM(RASSize, "RAS size"),
INIT_PARAM(LQEntries, "Number of load queue entries"),
INIT_PARAM(SQEntries, "Number of store queue entries"),
INIT_PARAM_DFLT(lsqLimits, "LSQ size limits dispatch", true),
INIT_PARAM(LFSTSize, "Last fetched store table size"),
INIT_PARAM(SSITSize, "Store set ID table size"),
INIT_PARAM(numPhysIntRegs, "Number of physical integer registers"),
INIT_PARAM(numPhysFloatRegs, "Number of physical floating point "
"registers"),
INIT_PARAM(numIQEntries, "Number of instruction queue entries"),
INIT_PARAM(numROBEntries, "Number of reorder buffer entries"),
INIT_PARAM_DFLT(decoupledFrontEnd, "Decoupled front end", true),
INIT_PARAM_DFLT(dispatchWidth, "Dispatch width", 0),
INIT_PARAM_DFLT(wbWidth, "Writeback width", 0),
INIT_PARAM_DFLT(smtNumFetchingThreads, "SMT Number of Fetching Threads", 1),
INIT_PARAM_DFLT(smtFetchPolicy, "SMT Fetch Policy", "SingleThread"),
INIT_PARAM_DFLT(smtLSQPolicy, "SMT LSQ Sharing Policy", "Partitioned"),
INIT_PARAM_DFLT(smtLSQThreshold,"SMT LSQ Threshold", 100),
INIT_PARAM_DFLT(smtIQPolicy, "SMT IQ Policy", "Partitioned"),
INIT_PARAM_DFLT(smtIQThreshold, "SMT IQ Threshold", 100),
INIT_PARAM_DFLT(smtROBPolicy, "SMT ROB Sharing Policy", "Partitioned"),
INIT_PARAM_DFLT(smtROBThreshold,"SMT ROB Threshold", 100),
INIT_PARAM_DFLT(smtCommitPolicy,"SMT Commit Fetch Policy", "RoundRobin"),
INIT_PARAM(instShiftAmt, "Number of bits to shift instructions by"),
INIT_PARAM(defer_registration, "defer system registration (for sampling)"),
INIT_PARAM(function_trace, "Enable function trace"),
INIT_PARAM(function_trace_start, "Cycle to start function trace")
END_INIT_SIM_OBJECT_PARAMS(DerivOzoneCPU)
CREATE_SIM_OBJECT(DerivOzoneCPU)
DerivOzoneCPU *
DerivOzoneCPUParams::create()
{
DerivOzoneCPU *cpu;
@ -339,7 +76,7 @@ CREATE_SIM_OBJECT(DerivOzoneCPU)
params->clock = clock;
params->name = getInstanceName();
params->name = name;
params->numberOfThreads = actual_num_threads;
#if FULL_SYSTEM
@ -464,5 +201,3 @@ CREATE_SIM_OBJECT(DerivOzoneCPU)
return cpu;
}
REGISTER_SIM_OBJECT("DerivOzoneCPU", DerivOzoneCPU)

261
src/cpu/ozone/simple_cpu_builder.cc
View file

@ -36,7 +36,7 @@
#include "cpu/ozone/simple_impl.hh"
#include "cpu/ozone/simple_params.hh"
#include "mem/cache/base_cache.hh"
#include "sim/builder.hh"
#include "sim/SimpleOzoneCPU.hh"
#include "sim/process.hh"
#include "sim/sim_object.hh"
@ -55,258 +55,8 @@ class SimpleOzoneCPU : public OzoneCPU<SimpleImpl>
//
// OzoneCPU Simulation Object
//
BEGIN_DECLARE_SIM_OBJECT_PARAMS(SimpleOzoneCPU)
Param<int> clock;
Param<int> numThreads;
#if FULL_SYSTEM
SimObjectParam<System *> system;
Param<int> cpu_id;
SimObjectParam<TheISA::ITB *> itb;
SimObjectParam<TheISA::DTB *> dtb;
#else
SimObjectVectorParam<Process *> workload;
//SimObjectParam<PageTable *> page_table;
#endif // FULL_SYSTEM
SimObjectParam<FunctionalMemory *> mem;
SimObjectParam<BaseCPU *> checker;
Param<Counter> max_insts_any_thread;
Param<Counter> max_insts_all_threads;
Param<Counter> max_loads_any_thread;
Param<Counter> max_loads_all_threads;
SimObjectParam<BaseCache *> icache;
SimObjectParam<BaseCache *> dcache;
Param<unsigned> cachePorts;
Param<unsigned> width;
Param<unsigned> frontEndWidth;
Param<unsigned> backEndWidth;
Param<unsigned> backEndSquashLatency;
Param<unsigned> backEndLatency;
Param<unsigned> maxInstBufferSize;
Param<unsigned> numPhysicalRegs;
Param<unsigned> decodeToFetchDelay;
Param<unsigned> renameToFetchDelay;
Param<unsigned> iewToFetchDelay;
Param<unsigned> commitToFetchDelay;
Param<unsigned> fetchWidth;
Param<unsigned> renameToDecodeDelay;
Param<unsigned> iewToDecodeDelay;
Param<unsigned> commitToDecodeDelay;
Param<unsigned> fetchToDecodeDelay;
Param<unsigned> decodeWidth;
Param<unsigned> iewToRenameDelay;
Param<unsigned> commitToRenameDelay;
Param<unsigned> decodeToRenameDelay;
Param<unsigned> renameWidth;
Param<unsigned> commitToIEWDelay;
Param<unsigned> renameToIEWDelay;
Param<unsigned> issueToExecuteDelay;
Param<unsigned> issueWidth;
Param<unsigned> executeWidth;
Param<unsigned> executeIntWidth;
Param<unsigned> executeFloatWidth;
Param<unsigned> executeBranchWidth;
Param<unsigned> executeMemoryWidth;
Param<unsigned> iewToCommitDelay;
Param<unsigned> renameToROBDelay;
Param<unsigned> commitWidth;
Param<unsigned> squashWidth;
Param<std::string> predType;
Param<unsigned> localPredictorSize;
Param<unsigned> localCtrBits;
Param<unsigned> localHistoryTableSize;
Param<unsigned> localHistoryBits;
Param<unsigned> globalPredictorSize;
Param<unsigned> globalCtrBits;
Param<unsigned> globalHistoryBits;
Param<unsigned> choicePredictorSize;
Param<unsigned> choiceCtrBits;
Param<unsigned> BTBEntries;
Param<unsigned> BTBTagSize;
Param<unsigned> RASSize;
Param<unsigned> LQEntries;
Param<unsigned> SQEntries;
Param<unsigned> LFSTSize;
Param<unsigned> SSITSize;
Param<unsigned> numPhysIntRegs;
Param<unsigned> numPhysFloatRegs;
Param<unsigned> numIQEntries;
Param<unsigned> numROBEntries;
Param<bool> decoupledFrontEnd;
Param<int> dispatchWidth;
Param<int> wbWidth;
Param<unsigned> smtNumFetchingThreads;
Param<std::string> smtFetchPolicy;
Param<std::string> smtLSQPolicy;
Param<unsigned> smtLSQThreshold;
Param<std::string> smtIQPolicy;
Param<unsigned> smtIQThreshold;
Param<std::string> smtROBPolicy;
Param<unsigned> smtROBThreshold;
Param<std::string> smtCommitPolicy;
Param<unsigned> instShiftAmt;
Param<bool> defer_registration;
Param<bool> function_trace;
Param<Tick> function_trace_start;
END_DECLARE_SIM_OBJECT_PARAMS(SimpleOzoneCPU)
BEGIN_INIT_SIM_OBJECT_PARAMS(SimpleOzoneCPU)
INIT_PARAM(clock, "clock speed"),
INIT_PARAM(numThreads, "number of HW thread contexts"),
#if FULL_SYSTEM
INIT_PARAM(system, "System object"),
INIT_PARAM(cpu_id, "processor ID"),
INIT_PARAM(itb, "Instruction translation buffer"),
INIT_PARAM(dtb, "Data translation buffer"),
#else
INIT_PARAM(workload, "Processes to run"),
// INIT_PARAM(page_table, "Page table"),
#endif // FULL_SYSTEM
INIT_PARAM_DFLT(mem, "Memory", NULL),
INIT_PARAM_DFLT(checker, "Checker CPU", NULL),
INIT_PARAM_DFLT(max_insts_any_thread,
"Terminate when any thread reaches this inst count",
0),
INIT_PARAM_DFLT(max_insts_all_threads,
"Terminate when all threads have reached"
"this inst count",
0),
INIT_PARAM_DFLT(max_loads_any_thread,
"Terminate when any thread reaches this load count",
0),
INIT_PARAM_DFLT(max_loads_all_threads,
"Terminate when all threads have reached this load"
"count",
0),
INIT_PARAM_DFLT(icache, "L1 instruction cache", NULL),
INIT_PARAM_DFLT(dcache, "L1 data cache", NULL),
INIT_PARAM_DFLT(cachePorts, "Cache Ports", 200),
INIT_PARAM_DFLT(width, "Width", 1),
INIT_PARAM_DFLT(frontEndWidth, "Front end width", 1),
INIT_PARAM_DFLT(backEndWidth, "Back end width", 1),
INIT_PARAM_DFLT(backEndSquashLatency, "Back end squash latency", 1),
INIT_PARAM_DFLT(backEndLatency, "Back end latency", 1),
INIT_PARAM_DFLT(maxInstBufferSize, "Maximum instruction buffer size", 16),
INIT_PARAM(numPhysicalRegs, "Number of physical registers"),
INIT_PARAM(decodeToFetchDelay, "Decode to fetch delay"),
INIT_PARAM(renameToFetchDelay, "Rename to fetch delay"),
INIT_PARAM(iewToFetchDelay, "Issue/Execute/Writeback to fetch"
"delay"),
INIT_PARAM(commitToFetchDelay, "Commit to fetch delay"),
INIT_PARAM(fetchWidth, "Fetch width"),
INIT_PARAM(renameToDecodeDelay, "Rename to decode delay"),
INIT_PARAM(iewToDecodeDelay, "Issue/Execute/Writeback to decode"
"delay"),
INIT_PARAM(commitToDecodeDelay, "Commit to decode delay"),
INIT_PARAM(fetchToDecodeDelay, "Fetch to decode delay"),
INIT_PARAM(decodeWidth, "Decode width"),
INIT_PARAM(iewToRenameDelay, "Issue/Execute/Writeback to rename"
"delay"),
INIT_PARAM(commitToRenameDelay, "Commit to rename delay"),
INIT_PARAM(decodeToRenameDelay, "Decode to rename delay"),
INIT_PARAM(renameWidth, "Rename width"),
INIT_PARAM(commitToIEWDelay, "Commit to "
"Issue/Execute/Writeback delay"),
INIT_PARAM(renameToIEWDelay, "Rename to "
"Issue/Execute/Writeback delay"),
INIT_PARAM(issueToExecuteDelay, "Issue to execute delay (internal"
"to the IEW stage)"),
INIT_PARAM(issueWidth, "Issue width"),
INIT_PARAM(executeWidth, "Execute width"),
INIT_PARAM(executeIntWidth, "Integer execute width"),
INIT_PARAM(executeFloatWidth, "Floating point execute width"),
INIT_PARAM(executeBranchWidth, "Branch execute width"),
INIT_PARAM(executeMemoryWidth, "Memory execute width"),
INIT_PARAM(iewToCommitDelay, "Issue/Execute/Writeback to commit "
"delay"),
INIT_PARAM(renameToROBDelay, "Rename to reorder buffer delay"),
INIT_PARAM(commitWidth, "Commit width"),
INIT_PARAM(squashWidth, "Squash width"),
INIT_PARAM(predType, "Type of branch predictor ('local', 'tournament')"),
INIT_PARAM(localPredictorSize, "Size of local predictor"),
INIT_PARAM(localCtrBits, "Bits per counter"),
INIT_PARAM(localHistoryTableSize, "Size of local history table"),
INIT_PARAM(localHistoryBits, "Bits for the local history"),
INIT_PARAM(globalPredictorSize, "Size of global predictor"),
INIT_PARAM(globalCtrBits, "Bits per counter"),
INIT_PARAM(globalHistoryBits, "Bits of history"),
INIT_PARAM(choicePredictorSize, "Size of choice predictor"),
INIT_PARAM(choiceCtrBits, "Bits of choice counters"),
INIT_PARAM(BTBEntries, "Number of BTB entries"),
INIT_PARAM(BTBTagSize, "Size of the BTB tags, in bits"),
INIT_PARAM(RASSize, "RAS size"),
INIT_PARAM(LQEntries, "Number of load queue entries"),
INIT_PARAM(SQEntries, "Number of store queue entries"),
INIT_PARAM(LFSTSize, "Last fetched store table size"),
INIT_PARAM(SSITSize, "Store set ID table size"),
INIT_PARAM(numPhysIntRegs, "Number of physical integer registers"),
INIT_PARAM(numPhysFloatRegs, "Number of physical floating point "
"registers"),
INIT_PARAM(numIQEntries, "Number of instruction queue entries"),
INIT_PARAM(numROBEntries, "Number of reorder buffer entries"),
INIT_PARAM_DFLT(decoupledFrontEnd, "Decoupled front end", true),
INIT_PARAM_DFLT(dispatchWidth, "Dispatch width", 0),
INIT_PARAM_DFLT(wbWidth, "Writeback width", 0),
INIT_PARAM_DFLT(smtNumFetchingThreads, "SMT Number of Fetching Threads", 1),
INIT_PARAM_DFLT(smtFetchPolicy, "SMT Fetch Policy", "SingleThread"),
INIT_PARAM_DFLT(smtLSQPolicy, "SMT LSQ Sharing Policy", "Partitioned"),
INIT_PARAM_DFLT(smtLSQThreshold,"SMT LSQ Threshold", 100),
INIT_PARAM_DFLT(smtIQPolicy, "SMT IQ Policy", "Partitioned"),
INIT_PARAM_DFLT(smtIQThreshold, "SMT IQ Threshold", 100),
INIT_PARAM_DFLT(smtROBPolicy, "SMT ROB Sharing Policy", "Partitioned"),
INIT_PARAM_DFLT(smtROBThreshold,"SMT ROB Threshold", 100),
INIT_PARAM_DFLT(smtCommitPolicy,"SMT Commit Fetch Policy", "RoundRobin"),
INIT_PARAM(instShiftAmt, "Number of bits to shift instructions by"),
INIT_PARAM(defer_registration, "defer system registration (for sampling)"),
INIT_PARAM(function_trace, "Enable function trace"),
INIT_PARAM(function_trace_start, "Cycle to start function trace")
END_INIT_SIM_OBJECT_PARAMS(SimpleOzoneCPU)
CREATE_SIM_OBJECT(SimpleOzoneCPU)
SimpleOzoneCPU *
SimpleOzoneCPUParams::create()
{
SimpleOzoneCPU *cpu;
@ -329,7 +79,7 @@ CREATE_SIM_OBJECT(SimpleOzoneCPU)
params->clock = clock;
params->name = getInstanceName();
params->name = name;
params->numberOfThreads = actual_num_threads;
#if FULL_SYSTEM
@ -447,6 +197,3 @@ CREATE_SIM_OBJECT(SimpleOzoneCPU)
return cpu;
}
REGISTER_SIM_OBJECT("SimpleOzoneCPU", SimpleOzoneCPU)

85
src/cpu/simple/atomic.cc
View file

@ -36,7 +36,7 @@
#include "cpu/simple/atomic.hh"
#include "mem/packet.hh"
#include "mem/packet_access.hh"
#include "sim/builder.hh"
#include "params/AtomicSimpleCPU.hh"
#include "sim/system.hh"
using namespace std;
@ -184,7 +184,7 @@ void
AtomicSimpleCPU::resume()
{
if (_status != SwitchedOut && _status != Idle) {
assert(system->getMemoryMode() == System::Atomic);
assert(system->getMemoryMode() == Enums::atomic);
changeState(SimObject::Running);
if (thread->status() == ThreadContext::Active) {
@ -548,79 +548,11 @@ AtomicSimpleCPU::tick()
//
// AtomicSimpleCPU Simulation Object
//
BEGIN_DECLARE_SIM_OBJECT_PARAMS(AtomicSimpleCPU)
Param<Counter> max_insts_any_thread;
Param<Counter> max_insts_all_threads;
Param<Counter> max_loads_any_thread;
Param<Counter> max_loads_all_threads;
Param<Tick> progress_interval;
SimObjectParam<System *> system;
Param<int> cpu_id;
#if FULL_SYSTEM
SimObjectParam<TheISA::ITB *> itb;
SimObjectParam<TheISA::DTB *> dtb;
Param<Tick> profile;
Param<bool> do_quiesce;
Param<bool> do_checkpoint_insts;
Param<bool> do_statistics_insts;
#else
SimObjectParam<Process *> workload;
#endif // FULL_SYSTEM
Param<int> clock;
Param<int> phase;
Param<bool> defer_registration;
Param<int> width;
Param<bool> function_trace;
Param<Tick> function_trace_start;
Param<bool> simulate_stalls;
END_DECLARE_SIM_OBJECT_PARAMS(AtomicSimpleCPU)
BEGIN_INIT_SIM_OBJECT_PARAMS(AtomicSimpleCPU)
INIT_PARAM(max_insts_any_thread,
"terminate when any thread reaches this inst count"),
INIT_PARAM(max_insts_all_threads,
"terminate when all threads have reached this inst count"),
INIT_PARAM(max_loads_any_thread,
"terminate when any thread reaches this load count"),
INIT_PARAM(max_loads_all_threads,
"terminate when all threads have reached this load count"),
INIT_PARAM(progress_interval, "Progress interval"),
INIT_PARAM(system, "system object"),
INIT_PARAM(cpu_id, "processor ID"),
#if FULL_SYSTEM
INIT_PARAM(itb, "Instruction TLB"),
INIT_PARAM(dtb, "Data TLB"),
INIT_PARAM(profile, ""),
INIT_PARAM(do_quiesce, ""),
INIT_PARAM(do_checkpoint_insts, ""),
INIT_PARAM(do_statistics_insts, ""),
#else
INIT_PARAM(workload, "processes to run"),
#endif // FULL_SYSTEM
INIT_PARAM(clock, "clock speed"),
INIT_PARAM_DFLT(phase, "clock phase", 0),
INIT_PARAM(defer_registration, "defer system registration (for sampling)"),
INIT_PARAM(width, "cpu width"),
INIT_PARAM(function_trace, "Enable function trace"),
INIT_PARAM(function_trace_start, "Cycle to start function trace"),
INIT_PARAM(simulate_stalls, "Simulate cache stall cycles")
END_INIT_SIM_OBJECT_PARAMS(AtomicSimpleCPU)
CREATE_SIM_OBJECT(AtomicSimpleCPU)
AtomicSimpleCPU *
AtomicSimpleCPUParams::create()
{
AtomicSimpleCPU::Params *params = new AtomicSimpleCPU::Params();
params->name = getInstanceName();
params->name = name;
params->numberOfThreads = 1;
params->max_insts_any_thread = max_insts_any_thread;
params->max_insts_all_threads = max_insts_all_threads;
@ -645,12 +577,11 @@ CREATE_SIM_OBJECT(AtomicSimpleCPU)
params->do_checkpoint_insts = do_checkpoint_insts;
params->do_statistics_insts = do_statistics_insts;
#else
params->process = workload;
if (workload.size() != 1)
panic("only one workload allowed");
params->process = workload[0];
#endif
AtomicSimpleCPU *cpu = new AtomicSimpleCPU(params);
return cpu;
}
REGISTER_SIM_OBJECT("AtomicSimpleCPU", AtomicSimpleCPU)

1
src/cpu/simple/base.cc
View file

@ -47,7 +47,6 @@
#include "cpu/static_inst.hh"
#include "cpu/thread_context.hh"
#include "mem/packet.hh"
#include "sim/builder.hh"
#include "sim/byteswap.hh"
#include "sim/debug.hh"
#include "sim/host.hh"

85
src/cpu/simple/timing.cc
View file

@ -35,7 +35,7 @@
#include "cpu/simple/timing.hh"
#include "mem/packet.hh"
#include "mem/packet_access.hh"
#include "sim/builder.hh"
#include "params/TimingSimpleCPU.hh"
#include "sim/system.hh"
using namespace std;
@ -158,7 +158,7 @@ void
TimingSimpleCPU::resume()
{
if (_status != SwitchedOut && _status != Idle) {
assert(system->getMemoryMode() == System::Timing);
assert(system->getMemoryMode() == Enums::timing);
// Delete the old event if it existed.
if (fetchEvent) {
@ -707,79 +707,11 @@ TimingSimpleCPU::DcachePort::recvRetry()
//
// TimingSimpleCPU Simulation Object
//
BEGIN_DECLARE_SIM_OBJECT_PARAMS(TimingSimpleCPU)
Param<Counter> max_insts_any_thread;
Param<Counter> max_insts_all_threads;
Param<Counter> max_loads_any_thread;
Param<Counter> max_loads_all_threads;
Param<Tick> progress_interval;
SimObjectParam<System *> system;
Param<int> cpu_id;
#if FULL_SYSTEM
SimObjectParam<TheISA::ITB *> itb;
SimObjectParam<TheISA::DTB *> dtb;
Param<Tick> profile;
Param<bool> do_quiesce;
Param<bool> do_checkpoint_insts;
Param<bool> do_statistics_insts;
#else
SimObjectParam<Process *> workload;
#endif // FULL_SYSTEM
Param<int> clock;
Param<int> phase;
Param<bool> defer_registration;
Param<int> width;
Param<bool> function_trace;
Param<Tick> function_trace_start;
Param<bool> simulate_stalls;
END_DECLARE_SIM_OBJECT_PARAMS(TimingSimpleCPU)
BEGIN_INIT_SIM_OBJECT_PARAMS(TimingSimpleCPU)
INIT_PARAM(max_insts_any_thread,
"terminate when any thread reaches this inst count"),
INIT_PARAM(max_insts_all_threads,
"terminate when all threads have reached this inst count"),
INIT_PARAM(max_loads_any_thread,
"terminate when any thread reaches this load count"),
INIT_PARAM(max_loads_all_threads,
"terminate when all threads have reached this load count"),
INIT_PARAM(progress_interval, "Progress interval"),
INIT_PARAM(system, "system object"),
INIT_PARAM(cpu_id, "processor ID"),
#if FULL_SYSTEM
INIT_PARAM(itb, "Instruction TLB"),
INIT_PARAM(dtb, "Data TLB"),
INIT_PARAM(profile, ""),
INIT_PARAM(do_quiesce, ""),
INIT_PARAM(do_checkpoint_insts, ""),
INIT_PARAM(do_statistics_insts, ""),
#else
INIT_PARAM(workload, "processes to run"),
#endif // FULL_SYSTEM
INIT_PARAM(clock, "clock speed"),
INIT_PARAM_DFLT(phase, "clock phase", 0),
INIT_PARAM(defer_registration, "defer system registration (for sampling)"),
INIT_PARAM(width, "cpu width"),
INIT_PARAM(function_trace, "Enable function trace"),
INIT_PARAM(function_trace_start, "Cycle to start function trace"),
INIT_PARAM(simulate_stalls, "Simulate cache stall cycles")
END_INIT_SIM_OBJECT_PARAMS(TimingSimpleCPU)
CREATE_SIM_OBJECT(TimingSimpleCPU)
TimingSimpleCPU *
TimingSimpleCPUParams::create()
{
TimingSimpleCPU::Params *params = new TimingSimpleCPU::Params();
params->name = getInstanceName();
params->name = name;
params->numberOfThreads = 1;
params->max_insts_any_thread = max_insts_any_thread;
params->max_insts_all_threads = max_insts_all_threads;
@ -802,12 +734,11 @@ CREATE_SIM_OBJECT(TimingSimpleCPU)
params->do_checkpoint_insts = do_checkpoint_insts;
params->do_statistics_insts = do_statistics_insts;
#else
params->process = workload;
if (workload.size() != 1)
panic("only one workload allowed");
params->process = workload[0];
#endif
TimingSimpleCPU *cpu = new TimingSimpleCPU(params);
return cpu;
}
REGISTER_SIM_OBJECT("TimingSimpleCPU", TimingSimpleCPU)

6
src/cpu/simple_thread.hh
View file

@ -377,15 +377,17 @@ class SimpleThread : public ThreadState
#if !FULL_SYSTEM
TheISA::IntReg getSyscallArg(int i)
{
assert(i < TheISA::NumArgumentRegs);
return regs.readIntReg(TheISA::flattenIntIndex(getTC(),
TheISA::ArgumentReg0 + i));
TheISA::ArgumentReg[i]));
}
// used to shift args for indirect syscall
void setSyscallArg(int i, TheISA::IntReg val)
{
assert(i < TheISA::NumArgumentRegs);
regs.setIntReg(TheISA::flattenIntIndex(getTC(),
TheISA::ArgumentReg0 + i), val);
TheISA::ArgumentReg[i]), val);
}
void setSyscallReturn(SyscallReturn return_value)

32
src/cpu/trace/opt_cpu.cc
View file

@ -38,8 +38,7 @@
#include "cpu/trace/opt_cpu.hh"
#include "cpu/trace/reader/mem_trace_reader.hh"
#include "sim/builder.hh"
#include "params/OptCPU.hh"
#include "sim/sim_events.hh"
using namespace std;
@ -211,31 +210,8 @@ OptCPU::TickEvent::description()
}
BEGIN_DECLARE_SIM_OBJECT_PARAMS(OptCPU)
SimObjectParam<MemTraceReader *> data_trace;
Param<int> size;
Param<int> block_size;
Param<int> assoc;
END_DECLARE_SIM_OBJECT_PARAMS(OptCPU)
BEGIN_INIT_SIM_OBJECT_PARAMS(OptCPU)
INIT_PARAM_DFLT(data_trace, "memory trace", NULL),
INIT_PARAM(size, "cache size"),
INIT_PARAM(block_size, "block size"),
INIT_PARAM(assoc,"associativity")
END_INIT_SIM_OBJECT_PARAMS(OptCPU)
CREATE_SIM_OBJECT(OptCPU)
OptCPU *
OptCPUParams::create()
{
return new OptCPU(getInstanceName(),
data_trace,
block_size,
size,
assoc);
return new OptCPU(name, data_trace, block_size, size, assoc);
}
REGISTER_SIM_OBJECT("OptCPU", OptCPU)

25
src/cpu/trace/reader/ibm_reader.cc
View file

@ -34,9 +34,9 @@
*/
#include <sstream>
#include "cpu/trace/reader/ibm_reader.hh"
#include "sim/builder.hh"
#include "base/misc.hh" // for fatal
#include "cpu/trace/reader/ibm_reader.hh"
#include "params/IBMReader.hh"
using namespace std;
@ -100,23 +100,8 @@ IBMReader::getNextReq(MemReqPtr &req)
return 0;
}
BEGIN_DECLARE_SIM_OBJECT_PARAMS(IBMReader)
Param<string> filename;
END_DECLARE_SIM_OBJECT_PARAMS(IBMReader)
BEGIN_INIT_SIM_OBJECT_PARAMS(IBMReader)
INIT_PARAM(filename, "trace file")
END_INIT_SIM_OBJECT_PARAMS(IBMReader)
CREATE_SIM_OBJECT(IBMReader)
IBMReader *
IBMReaderParams::create()
{
return new IBMReader(getInstanceName(), filename);
return new IBMReader(name, filename);
}
REGISTER_SIM_OBJECT("IBMReader", IBMReader)

25
src/cpu/trace/reader/itx_reader.cc
View file

@ -34,9 +34,9 @@
*/
#include <sstream>
#include "cpu/trace/reader/itx_reader.hh"
#include "sim/builder.hh"
#include "base/misc.hh" // for fatal
#include "cpu/trace/reader/itx_reader.hh"
#include "params/ITXReader.hh"
using namespace std;
@ -186,23 +186,8 @@ ITXReader::getNextReq(MemReqPtr &req)
return 0;
}
BEGIN_DECLARE_SIM_OBJECT_PARAMS(ITXReader)
Param<string> filename;
END_DECLARE_SIM_OBJECT_PARAMS(ITXReader)
BEGIN_INIT_SIM_OBJECT_PARAMS(ITXReader)
INIT_PARAM(filename, "trace file")
END_INIT_SIM_OBJECT_PARAMS(ITXReader)
CREATE_SIM_OBJECT(ITXReader)
ITXReader *
ITXReaderParams::create()
{
return new ITXReader(getInstanceName(), filename);
return new ITXReader(name, filename);
}
REGISTER_SIM_OBJECT("ITXReader", ITXReader)

23
src/cpu/trace/reader/m5_reader.cc
View file

@ -36,7 +36,7 @@
#include "cpu/trace/reader/m5_reader.hh"
#include "mem/trace/m5_format.hh"
#include "mem/mem_cmd.hh"
#include "sim/builder.hh"
#include "params/M5Reader.hh"
using namespace std;
@ -77,23 +77,8 @@ M5Reader::getNextReq(MemReqPtr &req)
return ref.cycle;
}
BEGIN_DECLARE_SIM_OBJECT_PARAMS(M5Reader)
Param<string> filename;
END_DECLARE_SIM_OBJECT_PARAMS(M5Reader)
BEGIN_INIT_SIM_OBJECT_PARAMS(M5Reader)
INIT_PARAM(filename, "trace file")
END_INIT_SIM_OBJECT_PARAMS(M5Reader)
CREATE_SIM_OBJECT(M5Reader)
M5Reader *
M5ReaderParams::create()
{
return new M5Reader(getInstanceName(), filename);
return new M5Reader(name, filename);
}
REGISTER_SIM_OBJECT("M5Reader", M5Reader)

28
src/cpu/trace/trace_cpu.cc
View file

@ -40,7 +40,7 @@
#include "cpu/trace/reader/mem_trace_reader.hh"
#include "mem/base_mem.hh" // For PARAM constructor
#include "mem/mem_interface.hh"
#include "sim/builder.hh"
#include "params/TraceCPU.hh"
#include "sim/sim_events.hh"
using namespace std;
@ -151,31 +151,11 @@ TraceCPU::TickEvent::description()
return "TraceCPU tick";
}
BEGIN_DECLARE_SIM_OBJECT_PARAMS(TraceCPU)
SimObjectParam<BaseMem *> icache;
SimObjectParam<BaseMem *> dcache;
SimObjectParam<MemTraceReader *> data_trace;
END_DECLARE_SIM_OBJECT_PARAMS(TraceCPU)
BEGIN_INIT_SIM_OBJECT_PARAMS(TraceCPU)
INIT_PARAM_DFLT(icache, "instruction cache", NULL),
INIT_PARAM_DFLT(dcache, "data cache", NULL),
INIT_PARAM_DFLT(data_trace, "data trace", NULL)
END_INIT_SIM_OBJECT_PARAMS(TraceCPU)
CREATE_SIM_OBJECT(TraceCPU)
TraceCPU *
TraceCPUParams::create()
{
return new TraceCPU(getInstanceName(),
return new TraceCPU(name,
(icache) ? icache->getInterface() : NULL,
(dcache) ? dcache->getInterface() : NULL,
data_trace);
}
REGISTER_SIM_OBJECT("TraceCPU", TraceCPU)

5
src/dev/Ethernet.py
View file

@ -180,6 +180,8 @@ class SinicPciData(PciConfigData):
class Sinic(EtherDevBase):
type = 'Sinic'
cxx_namespace = 'Sinic'
cxx_class = 'Device'
rx_max_copy = Param.MemorySize('1514B', "rx max copy")
tx_max_copy = Param.MemorySize('16kB', "tx max copy")
@ -197,4 +199,7 @@ class Sinic(EtherDevBase):
class SinicInt(EtherInt):
type = 'SinicInt'
cxx_namespace = 'Sinic'
cxx_class = 'Interface'
device = Param.Sinic("Ethernet device of this interface")

2
src/dev/SConscript
View file

@ -63,6 +63,6 @@ if env['FULL_SYSTEM']:
Source('platform.cc')
Source('simconsole.cc')
Source('simple_disk.cc')
#Source('sinic.cc')
Source('sinic.cc')
Source('uart.cc')
Source('uart8250.cc')

49
src/dev/alpha/console.cc
View file

@ -51,15 +51,15 @@
#include "mem/packet.hh"
#include "mem/packet_access.hh"
#include "mem/physical.hh"
#include "sim/builder.hh"
#include "params/AlphaConsole.hh"
#include "sim/sim_object.hh"
using namespace std;
using namespace AlphaISA;
AlphaConsole::AlphaConsole(Params *p)
: BasicPioDevice(p), disk(p->disk),
console(params()->cons), system(params()->alpha_sys), cpu(params()->cpu)
AlphaConsole::AlphaConsole(const Params *p)
: BasicPioDevice(p), disk(p->disk), console(p->sim_console),
system(p->system), cpu(p->cpu)
{
pioSize = sizeof(struct AlphaAccess);
@ -303,43 +303,8 @@ AlphaConsole::unserialize(Checkpoint *cp, const std::string &section)
alphaAccess->unserialize(cp, section);
}
BEGIN_DECLARE_SIM_OBJECT_PARAMS(AlphaConsole)
SimObjectParam<SimConsole *> sim_console;
SimObjectParam<SimpleDisk *> disk;
Param<Addr> pio_addr;
SimObjectParam<AlphaSystem *> system;
SimObjectParam<BaseCPU *> cpu;
SimObjectParam<Platform *> platform;
Param<Tick> pio_latency;
END_DECLARE_SIM_OBJECT_PARAMS(AlphaConsole)
BEGIN_INIT_SIM_OBJECT_PARAMS(AlphaConsole)
INIT_PARAM(sim_console, "The Simulator Console"),
INIT_PARAM(disk, "Simple Disk"),
INIT_PARAM(pio_addr, "Device Address"),
INIT_PARAM(system, "system object"),
INIT_PARAM(cpu, "Processor"),
INIT_PARAM(platform, "platform"),
INIT_PARAM_DFLT(pio_latency, "Programmed IO latency", 1000)
END_INIT_SIM_OBJECT_PARAMS(AlphaConsole)
CREATE_SIM_OBJECT(AlphaConsole)
AlphaConsole *
AlphaConsoleParams::create()
{
AlphaConsole::Params *p = new AlphaConsole::Params;
p->name = getInstanceName();
p->platform = platform;
p->pio_addr = pio_addr;
p->pio_delay = pio_latency;
p->cons = sim_console;
p->disk = disk;
p->alpha_sys = system;
p->system = system;
p->cpu = cpu;
return new AlphaConsole(p);
return new AlphaConsole(this);
}
REGISTER_SIM_OBJECT("AlphaConsole", AlphaConsole)

21
src/dev/alpha/console.hh
View file

@ -38,6 +38,7 @@
#include "base/range.hh"
#include "dev/alpha/access.h"
#include "dev/io_device.hh"
#include "params/AlphaConsole.hh"
#include "sim/host.hh"
#include "sim/sim_object.hh"
@ -98,20 +99,14 @@ class AlphaConsole : public BasicPioDevice
BaseCPU *cpu;
public:
struct Params : public BasicPioDevice::Params
typedef AlphaConsoleParams Params;
AlphaConsole(const Params *p);
const Params *
params() const
{
SimConsole *cons;
SimpleDisk *disk;
AlphaSystem *alpha_sys;
BaseCPU *cpu;
};
protected:
const Params *params() const {return (const Params *)_params; }
public:
/** Standard Constructor */
AlphaConsole(Params *p);
return dynamic_cast<const Params *>(_params);
}
virtual void startup();

23
src/dev/alpha/tsunami.cc
View file

@ -42,7 +42,7 @@
#include "dev/alpha/tsunami_pchip.hh"
#include "dev/alpha/tsunami_io.hh"
#include "dev/alpha/tsunami.hh"
#include "sim/builder.hh"
#include "params/Tsunami.hh"
#include "sim/system.hh"
using namespace std;
@ -114,23 +114,8 @@ Tsunami::unserialize(Checkpoint *cp, const std::string &section)
UNSERIALIZE_ARRAY(intr_sum_type, Tsunami::Max_CPUs);
}
BEGIN_DECLARE_SIM_OBJECT_PARAMS(Tsunami)
SimObjectParam<System *> system;
SimObjectParam<IntrControl *> intrctrl;
END_DECLARE_SIM_OBJECT_PARAMS(Tsunami)
BEGIN_INIT_SIM_OBJECT_PARAMS(Tsunami)
INIT_PARAM(system, "system"),
INIT_PARAM(intrctrl, "interrupt controller")
END_INIT_SIM_OBJECT_PARAMS(Tsunami)
CREATE_SIM_OBJECT(Tsunami)
Tsunami *
TsunamiParams::create()
{
return new Tsunami(getInstanceName(), system, intrctrl);
return new Tsunami(name, system, intrctrl);
}
REGISTER_SIM_OBJECT("Tsunami", Tsunami)

38
src/dev/alpha/tsunami_cchip.cc
View file

@ -47,14 +47,14 @@
#include "mem/packet.hh"
#include "mem/packet_access.hh"
#include "mem/port.hh"
#include "sim/builder.hh"
#include "params/TsunamiCChip.hh"
#include "sim/system.hh"
using namespace std;
//Should this be AlphaISA?
using namespace TheISA;
TsunamiCChip::TsunamiCChip(Params *p)
TsunamiCChip::TsunamiCChip(const Params *p)
: BasicPioDevice(p), tsunami(p->tsunami)
{
pioSize = 0x10000000;
@ -521,36 +521,8 @@ TsunamiCChip::unserialize(Checkpoint *cp, const std::string &section)
UNSERIALIZE_SCALAR(drir);
}
BEGIN_DECLARE_SIM_OBJECT_PARAMS(TsunamiCChip)
Param<Addr> pio_addr;
Param<Tick> pio_latency;
SimObjectParam<Platform *> platform;
SimObjectParam<System *> system;
SimObjectParam<Tsunami *> tsunami;
END_DECLARE_SIM_OBJECT_PARAMS(TsunamiCChip)
BEGIN_INIT_SIM_OBJECT_PARAMS(TsunamiCChip)
INIT_PARAM(pio_addr, "Device Address"),
INIT_PARAM(pio_latency, "Programmed IO latency"),
INIT_PARAM(platform, "platform"),
INIT_PARAM(system, "system object"),
INIT_PARAM(tsunami, "Tsunami")
END_INIT_SIM_OBJECT_PARAMS(TsunamiCChip)
CREATE_SIM_OBJECT(TsunamiCChip)
TsunamiCChip *
TsunamiCChipParams::create()
{
TsunamiCChip::Params *p = new TsunamiCChip::Params;
p->name = getInstanceName();
p->pio_addr = pio_addr;
p->pio_delay = pio_latency;
p->platform = platform;
p->system = system;
p->tsunami = tsunami;
return new TsunamiCChip(p);
return new TsunamiCChip(this);
}
REGISTER_SIM_OBJECT("TsunamiCChip", TsunamiCChip)

21
src/dev/alpha/tsunami_cchip.hh
View file

@ -35,10 +35,10 @@
#ifndef __TSUNAMI_CCHIP_HH__
#define __TSUNAMI_CCHIP_HH__
#include "dev/alpha/tsunami.hh"
#include "base/range.hh"
#include "dev/alpha/tsunami.hh"
#include "dev/io_device.hh"
#include "params/TsunamiCChip.hh"
/**
* Tsunami CChip CSR Emulation. This device includes all the interrupt
@ -79,20 +79,19 @@ class TsunamiCChip : public BasicPioDevice
uint64_t itint;
public:
struct Params : public BasicPioDevice::Params
{
Tsunami *tsunami;
};
protected:
const Params *params() const {return (const Params *)_params; }
public:
typedef TsunamiCChipParams Params;
/**
* Initialize the Tsunami CChip by setting all of the
* device register to 0.
* @param p params struct
*/
TsunamiCChip(Params *p);
TsunamiCChip(const Params *p);
const Params *
params() const
{
return dynamic_cast<const Params *>(_params);
}
virtual Tick read(PacketPtr pkt);

77
src/dev/alpha/tsunami_io.cc
View file

@ -40,6 +40,7 @@
#include <string>
#include <vector>
#include "base/time.hh"
#include "base/trace.hh"
#include "dev/pitreg.h"
#include "dev/rtcreg.h"
@ -50,27 +51,23 @@
#include "mem/packet.hh"
#include "mem/packet_access.hh"
#include "mem/port.hh"
#include "sim/builder.hh"
#include "sim/system.hh"
using namespace std;
//Should this be AlphaISA?
using namespace TheISA;
TsunamiIO::RTC::RTC(const string &n, Tsunami* tsunami, const vector<int> &t,
bool bcd, Tick i)
: _name(n), event(tsunami, i), addr(0), year_is_bcd(bcd)
TsunamiIO::RTC::RTC(const string &n, Tsunami* tsunami,
const TsunamiIO::Params *p)
: _name(n), event(tsunami, p->frequency), addr(0)
{
memset(clock_data, 0, sizeof(clock_data));
stat_regA = RTCA_32768HZ | RTCA_1024HZ;
stat_regB = RTCB_PRDC_IE |RTCB_BIN | RTCB_24HR;
struct tm tm;
parseTime(t, &tm);
year = p->time.tm_year;
year = tm.tm_year;
if (year_is_bcd) {
if (p->year_is_bcd) {
// The datasheet says that the year field can be either BCD or
// years since 1900. Linux seems to be happy with years since
// 1900.
@ -81,16 +78,16 @@ TsunamiIO::RTC::RTC(const string &n, Tsunami* tsunami, const vector<int> &t,
}
// Unix is 0-11 for month, data seet says start at 1
mon = tm.tm_mon + 1;
mday = tm.tm_mday;
hour = tm.tm_hour;
min = tm.tm_min;
sec = tm.tm_sec;
mon = p->time.tm_mon + 1;
mday = p->time.tm_mday;
hour = p->time.tm_hour;
min = p->time.tm_min;
sec = p->time.tm_sec;
// Datasheet says 1 is sunday
wday = tm.tm_wday + 1;
wday = p->time.tm_wday + 1;
DPRINTFN("Real-time clock set to %s", asctime(&tm));
DPRINTFN("Real-time clock set to %s", asctime(&p->time));
}
void
@ -437,10 +434,9 @@ TsunamiIO::PITimer::Counter::CounterEvent::description()
return "tsunami 8254 Interval timer";
}
TsunamiIO::TsunamiIO(Params *p)
TsunamiIO::TsunamiIO(const Params *p)
: BasicPioDevice(p), tsunami(p->tsunami), pitimer(p->name + "pitimer"),
rtc(p->name + ".rtc", p->tsunami, p->init_time, p->year_is_bcd,
p->frequency)
rtc(p->name + ".rtc", p->tsunami, p)
{
pioSize = 0x100;
@ -656,45 +652,8 @@ TsunamiIO::unserialize(Checkpoint *cp, const string &section)
rtc.unserialize("rtc", cp, section);
}
BEGIN_DECLARE_SIM_OBJECT_PARAMS(TsunamiIO)
Param<Addr> pio_addr;
Param<Tick> pio_latency;
Param<Tick> frequency;
SimObjectParam<Platform *> platform;
SimObjectParam<System *> system;
VectorParam<int> time;
Param<bool> year_is_bcd;
SimObjectParam<Tsunami *> tsunami;
END_DECLARE_SIM_OBJECT_PARAMS(TsunamiIO)
BEGIN_INIT_SIM_OBJECT_PARAMS(TsunamiIO)
INIT_PARAM(pio_addr, "Device Address"),
INIT_PARAM(pio_latency, "Programmed IO latency"),
INIT_PARAM(frequency, "clock interrupt frequency"),
INIT_PARAM(platform, "platform"),
INIT_PARAM(system, "system object"),
INIT_PARAM(time, "System time to use (0 for actual time"),
INIT_PARAM(year_is_bcd, ""),
INIT_PARAM(tsunami, "Tsunami")
END_INIT_SIM_OBJECT_PARAMS(TsunamiIO)
CREATE_SIM_OBJECT(TsunamiIO)
TsunamiIO *
TsunamiIOParams::create()
{
TsunamiIO::Params *p = new TsunamiIO::Params;
p->frequency = frequency;
p->name = getInstanceName();
p->pio_addr = pio_addr;
p->pio_delay = pio_latency;
p->platform = platform;
p->system = system;
p->init_time = time;
p->year_is_bcd = year_is_bcd;
p->tsunami = tsunami;
return new TsunamiIO(p);
return new TsunamiIO(this);
}
REGISTER_SIM_OBJECT("TsunamiIO", TsunamiIO)

28
src/dev/alpha/tsunami_io.hh
View file

@ -37,9 +37,10 @@
#ifndef __DEV_TSUNAMI_IO_HH__
#define __DEV_TSUNAMI_IO_HH__
#include "dev/io_device.hh"
#include "base/range.hh"
#include "dev/alpha/tsunami.hh"
#include "dev/io_device.hh"
#include "params/TsunamiIO.hh"
#include "sim/eventq.hh"
/**
@ -85,9 +86,6 @@ class TsunamiIO : public BasicPioDevice
/** Current RTC register address/index */
int addr;
/** should the year be interpreted as BCD? */
bool year_is_bcd;
/** Data for real-time clock function */
union {
uint8_t clock_data[10];
@ -114,7 +112,7 @@ class TsunamiIO : public BasicPioDevice
public:
RTC(const std::string &name, Tsunami* tsunami,
const std::vector<int> &t, bool bcd, Tick i);
const TsunamiIOParams *params);
/** RTC address port: write address of RTC RAM data to access */
void writeAddr(const uint8_t data);
@ -313,23 +311,19 @@ class TsunamiIO : public BasicPioDevice
*/
Tick frequency() const;
struct Params : public BasicPioDevice::Params
{
Tick frequency;
Tsunami *tsunami;
std::vector<int> init_time;
bool year_is_bcd;
};
protected:
const Params *params() const { return (const Params*)_params; }
public:
typedef TsunamiIOParams Params;
/**
* Initialize all the data for devices supported by Tsunami I/O.
* @param p pointer to Params struct
*/
TsunamiIO(Params *p);
TsunamiIO(const Params *p);
const Params *
params() const
{
return dynamic_cast<const Params *>(_params);
}
virtual Tick read(PacketPtr pkt);
virtual Tick write(PacketPtr pkt);

37
src/dev/alpha/tsunami_pchip.cc
View file

@ -43,14 +43,13 @@
#include "dev/alpha/tsunami.hh"
#include "mem/packet.hh"
#include "mem/packet_access.hh"
#include "sim/builder.hh"
#include "sim/system.hh"
using namespace std;
//Should this be AlphaISA?
using namespace TheISA;
TsunamiPChip::TsunamiPChip(Params *p)
TsunamiPChip::TsunamiPChip(const Params *p)
: BasicPioDevice(p)
{
pioSize = 0x1000;
@ -332,36 +331,8 @@ TsunamiPChip::unserialize(Checkpoint *cp, const std::string &section)
}
BEGIN_DECLARE_SIM_OBJECT_PARAMS(TsunamiPChip)
Param<Addr> pio_addr;
Param<Tick> pio_latency;
SimObjectParam<Platform *> platform;
SimObjectParam<System *> system;
SimObjectParam<Tsunami *> tsunami;
END_DECLARE_SIM_OBJECT_PARAMS(TsunamiPChip)
BEGIN_INIT_SIM_OBJECT_PARAMS(TsunamiPChip)
INIT_PARAM(pio_addr, "Device Address"),
INIT_PARAM(pio_latency, "Programmed IO latency"),
INIT_PARAM(platform, "platform"),
INIT_PARAM(system, "system object"),
INIT_PARAM(tsunami, "Tsunami")
END_INIT_SIM_OBJECT_PARAMS(TsunamiPChip)
CREATE_SIM_OBJECT(TsunamiPChip)
TsunamiPChip *
TsunamiPChipParams::create()
{
TsunamiPChip::Params *p = new TsunamiPChip::Params;
p->name = getInstanceName();
p->pio_addr = pio_addr;
p->pio_delay = pio_latency;
p->platform = platform;
p->system = system;
p->tsunami = tsunami;
return new TsunamiPChip(p);
return new TsunamiPChip(this);
}
REGISTER_SIM_OBJECT("TsunamiPChip", TsunamiPChip)

20
src/dev/alpha/tsunami_pchip.hh
View file

@ -35,9 +35,10 @@
#ifndef __TSUNAMI_PCHIP_HH__
#define __TSUNAMI_PCHIP_HH__
#include "dev/alpha/tsunami.hh"
#include "base/range.hh"
#include "dev/alpha/tsunami.hh"
#include "dev/io_device.hh"
#include "params/TsunamiPChip.hh"
/**
* A very simple implementation of the Tsunami PCI interface chips.
@ -61,19 +62,18 @@ class TsunamiPChip : public BasicPioDevice
uint64_t tba[4];
public:
struct Params : public BasicPioDevice::Params
{
Tsunami *tsunami;
};
protected:
const Params *params() const { return (const Params*)_params; }
public:
typedef TsunamiPChipParams Params;
/**
* Register the PChip with the mmu and init all wsba, wsm, and tba to 0
* @param p pointer to the parameters struct
*/
TsunamiPChip(Params *p);
TsunamiPChip(const Params *p);
const Params *
params() const
{
return dynamic_cast<const Params *>(_params);
}
/**
* Translate a PCI bus address to a memory address for DMA.

38
src/dev/baddev.cc
View file

@ -40,14 +40,14 @@
#include "dev/baddev.hh"
#include "dev/platform.hh"
#include "mem/port.hh"
#include "sim/builder.hh"
#include "params/BadDevice.hh"
#include "sim/system.hh"
using namespace std;
using namespace TheISA;
BadDevice::BadDevice(Params *p)
: BasicPioDevice(p), devname(p->device_name)
: BasicPioDevice(p), devname(p->devicename)
{
pioSize = 0x10;
}
@ -66,36 +66,8 @@ BadDevice::write(PacketPtr pkt)
M5_DUMMY_RETURN
}
BEGIN_DECLARE_SIM_OBJECT_PARAMS(BadDevice)
Param<string> devicename;
Param<Addr> pio_addr;
SimObjectParam<System *> system;
SimObjectParam<Platform *> platform;
Param<Tick> pio_latency;
END_DECLARE_SIM_OBJECT_PARAMS(BadDevice)
BEGIN_INIT_SIM_OBJECT_PARAMS(BadDevice)
INIT_PARAM(devicename, "Name of device to error on"),
INIT_PARAM(pio_addr, "Device Address"),
INIT_PARAM(system, "system object"),
INIT_PARAM(platform, "platform"),
INIT_PARAM_DFLT(pio_latency, "Programmed IO latency", 1000)
END_INIT_SIM_OBJECT_PARAMS(BadDevice)
CREATE_SIM_OBJECT(BadDevice)
BadDevice *
BadDeviceParams::create()
{
BadDevice::Params *p = new BadDevice::Params;
p->name =getInstanceName();
p->platform = platform;
p->pio_addr = pio_addr;
p->pio_delay = pio_latency;
p->system = system;
p->device_name = devicename;
return new BadDevice(p);
return new BadDevice(this);
}
REGISTER_SIM_OBJECT("BadDevice", BadDevice)

14
src/dev/baddev.hh
View file

@ -38,7 +38,7 @@
#include "base/range.hh"
#include "dev/io_device.hh"
#include "params/BadDevice.hh"
/**
* BadDevice
@ -52,12 +52,14 @@ class BadDevice : public BasicPioDevice
std::string devname;
public:
struct Params : public BasicPioDevice::Params
{
std::string device_name;
};
typedef BadDeviceParams Params;
protected:
const Params *params() const { return (const Params *)_params; }
const Params *
params() const
{
return dynamic_cast<const Params *>(_params);
}
public:
/**

56
src/dev/disk_image.cc
View file

@ -45,7 +45,8 @@
#include "base/misc.hh"
#include "base/trace.hh"
#include "dev/disk_image.hh"
#include "sim/builder.hh"
#include "params/CowDiskImage.hh"
#include "params/RawDiskImage.hh"
#include "sim/sim_exit.hh"
#include "sim/byteswap.hh"
@ -143,30 +144,12 @@ RawDiskImage::write(const uint8_t *data, off_t offset)
return stream.tellp() - pos;
}
DEFINE_SIM_OBJECT_CLASS_NAME("DiskImage", DiskImage)
BEGIN_DECLARE_SIM_OBJECT_PARAMS(RawDiskImage)
Param<string> image_file;
Param<bool> read_only;
END_DECLARE_SIM_OBJECT_PARAMS(RawDiskImage)
BEGIN_INIT_SIM_OBJECT_PARAMS(RawDiskImage)
INIT_PARAM(image_file, "disk image file"),
INIT_PARAM_DFLT(read_only, "read only image", false)
END_INIT_SIM_OBJECT_PARAMS(RawDiskImage)
CREATE_SIM_OBJECT(RawDiskImage)
RawDiskImage *
RawDiskImageParams::create()
{
return new RawDiskImage(getInstanceName(), image_file, read_only);
return new RawDiskImage(name, image_file, read_only);
}
REGISTER_SIM_OBJECT("RawDiskImage", RawDiskImage)
////////////////////////////////////////////////////////////////////////
//
// Copy on Write Disk image
@ -440,33 +423,12 @@ CowDiskImage::unserialize(Checkpoint *cp, const string &section)
open(cowFilename);
}
BEGIN_DECLARE_SIM_OBJECT_PARAMS(CowDiskImage)
SimObjectParam<DiskImage *> child;
Param<string> image_file;
Param<int> table_size;
Param<bool> read_only;
END_DECLARE_SIM_OBJECT_PARAMS(CowDiskImage)
BEGIN_INIT_SIM_OBJECT_PARAMS(CowDiskImage)
INIT_PARAM(child, "child image"),
INIT_PARAM_DFLT(image_file, "disk image file", ""),
INIT_PARAM_DFLT(table_size, "initial table size", 65536),
INIT_PARAM_DFLT(read_only, "don't write back to the copy-on-write file",
true)
END_INIT_SIM_OBJECT_PARAMS(CowDiskImage)
CREATE_SIM_OBJECT(CowDiskImage)
CowDiskImage *
CowDiskImageParams::create()
{
if (((string)image_file).empty())
return new CowDiskImage(getInstanceName(), child, table_size);
return new CowDiskImage(name, child, table_size);
else
return new CowDiskImage(getInstanceName(), child, table_size,
return new CowDiskImage(name, child, table_size,
image_file, read_only);
}
REGISTER_SIM_OBJECT("CowDiskImage", CowDiskImage)

25
src/dev/etherbus.cc
View file

@ -42,7 +42,7 @@
#include "dev/etherdump.hh"
#include "dev/etherint.hh"
#include "dev/etherpkt.hh"
#include "sim/builder.hh"
#include "params/EtherBus.hh"
#include "sim/core.hh"
using namespace std;
@ -103,25 +103,8 @@ EtherBus::send(EtherInt *sndr, EthPacketPtr &pkt)
return true;
}
BEGIN_DECLARE_SIM_OBJECT_PARAMS(EtherBus)
Param<bool> loopback;
Param<double> speed;
SimObjectParam<EtherDump *> packet_dump;
END_DECLARE_SIM_OBJECT_PARAMS(EtherBus)
BEGIN_INIT_SIM_OBJECT_PARAMS(EtherBus)
INIT_PARAM(loopback, "send the packet back to the sending interface"),
INIT_PARAM(speed, "bus speed in ticks per byte"),
INIT_PARAM(packet_dump, "object to dump network packets to")
END_INIT_SIM_OBJECT_PARAMS(EtherBus)
CREATE_SIM_OBJECT(EtherBus)
EtherBus *
EtherBusParams::create()
{
return new EtherBus(getInstanceName(), speed, loopback, packet_dump);
return new EtherBus(name, speed, loopback, dump);
}
REGISTER_SIM_OBJECT("EtherBus", EtherBus)

23
src/dev/etherdump.cc
View file

@ -40,7 +40,7 @@
#include "base/misc.hh"
#include "base/output.hh"
#include "dev/etherdump.hh"
#include "sim/builder.hh"
#include "params/EtherDump.hh"
#include "sim/core.hh"
using std::string;
@ -116,23 +116,8 @@ EtherDump::dumpPacket(EthPacketPtr &packet)
stream.flush();
}
BEGIN_DECLARE_SIM_OBJECT_PARAMS(EtherDump)
Param<string> file;
Param<int> maxlen;
END_DECLARE_SIM_OBJECT_PARAMS(EtherDump)
BEGIN_INIT_SIM_OBJECT_PARAMS(EtherDump)
INIT_PARAM(file, "file to dump packets to"),
INIT_PARAM(maxlen, "max portion of packet data to dump")
END_INIT_SIM_OBJECT_PARAMS(EtherDump)
CREATE_SIM_OBJECT(EtherDump)
EtherDump *
EtherDumpParams::create()
{
return new EtherDump(getInstanceName(), simout.resolve(file), maxlen);
return new EtherDump(name, simout.resolve(file), maxlen);
}
REGISTER_SIM_OBJECT("EtherDump", EtherDump)

4
src/dev/etherint.cc
View file

@ -30,7 +30,6 @@
#include "dev/etherint.hh"
#include "base/misc.hh"
#include "sim/param.hh"
#include "sim/sim_object.hh"
void
@ -42,6 +41,3 @@ EtherInt::setPeer(EtherInt *p)
peer = p;
}
DEFINE_SIM_OBJECT_CLASS_NAME("EtherInt", EtherInt)

32
src/dev/etherlink.cc
View file

@ -44,7 +44,7 @@
#include "dev/etherint.hh"
#include "dev/etherlink.hh"
#include "dev/etherpkt.hh"
#include "sim/builder.hh"
#include "params/EtherLink.hh"
#include "sim/serialize.hh"
#include "sim/system.hh"
#include "sim/core.hh"
@ -272,32 +272,8 @@ LinkDelayEvent::createForUnserialize(Checkpoint *cp, const string &section)
REGISTER_SERIALIZEABLE("LinkDelayEvent", LinkDelayEvent)
BEGIN_DECLARE_SIM_OBJECT_PARAMS(EtherLink)
SimObjectParam<EtherInt *> int1;
SimObjectParam<EtherInt *> int2;
Param<double> speed;
Param<Tick> delay;
Param<Tick> delay_var;
SimObjectParam<EtherDump *> dump;
END_DECLARE_SIM_OBJECT_PARAMS(EtherLink)
BEGIN_INIT_SIM_OBJECT_PARAMS(EtherLink)
INIT_PARAM(int1, "interface 1"),
INIT_PARAM(int2, "interface 2"),
INIT_PARAM(speed, "link speed in bits per second"),
INIT_PARAM(delay, "transmit delay of packets in us"),
INIT_PARAM(delay_var, "Difference in amount of time to traverse wire"),
INIT_PARAM(dump, "object to dump network packets to")
END_INIT_SIM_OBJECT_PARAMS(EtherLink)
CREATE_SIM_OBJECT(EtherLink)
EtherLink *
EtherLinkParams::create()
{
return new EtherLink(getInstanceName(), int1, int2, speed, delay, delay_var,
dump);
return new EtherLink(name, int1, int2, speed, delay, delay_var, dump);
}
REGISTER_SIM_OBJECT("EtherLink", EtherLink)

28
src/dev/ethertap.cc
View file

@ -50,7 +50,7 @@
#include "dev/etherint.hh"
#include "dev/etherpkt.hh"
#include "dev/ethertap.hh"
#include "sim/builder.hh"
#include "params/EtherTap.hh"
using namespace std;
@ -313,28 +313,10 @@ EtherTap::unserialize(Checkpoint *cp, const std::string &section)
//=====================================================================
BEGIN_DECLARE_SIM_OBJECT_PARAMS(EtherTap)
SimObjectParam<EtherInt *> peer;
SimObjectParam<EtherDump *> dump;
Param<unsigned> port;
Param<unsigned> bufsz;
END_DECLARE_SIM_OBJECT_PARAMS(EtherTap)
BEGIN_INIT_SIM_OBJECT_PARAMS(EtherTap)
INIT_PARAM_DFLT(peer, "peer interface", NULL),
INIT_PARAM_DFLT(dump, "object to dump network packets to", NULL),
INIT_PARAM_DFLT(port, "tap port", 3500),
INIT_PARAM_DFLT(bufsz, "tap buffer size", 10000)
END_INIT_SIM_OBJECT_PARAMS(EtherTap)
CREATE_SIM_OBJECT(EtherTap)
EtherTap *
EtherTapParams::create()
{
EtherTap *tap = new EtherTap(getInstanceName(), dump, port, bufsz);
EtherTap *tap = new EtherTap(name, dump, port, bufsz);
if (peer) {
tap->setPeer(peer);
@ -343,5 +325,3 @@ CREATE_SIM_OBJECT(EtherTap)
return tap;
}
REGISTER_SIM_OBJECT("EtherTap", EtherTap)

105
src/dev/i8254xGBe.cc
View file

@ -40,17 +40,18 @@
* @todo really there are multiple dma engines.. we should implement them.
*/
#include <algorithm>
#include "base/inet.hh"
#include "base/trace.hh"
#include "dev/i8254xGBe.hh"
#include "mem/packet.hh"
#include "mem/packet_access.hh"
#include "sim/builder.hh"
#include "params/IGbE.hh"
#include "params/IGbEInt.hh"
#include "sim/stats.hh"
#include "sim/system.hh"
#include <algorithm>
using namespace iGbReg;
using namespace Net;
@ -1446,24 +1447,10 @@ IGbE::unserialize(Checkpoint *cp, const std::string &section)
rxDescCache.unserialize(cp, csprintf("%s.RxDescCache", section));
}
BEGIN_DECLARE_SIM_OBJECT_PARAMS(IGbEInt)
SimObjectParam<EtherInt *> peer;
SimObjectParam<IGbE *> device;
END_DECLARE_SIM_OBJECT_PARAMS(IGbEInt)
BEGIN_INIT_SIM_OBJECT_PARAMS(IGbEInt)
INIT_PARAM_DFLT(peer, "peer interface", NULL),
INIT_PARAM(device, "Ethernet device of this interface")
END_INIT_SIM_OBJECT_PARAMS(IGbEInt)
CREATE_SIM_OBJECT(IGbEInt)
IGbEInt *
IGbEIntParams::create()
{
IGbEInt *dev_int = new IGbEInt(getInstanceName(), device);
IGbEInt *dev_int = new IGbEInt(name, device);
EtherInt *p = (EtherInt *)peer;
if (p) {
@ -1474,80 +1461,8 @@ CREATE_SIM_OBJECT(IGbEInt)
return dev_int;
}
REGISTER_SIM_OBJECT("IGbEInt", IGbEInt)
BEGIN_DECLARE_SIM_OBJECT_PARAMS(IGbE)
SimObjectParam<System *> system;
SimObjectParam<Platform *> platform;
Param<Tick> min_backoff_delay;
Param<Tick> max_backoff_delay;
SimObjectParam<PciConfigData *> configdata;
Param<uint32_t> pci_bus;
Param<uint32_t> pci_dev;
Param<uint32_t> pci_func;
Param<Tick> pio_latency;
Param<Tick> config_latency;
Param<std::string> hardware_address;
Param<bool> use_flow_control;
Param<int> rx_fifo_size;
Param<int> tx_fifo_size;
Param<int> rx_desc_cache_size;
Param<int> tx_desc_cache_size;
Param<Tick> clock;
END_DECLARE_SIM_OBJECT_PARAMS(IGbE)
BEGIN_INIT_SIM_OBJECT_PARAMS(IGbE)
INIT_PARAM(system, "System pointer"),
INIT_PARAM(platform, "Platform pointer"),
INIT_PARAM(min_backoff_delay, "Minimum delay after receving a nack packed"),
INIT_PARAM(max_backoff_delay, "Maximum delay after receving a nack packed"),
INIT_PARAM(configdata, "PCI Config data"),
INIT_PARAM(pci_bus, "PCI bus ID"),
INIT_PARAM(pci_dev, "PCI device number"),
INIT_PARAM(pci_func, "PCI function code"),
INIT_PARAM_DFLT(pio_latency, "Programmed IO latency in bus cycles", 1),
INIT_PARAM(config_latency, "Number of cycles for a config read or write"),
INIT_PARAM(hardware_address, "Ethernet Hardware Address"),
INIT_PARAM(use_flow_control,"Should the device use xon/off packets"),
INIT_PARAM(rx_fifo_size,"Size of the RX FIFO"),
INIT_PARAM(tx_fifo_size,"Size of the TX FIFO"),
INIT_PARAM(rx_desc_cache_size,"Size of the RX descriptor cache"),
INIT_PARAM(tx_desc_cache_size,"Size of the TX descriptor cache"),
INIT_PARAM(clock,"Clock rate for the device to tick at")
END_INIT_SIM_OBJECT_PARAMS(IGbE)
CREATE_SIM_OBJECT(IGbE)
IGbE *
IGbEParams::create()
{
IGbE::Params *params = new IGbE::Params;
params->name = getInstanceName();
params->platform = platform;
params->system = system;
params->min_backoff_delay = min_backoff_delay;
params->max_backoff_delay = max_backoff_delay;
params->configData = configdata;
params->busNum = pci_bus;
params->deviceNum = pci_dev;
params->functionNum = pci_func;
params->pio_delay = pio_latency;
params->config_delay = config_latency;
params->hardware_address = hardware_address;
params->use_flow_control = use_flow_control;
params->rx_fifo_size = rx_fifo_size;
params->tx_fifo_size = tx_fifo_size;
params->rx_desc_cache_size = rx_desc_cache_size;
params->tx_desc_cache_size = tx_desc_cache_size;
params->clock = clock;
return new IGbE(params);
return new IGbE(this);
}
REGISTER_SIM_OBJECT("IGbE", IGbE)

21
src/dev/i8254xGBe.hh
View file

@ -45,6 +45,7 @@
#include "dev/i8254xGBe_defs.hh"
#include "dev/pcidev.hh"
#include "dev/pktfifo.hh"
#include "params/IGbE.hh"
#include "sim/eventq.hh"
class IGbEInt;
@ -585,19 +586,14 @@ class IGbE : public PciDev
TxDescCache txDescCache;
public:
struct Params : public PciDev::Params
typedef IGbEParams Params;
const Params *
params() const
{
Net::EthAddr hardware_address;
bool use_flow_control;
int rx_fifo_size;
int tx_fifo_size;
int rx_desc_cache_size;
int tx_desc_cache_size;
Tick clock;
};
return dynamic_cast<const Params *>(_params);
}
IGbE(Params *params);
~IGbE() {;}
~IGbE() {}
Tick clock;
inline Tick cycles(int numCycles) const { return numCycles * clock; }
@ -612,9 +608,6 @@ class IGbE : public PciDev
void setEthInt(IGbEInt *i) { assert(!etherInt); etherInt = i; }
const Params *params() const {return (const Params *)_params; }
virtual void serialize(std::ostream &os);
virtual void unserialize(Checkpoint *cp, const std::string &section);
virtual unsigned int drain(Event *de);

58
src/dev/ide_ctrl.cc
View file

@ -44,7 +44,7 @@
#include "dev/platform.hh"
#include "mem/packet.hh"
#include "mem/packet_access.hh"
#include "sim/builder.hh"
#include "params/IdeController.hh"
#include "sim/sim_object.hh"
#include "sim/byteswap.hh"
@ -746,58 +746,8 @@ IdeController::unserialize(Checkpoint *cp, const std::string &section)
sizeof(cmd_in_progress) / sizeof(cmd_in_progress[0]));
}
#ifndef DOXYGEN_SHOULD_SKIP_THIS
BEGIN_DECLARE_SIM_OBJECT_PARAMS(IdeController)
SimObjectParam<System *> system;
SimObjectParam<Platform *> platform;
Param<Tick> min_backoff_delay;
Param<Tick> max_backoff_delay;
SimObjectParam<PciConfigData *> configdata;
Param<uint32_t> pci_bus;
Param<uint32_t> pci_dev;
Param<uint32_t> pci_func;
Param<Tick> pio_latency;
Param<Tick> config_latency;
SimObjectVectorParam<IdeDisk *> disks;
END_DECLARE_SIM_OBJECT_PARAMS(IdeController)
BEGIN_INIT_SIM_OBJECT_PARAMS(IdeController)
INIT_PARAM(system, "System pointer"),
INIT_PARAM(platform, "Platform pointer"),
INIT_PARAM(min_backoff_delay, "Minimum delay after receving a nack packed"),
INIT_PARAM(max_backoff_delay, "Maximum delay after receving a nack packed"),
INIT_PARAM(configdata, "PCI Config data"),
INIT_PARAM(pci_bus, "PCI bus ID"),
INIT_PARAM(pci_dev, "PCI device number"),
INIT_PARAM(pci_func, "PCI function code"),
INIT_PARAM_DFLT(pio_latency, "Programmed IO latency in bus cycles", 1),
INIT_PARAM(config_latency, "Number of cycles for a config read or write"),
INIT_PARAM(disks, "IDE disks attached to this controller")
END_INIT_SIM_OBJECT_PARAMS(IdeController)
CREATE_SIM_OBJECT(IdeController)
IdeController *
IdeControllerParams::create()
{
IdeController::Params *params = new IdeController::Params;
params->name = getInstanceName();
params->platform = platform;
params->system = system;
params->min_backoff_delay = min_backoff_delay;
params->max_backoff_delay = max_backoff_delay;
params->configData = configdata;
params->busNum = pci_bus;
params->deviceNum = pci_dev;
params->functionNum = pci_func;
params->pio_delay = pio_latency;
params->config_delay = config_latency;
params->disks = disks;
return new IdeController(params);
return new IdeController(this);
}
REGISTER_SIM_OBJECT("IdeController", IdeController)
#endif //DOXYGEN_SHOULD_SKIP_THIS

9
src/dev/ide_ctrl.hh
View file

@ -40,6 +40,7 @@
#include "dev/pcidev.hh"
#include "dev/pcireg.h"
#include "dev/io_device.hh"
#include "params/IdeController.hh"
#define BMIC0 0x0 // Bus master IDE command register
#define BMIS0 0x2 // Bus master IDE status register
@ -193,14 +194,8 @@ class IdeController : public PciDev
bool isDiskSelected(IdeDisk *diskPtr);
public:
struct Params : public PciDev::Params
{
/** Array of disk objects */
std::vector<IdeDisk *> disks;
};
typedef IdeControllerParams Params;
const Params *params() const { return (const Params *)_params; }
public:
IdeController(Params *p);
~IdeController();

40
src/dev/ide_disk.cc
View file

@ -38,18 +38,16 @@
#include <deque>
#include <string>
#include "arch/isa_traits.hh"
#include "base/chunk_generator.hh"
#include "base/cprintf.hh" // csprintf
#include "base/trace.hh"
#include "dev/disk_image.hh"
#include "dev/ide_disk.hh"
#include "dev/ide_ctrl.hh"
#include "dev/alpha/tsunami.hh"
#include "dev/alpha/tsunami_pchip.hh"
#include "sim/builder.hh"
#include "sim/sim_object.hh"
#include "dev/ide_disk.hh"
#include "params/IdeDisk.hh"
#include "sim/core.hh"
#include "arch/isa_traits.hh"
#include "sim/sim_object.hh"
using namespace std;
using namespace TheISA;
@ -1116,32 +1114,8 @@ IdeDisk::unserialize(Checkpoint *cp, const string &section)
UNSERIALIZE_ARRAY(dataBuffer, MAX_DMA_SIZE);
}
#ifndef DOXYGEN_SHOULD_SKIP_THIS
enum DriveID { master, slave };
static const char *DriveID_strings[] = { "master", "slave" };
BEGIN_DECLARE_SIM_OBJECT_PARAMS(IdeDisk)
SimObjectParam<DiskImage *> image;
SimpleEnumParam<DriveID> driveID;
Param<int> delay;
END_DECLARE_SIM_OBJECT_PARAMS(IdeDisk)
BEGIN_INIT_SIM_OBJECT_PARAMS(IdeDisk)
INIT_PARAM(image, "Disk image"),
INIT_ENUM_PARAM(driveID, "Drive ID (0=master 1=slave)", DriveID_strings),
INIT_PARAM_DFLT(delay, "Fixed disk delay in microseconds", 1)
END_INIT_SIM_OBJECT_PARAMS(IdeDisk)
CREATE_SIM_OBJECT(IdeDisk)
IdeDisk *
IdeDiskParams::create()
{
return new IdeDisk(getInstanceName(), image, driveID, delay);
return new IdeDisk(name, image, driveID, delay);
}
REGISTER_SIM_OBJECT("IdeDisk", IdeDisk)
#endif //DOXYGEN_SHOULD_SKIP_THIS

20
src/dev/io_device.cc
View file

@ -32,7 +32,6 @@
#include "base/chunk_generator.hh"
#include "base/trace.hh"
#include "dev/io_device.hh"
#include "sim/builder.hh"
#include "sim/system.hh"
@ -55,6 +54,10 @@ PioPort::getDeviceAddressRanges(AddrRangeList &resp, bool &snoop)
}
PioDevice::PioDevice(const Params *p)
: MemObject(p), platform(p->platform), sys(p->system), pioPort(NULL)
{}
PioDevice::~PioDevice()
{
if (pioPort)
@ -82,6 +85,11 @@ PioDevice::drain(Event *de)
return count;
}
BasicPioDevice::BasicPioDevice(const Params *p)
: PioDevice(p), pioAddr(p->pio_addr), pioSize(0),
pioDelay(p->pio_latency)
{}
void
BasicPioDevice::addressRanges(AddrRangeList &range_list)
{
@ -147,7 +155,7 @@ DmaPort::recvTiming(PacketPtr pkt)
return true;
}
DmaDevice::DmaDevice(Params *p)
DmaDevice::DmaDevice(const Params *p)
: PioDevice(p), dmaPort(NULL), minBackoffDelay(p->min_backoff_delay),
maxBackoffDelay(p->max_backoff_delay)
{ }
@ -260,8 +268,8 @@ DmaPort::sendDma()
assert(transmitList.size());
PacketPtr pkt = transmitList.front();
System::MemoryMode state = sys->getMemoryMode();
if (state == System::Timing) {
Enums::MemoryMode state = sys->getMemoryMode();
if (state == Enums::timing) {
if (backoffEvent.scheduled() || inRetry) {
DPRINTF(DMA, "Can't send immediately, waiting for retry or backoff timer\n");
return;
@ -288,7 +296,7 @@ DmaPort::sendDma()
backoffTime+curTick);
backoffEvent.schedule(backoffTime+curTick);
}
} else if (state == System::Atomic) {
} else if (state == Enums::atomic) {
transmitList.pop_front();
Tick lat;
@ -328,5 +336,3 @@ DmaDevice::~DmaDevice()
if (dmaPort)
delete dmaPort;
}

67
src/dev/io_device.hh
View file

@ -35,6 +35,9 @@
#include "mem/mem_object.hh"
#include "mem/packet.hh"
#include "mem/tport.hh"
#include "params/BasicPioDevice.hh"
#include "params/DmaDevice.hh"
#include "params/PioDevice.hh"
#include "sim/sim_object.hh"
class Event;
@ -186,29 +189,16 @@ class PioDevice : public MemObject
virtual Tick write(PacketPtr pkt) = 0;
public:
/** Params struct which is extended through each device based on
* the parameters it needs. Since we are re-writing everything, we
* might as well start from the bottom this time. */
struct Params
{
std::string name;
Platform *platform;
System *system;
};
protected:
Params *_params;
public:
const Params *params() const { return _params; }
PioDevice(Params *p)
: MemObject(p->name), platform(p->platform), sys(p->system),
pioPort(NULL), _params(p)
{}
typedef PioDeviceParams Params;
PioDevice(const Params *p);
virtual ~PioDevice();
const Params *
params() const
{
return dynamic_cast<const Params *>(_params);
}
virtual void init();
virtual unsigned int drain(Event *de);
@ -229,13 +219,6 @@ class PioDevice : public MemObject
class BasicPioDevice : public PioDevice
{
public:
struct Params : public PioDevice::Params
{
Addr pio_addr;
Tick pio_delay;
};
protected:
/** Address that the device listens to. */
Addr pioAddr;
@ -247,10 +230,14 @@ class BasicPioDevice : public PioDevice
Tick pioDelay;
public:
BasicPioDevice(Params *p)
: PioDevice(p), pioAddr(p->pio_addr), pioSize(0),
pioDelay(p->pio_delay)
{}
typedef BasicPioDeviceParams Params;
BasicPioDevice(const Params *p);
const Params *
params() const
{
return dynamic_cast<const Params *>(_params);
}
/** return the address ranges that this device responds to.
* @param range_list range list to populate with ranges
@ -261,22 +248,22 @@ class BasicPioDevice : public PioDevice
class DmaDevice : public PioDevice
{
public:
struct Params : public PioDevice::Params
{
Tick min_backoff_delay;
Tick max_backoff_delay;
};
protected:
DmaPort *dmaPort;
Tick minBackoffDelay;
Tick maxBackoffDelay;
public:
DmaDevice(Params *p);
typedef DmaDeviceParams Params;
DmaDevice(const Params *p);
virtual ~DmaDevice();
const Params *
params() const
{
return dynamic_cast<const Params *>(_params);
}
void dmaWrite(Addr addr, int size, Event *event, uint8_t *data)
{
dmaPort->dmaAction(MemCmd::WriteInvalidateReq,

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