cpu_models: get rid of cpu_models.py and move the stuff into SCons
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parent
ac106767c8
commit
f0b4259e98
9 changed files with 90 additions and 118 deletions
38
SConstruct
38
SConstruct
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@ -612,10 +612,34 @@ main = conf.Finish()
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all_isa_list = [ ]
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Export('all_isa_list')
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# Define the universe of supported CPU models
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all_cpu_list = [ ]
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default_cpus = [ ]
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Export('all_cpu_list', 'default_cpus')
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class CpuModel(object):
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'''The CpuModel class encapsulates everything the ISA parser needs to
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know about a particular CPU model.'''
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# Dict of available CPU model objects. Accessible as CpuModel.dict.
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dict = {}
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list = []
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defaults = []
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# Constructor. Automatically adds models to CpuModel.dict.
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def __init__(self, name, filename, includes, strings, default=False):
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self.name = name # name of model
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self.filename = filename # filename for output exec code
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self.includes = includes # include files needed in exec file
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# The 'strings' dict holds all the per-CPU symbols we can
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# substitute into templates etc.
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self.strings = strings
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# This cpu is enabled by default
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self.default = default
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# Add self to dict
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if name in CpuModel.dict:
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raise AttributeError, "CpuModel '%s' already registered" % name
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CpuModel.dict[name] = self
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CpuModel.list.append(name)
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Export('CpuModel')
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# Sticky variables get saved in the variables file so they persist from
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# one invocation to the next (unless overridden, in which case the new
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@ -640,13 +664,13 @@ for bdir in [ base_dir ] + extras_dir_list:
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SConscript(joinpath(root, 'SConsopts'))
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all_isa_list.sort()
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all_cpu_list.sort()
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default_cpus.sort()
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sticky_vars.AddVariables(
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EnumVariable('TARGET_ISA', 'Target ISA', 'alpha', all_isa_list),
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BoolVariable('FULL_SYSTEM', 'Full-system support', False),
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ListVariable('CPU_MODELS', 'CPU models', default_cpus, all_cpu_list),
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ListVariable('CPU_MODELS', 'CPU models',
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sorted(n for n,m in CpuModel.dict.iteritems() if m.default),
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sorted(CpuModel.list)),
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BoolVariable('NO_FAST_ALLOC', 'Disable fast object allocator', False),
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BoolVariable('FAST_ALLOC_DEBUG', 'Enable fast object allocator debugging',
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False),
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@ -90,16 +90,6 @@ env.Append(SCANNERS = isa_scanner)
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# output from the ISA description (*.isa) files.
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#
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#
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# Grab the CPU Model information
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#
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# Convert to File node to fix path
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cpu_models_file = File('../cpu/cpu_models.py')
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# This sucks in the defintions of the CpuModel objects.
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execfile(cpu_models_file.srcnode().abspath)
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# The emitter patches up the sources & targets to include the
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# autogenerated files as targets and isa parser itself as a source.
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def isa_desc_emitter(target, source, env):
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@ -40,12 +40,6 @@ Import('*')
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#
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#################################################################
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# CPU model-specific data is contained in cpu_models.py
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# Convert to SCons File node to get path handling
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models_db = File('cpu_models.py')
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# slurp in contents of file
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execfile(models_db.srcnode().abspath)
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# Template for execute() signature.
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exec_sig_template = '''
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virtual Fault execute(%(type)s *xc, Trace::InstRecord *traceData) const = 0;
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@ -97,7 +91,7 @@ def gen_sigs_string(target, source, env):
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+ ', '.join(temp_cpu_list)
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# Add command to generate header to environment.
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env.Command('static_inst_exec_sigs.hh', models_db,
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env.Command('static_inst_exec_sigs.hh', (),
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Action(gen_cpu_exec_signatures, gen_sigs_string,
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varlist = temp_cpu_list))
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35
src/cpu/checker/SConsopts
Normal file
35
src/cpu/checker/SConsopts
Normal file
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@ -0,0 +1,35 @@
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# -*- mode:python -*-
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# Copyright (c) 2003-2006 The Regents of The University of Michigan
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# All rights reserved.
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#
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# Redistribution and use in source and binary forms, with or without
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# modification, are permitted provided that the following conditions are
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# met: redistributions of source code must retain the above copyright
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# notice, this list of conditions and the following disclaimer;
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# redistributions in binary form must reproduce the above copyright
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# notice, this list of conditions and the following disclaimer in the
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# documentation and/or other materials provided with the distribution;
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# neither the name of the copyright holders nor the names of its
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# contributors may be used to endorse or promote products derived from
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# this software without specific prior written permission.
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#
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# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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#
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# Authors: Steve Reinhardt
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Import('*')
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CpuModel('CheckerCPU', 'checker_cpu_exec.cc',
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'#include "cpu/checker/cpu.hh"',
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{ 'CPU_exec_context': 'CheckerCPU' })
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@ -1,87 +0,0 @@
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# Copyright (c) 2003-2006 The Regents of The University of Michigan
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# All rights reserved.
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#
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# Redistribution and use in source and binary forms, with or without
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# modification, are permitted provided that the following conditions are
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# met: redistributions of source code must retain the above copyright
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# notice, this list of conditions and the following disclaimer;
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# redistributions in binary form must reproduce the above copyright
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# notice, this list of conditions and the following disclaimer in the
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# documentation and/or other materials provided with the distribution;
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# neither the name of the copyright holders nor the names of its
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# contributors may be used to endorse or promote products derived from
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# this software without specific prior written permission.
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#
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# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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#
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# Authors: Steve Reinhardt
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import os
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import os.path
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import sys
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################
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# CpuModel class
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#
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# The CpuModel class encapsulates everything the ISA parser needs to
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# know about a particular CPU model.
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class CpuModel:
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# Dict of available CPU model objects. Accessible as CpuModel.dict.
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dict = {}
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# Constructor. Automatically adds models to CpuModel.dict.
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def __init__(self, name, filename, includes, strings):
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self.name = name
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self.filename = filename # filename for output exec code
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self.includes = includes # include files needed in exec file
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# The 'strings' dict holds all the per-CPU symbols we can
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# substitute into templates etc.
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self.strings = strings
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# Add self to dict
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CpuModel.dict[name] = self
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#
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# Define CPU models.
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#
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# Parameters are:
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# - name of model
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# - filename for generated ISA execution file
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# - includes needed for generated ISA execution file
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# - substitution strings for ISA description templates
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#
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CpuModel('AtomicSimpleCPU', 'atomic_simple_cpu_exec.cc',
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'#include "cpu/simple/atomic.hh"',
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{ 'CPU_exec_context': 'AtomicSimpleCPU' })
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CpuModel('TimingSimpleCPU', 'timing_simple_cpu_exec.cc',
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'#include "cpu/simple/timing.hh"',
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{ 'CPU_exec_context': 'TimingSimpleCPU' })
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CpuModel('FullCPU', 'full_cpu_exec.cc',
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'#include "encumbered/cpu/full/dyn_inst.hh"',
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{ 'CPU_exec_context': 'DynInst' })
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CpuModel('OzoneSimpleCPU', 'ozone_simple_exec.cc',
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'#include "cpu/ozone/dyn_inst.hh"',
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{ 'CPU_exec_context': 'OzoneDynInst<SimpleImpl>' })
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CpuModel('OzoneCPU', 'ozone_exec.cc',
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'#include "cpu/ozone/dyn_inst.hh"',
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{ 'CPU_exec_context': 'OzoneDynInst<OzoneImpl>' })
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CpuModel('CheckerCPU', 'checker_cpu_exec.cc',
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'#include "cpu/checker/cpu.hh"',
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{ 'CPU_exec_context': 'CheckerCPU' })
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CpuModel('O3CPU', 'o3_cpu_exec.cc',
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'#include "cpu/o3/isa_specific.hh"',
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{ 'CPU_exec_context': 'O3DynInst' })
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CpuModel('InOrderCPU', 'inorder_cpu_exec.cc',
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'#include "cpu/inorder/inorder_dyn_inst.hh"',
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{ 'CPU_exec_context': 'InOrderDynInst' })
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@ -30,5 +30,7 @@
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Import('*')
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all_cpu_list.append('InOrderCPU')
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default_cpus.append('InOrderCPU')
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CpuModel('InOrderCPU', 'inorder_cpu_exec.cc',
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'#include "cpu/inorder/inorder_dyn_inst.hh"',
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{ 'CPU_exec_context': 'InOrderDynInst' },
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default=True)
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@ -30,5 +30,7 @@
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Import('*')
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all_cpu_list.append('O3CPU')
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default_cpus.append('O3CPU')
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CpuModel('O3CPU', 'o3_cpu_exec.cc',
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'#include "cpu/o3/isa_specific.hh"',
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{ 'CPU_exec_context': 'O3DynInst' },
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default=True)
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@ -30,4 +30,10 @@
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Import('*')
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all_cpu_list.append('OzoneCPU')
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CpuModel('OzoneSimpleCPU', 'ozone_simple_exec.cc',
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'#include "cpu/ozone/dyn_inst.hh"',
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{ 'CPU_exec_context': 'OzoneDynInst<SimpleImpl>' })
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CpuModel('OzoneCPU', 'ozone_exec.cc',
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'#include "cpu/ozone/dyn_inst.hh"',
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{ 'CPU_exec_context': 'OzoneDynInst<OzoneImpl>' })
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@ -30,5 +30,11 @@
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Import('*')
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all_cpu_list.extend(('AtomicSimpleCPU', 'TimingSimpleCPU'))
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default_cpus.extend(('AtomicSimpleCPU', 'TimingSimpleCPU'))
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CpuModel('AtomicSimpleCPU', 'atomic_simple_cpu_exec.cc',
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'#include "cpu/simple/atomic.hh"',
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{ 'CPU_exec_context': 'AtomicSimpleCPU' },
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default=True)
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CpuModel('TimingSimpleCPU', 'timing_simple_cpu_exec.cc',
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'#include "cpu/simple/timing.hh"',
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{ 'CPU_exec_context': 'TimingSimpleCPU' },
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default=True)
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