Add LRU aligned copies to the hierarchy, with only one outstanding copy. Aligned copies now fully work in LRU (just need to write the IIC doCopy call). At the moment they are slow since a stalled copy stalls the entire cache.
cpu/memtest/memtest.cc: cpu/memtest/memtest.hh: Add aligned copy tests, percent of copies is specified by percent_copies --HG-- extra : convert_revision : eaf1900fcb8832db98249e94e3472ebfb049eb48
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2 changed files with 35 additions and 3 deletions
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@ -50,6 +50,7 @@ MemTest::MemTest(const string &name,
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FunctionalMemory *check_mem,
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FunctionalMemory *check_mem,
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unsigned _memorySize,
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unsigned _memorySize,
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unsigned _percentReads,
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unsigned _percentReads,
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unsigned _percentCopies,
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unsigned _percentUncacheable,
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unsigned _percentUncacheable,
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unsigned _progressInterval,
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unsigned _progressInterval,
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Addr _traceAddr,
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Addr _traceAddr,
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@ -62,6 +63,7 @@ MemTest::MemTest(const string &name,
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checkMem(check_mem),
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checkMem(check_mem),
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size(_memorySize),
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size(_memorySize),
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percentReads(_percentReads),
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percentReads(_percentReads),
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percentCopies(_percentCopies),
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percentUncacheable(_percentUncacheable),
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percentUncacheable(_percentUncacheable),
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progressInterval(_progressInterval),
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progressInterval(_progressInterval),
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nextProgressMessage(_progressInterval)
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nextProgressMessage(_progressInterval)
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@ -149,6 +151,8 @@ MemTest::completeRequest(MemReqPtr &req, uint8_t *data)
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numWrites++;
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numWrites++;
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break;
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break;
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case Copy:
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break;
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default:
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default:
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panic("invalid command");
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panic("invalid command");
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@ -156,7 +160,8 @@ MemTest::completeRequest(MemReqPtr &req, uint8_t *data)
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if (blockAddr(req->paddr) == traceBlockAddr) {
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if (blockAddr(req->paddr) == traceBlockAddr) {
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cerr << name() << ": completed "
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cerr << name() << ": completed "
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<< (req->cmd.isWrite() ? "write" : "read") << " access of "
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<< (req->cmd.isWrite() ? "write" : "read")
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<< " access of "
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<< req->size << " bytes at address 0x"
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<< req->size << " bytes at address 0x"
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<< hex << req->paddr << ", value = 0x";
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<< hex << req->paddr << ", value = 0x";
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printData(cerr, req->data, req->size);
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printData(cerr, req->data, req->size);
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@ -209,6 +214,7 @@ MemTest::tick()
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//make new request
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//make new request
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unsigned cmd = rand() % 100;
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unsigned cmd = rand() % 100;
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unsigned offset1 = random() % size;
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unsigned offset1 = random() % size;
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unsigned offset2 = random() % size;
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unsigned base = random() % 2;
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unsigned base = random() % 2;
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uint64_t data = random();
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uint64_t data = random();
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unsigned access_size = random() % 4;
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unsigned access_size = random() % 4;
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@ -250,7 +256,7 @@ MemTest::tick()
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req->completionEvent = new MemCompleteEvent(req, result, this);
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req->completionEvent = new MemCompleteEvent(req, result, this);
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cacheInterface->access(req);
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cacheInterface->access(req);
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}
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}
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} else {
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} else if (cmd < (100 - percentCopies)){
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// write
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// write
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req->cmd = Write;
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req->cmd = Write;
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memcpy(req->data, &data, req->size);
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memcpy(req->data, &data, req->size);
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@ -271,6 +277,28 @@ MemTest::tick()
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req->completionEvent = new MemCompleteEvent(req, NULL, this);
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req->completionEvent = new MemCompleteEvent(req, NULL, this);
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cacheInterface->access(req);
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cacheInterface->access(req);
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}
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}
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} else {
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// copy
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Addr source = blockAddr(((base) ? baseAddr1 : baseAddr2) + offset1);
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Addr dest = blockAddr(((base) ? baseAddr2 : baseAddr1) + offset2);
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req->cmd = Copy;
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req->flags &= ~UNCACHEABLE;
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req->paddr = source;
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req->dest = dest;
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delete [] req->data;
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req->data = new uint8_t[blockSize];
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req->size = blockSize;
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if (source == traceBlockAddr || dest == traceBlockAddr) {
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cerr << name() << ": initiating copy of "
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<< req->size << " bytes from addr 0x"
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<< hex << source << " to addr 0x"
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<< hex << dest << " at cycle "
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<< dec << curTick << endl;
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}
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cacheInterface->access(req);
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uint8_t result[blockSize];
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checkMem->access(Read, source, &result, blockSize);
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checkMem->access(Write, dest, &result, blockSize);
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}
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}
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}
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}
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@ -297,6 +325,7 @@ BEGIN_DECLARE_SIM_OBJECT_PARAMS(MemTest)
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SimObjectParam<FunctionalMemory *> check_mem;
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SimObjectParam<FunctionalMemory *> check_mem;
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Param<unsigned> memory_size;
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Param<unsigned> memory_size;
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Param<unsigned> percent_reads;
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Param<unsigned> percent_reads;
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Param<unsigned> percent_copies;
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Param<unsigned> percent_uncacheable;
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Param<unsigned> percent_uncacheable;
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Param<unsigned> progress_interval;
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Param<unsigned> progress_interval;
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Param<Addr> trace_addr;
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Param<Addr> trace_addr;
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@ -313,6 +342,7 @@ BEGIN_INIT_SIM_OBJECT_PARAMS(MemTest)
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INIT_PARAM(check_mem, "check memory"),
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INIT_PARAM(check_mem, "check memory"),
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INIT_PARAM_DFLT(memory_size, "memory size", 65536),
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INIT_PARAM_DFLT(memory_size, "memory size", 65536),
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INIT_PARAM_DFLT(percent_reads, "target read percentage", 65),
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INIT_PARAM_DFLT(percent_reads, "target read percentage", 65),
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INIT_PARAM_DFLT(percent_copies, "target copy percentage", 0),
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INIT_PARAM_DFLT(percent_uncacheable, "target uncacheable percentage", 10),
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INIT_PARAM_DFLT(percent_uncacheable, "target uncacheable percentage", 10),
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INIT_PARAM_DFLT(progress_interval,
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INIT_PARAM_DFLT(progress_interval,
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"progress report interval (in accesses)", 1000000),
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"progress report interval (in accesses)", 1000000),
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@ -330,7 +360,7 @@ END_INIT_SIM_OBJECT_PARAMS(MemTest)
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CREATE_SIM_OBJECT(MemTest)
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CREATE_SIM_OBJECT(MemTest)
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{
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{
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return new MemTest(getInstanceName(), cache->getInterface(), main_mem,
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return new MemTest(getInstanceName(), cache->getInterface(), main_mem,
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check_mem, memory_size, percent_reads,
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check_mem, memory_size, percent_reads, percent_copies,
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percent_uncacheable, progress_interval,
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percent_uncacheable, progress_interval,
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trace_addr, max_loads_any_thread,
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trace_addr, max_loads_any_thread,
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max_loads_all_threads);
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max_loads_all_threads);
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@ -48,6 +48,7 @@ class MemTest : public BaseCPU
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FunctionalMemory *check_mem,
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FunctionalMemory *check_mem,
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unsigned _memorySize,
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unsigned _memorySize,
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unsigned _percentReads,
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unsigned _percentReads,
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unsigned _percentCopies,
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unsigned _percentUncacheable,
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unsigned _percentUncacheable,
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unsigned _progressInterval,
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unsigned _progressInterval,
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Addr _traceAddr,
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Addr _traceAddr,
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@ -81,6 +82,7 @@ class MemTest : public BaseCPU
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unsigned size; // size of testing memory region
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unsigned size; // size of testing memory region
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unsigned percentReads; // target percentage of read accesses
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unsigned percentReads; // target percentage of read accesses
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unsigned percentCopies; // target percentage of copy accesses
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unsigned percentUncacheable;
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unsigned percentUncacheable;
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unsigned blockSize;
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unsigned blockSize;
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