From f04d81163cee54849ea06e8decfbe122fdb3d68d Mon Sep 17 00:00:00 2001
From: Curtis Dunham <Curtis.Dunham@arm.com>
Date: Mon, 19 Dec 2016 11:03:28 -0600
Subject: [PATCH] arm: provide correct timer availability in ID_PFR1 register

Change-Id: Id4cd839c12b70616017a5830e3f9bbb59b0f97ba
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
---
 src/arch/arm/isa.cc | 11 +++++++----
 1 file changed, 7 insertions(+), 4 deletions(-)

diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc
index 74ea91a8d..4f099bf90 100644
--- a/src/arch/arm/isa.cc
+++ b/src/arch/arm/isa.cc
@@ -770,10 +770,13 @@ ISA::readMiscReg(int misc_reg, ThreadContext *tc)
         // !ThumbEE | !Jazelle | Thumb | ARM
         return 0x00000031;
       case MISCREG_ID_PFR1:
-        // !Timer | Virti | !M Profile | TrustZone | ARMv4
-        return 0x00000001
-             | (haveSecurity       ? 0x00000010 : 0x0)
-             | (haveVirtualization ? 0x00001000 : 0x0);
+        {   // Timer | Virti | !M Profile | TrustZone | ARMv4
+            bool haveTimer = (system->getGenericTimer() != NULL);
+            return 0x00000001
+                 | (haveSecurity       ? 0x00000010 : 0x0)
+                 | (haveVirtualization ? 0x00001000 : 0x0)
+                 | (haveTimer          ? 0x00010000 : 0x0);
+        }
       case MISCREG_ID_AA64PFR0_EL1:
         return 0x0000000000000002   // AArch{64,32} supported at EL0
              | 0x0000000000000020                             // EL1