O3: Fetch from the microcode ROM when needed.
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@ -1070,6 +1070,8 @@ DefaultFetch<Impl>::fetch(bool &status_change)
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Addr pcOffset = fetchOffset[tid];
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Addr fetchAddr = (thisPC.instAddr() + pcOffset) & BaseCPU::PCMask;
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bool inRom = isRomMicroPC(thisPC.microPC());
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// If returning from the delay of a cache miss, then update the status
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// to running, otherwise do the cache access. Possibly move this up
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// to tick() function.
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@ -1083,7 +1085,7 @@ DefaultFetch<Impl>::fetch(bool &status_change)
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Addr block_PC = icacheBlockAlignPC(fetchAddr);
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// Unless buffer already got the block, fetch it from icache.
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if (!cacheDataValid[tid] || block_PC != cacheDataPC[tid]) {
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if (!(cacheDataValid[tid] && block_PC == cacheDataPC[tid]) && !inRom) {
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DPRINTF(Fetch, "[tid:%i]: Attempting to translate and read "
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"instruction, starting at PC %s.\n", tid, thisPC);
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@ -1155,7 +1157,7 @@ DefaultFetch<Impl>::fetch(bool &status_change)
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!predictedBranch) {
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// If we need to process more memory, do it now.
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if (!curMacroop && !predecoder.extMachInstReady()) {
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if (!(curMacroop || inRom) && !predecoder.extMachInstReady()) {
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if (ISA_HAS_DELAY_SLOT && pcOffset == 0) {
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// Walk past any annulled delay slot instructions.
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Addr pcAddr = thisPC.instAddr() & BaseCPU::PCMask;
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@ -1181,7 +1183,7 @@ DefaultFetch<Impl>::fetch(bool &status_change)
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// Extract as many instructions and/or microops as we can from
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// the memory we've processed so far.
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do {
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if (!curMacroop) {
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if (!(curMacroop || inRom)) {
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if (predecoder.extMachInstReady()) {
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ExtMachInst extMachInst;
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@ -1202,8 +1204,13 @@ DefaultFetch<Impl>::fetch(bool &status_change)
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break;
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}
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}
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if (curMacroop) {
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staticInst = curMacroop->fetchMicroop(thisPC.microPC());
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if (curMacroop || inRom) {
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if (inRom) {
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staticInst = cpu->microcodeRom.fetchMicroop(
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thisPC.microPC(), curMacroop);
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} else {
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staticInst = curMacroop->fetchMicroop(thisPC.microPC());
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}
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if (staticInst->isLastMicroop()) {
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curMacroop = NULL;
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pcOffset = 0;
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