From efea870fce8c00dbb8d5b9b33fe6fd0cf2e3b960 Mon Sep 17 00:00:00 2001 From: Andreas Hansson Date: Fri, 21 Sep 2012 11:48:11 -0400 Subject: [PATCH] TrafficGen: Add a basic traffic generator regression This patch adds a basic regression for the traffic generator. The regression also serves as an example of the file formats used. More complex regressions that make use of a DRAM controller model will follow shortly. --- tests/SConscript | 2 +- tests/configs/tgen-simple-mem.py | 67 ++++ .../ref/arm/linux/tgen-simple-mem/simerr | 0 .../ref/arm/linux/tgen-simple-mem/simout | 10 + .../ref/arm/linux/tgen-simple-mem/stats.txt | 365 ++++++++++++++++++ tests/quick/se/70.tgen/test-frfcfs-toy.trc | 7 + tests/quick/se/70.tgen/test-open-ops.trc | 6 + tests/quick/se/70.tgen/test-refresh.trc | 3 + tests/quick/se/70.tgen/test-writebuffer.trc | 5 + tests/quick/se/70.tgen/test-writefrfcfs.trc | 26 ++ tests/quick/se/70.tgen/test.py | 38 ++ tests/quick/se/70.tgen/tgen-simple-mem.cfg | 27 ++ tests/quick/se/70.tgen/tgen-simple-mem.trc | 2 + 13 files changed, 557 insertions(+), 1 deletion(-) create mode 100644 tests/configs/tgen-simple-mem.py create mode 100755 tests/quick/se/70.tgen/ref/arm/linux/tgen-simple-mem/simerr create mode 100755 tests/quick/se/70.tgen/ref/arm/linux/tgen-simple-mem/simout create mode 100644 tests/quick/se/70.tgen/ref/arm/linux/tgen-simple-mem/stats.txt create mode 100644 tests/quick/se/70.tgen/test-frfcfs-toy.trc create mode 100644 tests/quick/se/70.tgen/test-open-ops.trc create mode 100644 tests/quick/se/70.tgen/test-refresh.trc create mode 100644 tests/quick/se/70.tgen/test-writebuffer.trc create mode 100644 tests/quick/se/70.tgen/test-writefrfcfs.trc create mode 100644 tests/quick/se/70.tgen/test.py create mode 100644 tests/quick/se/70.tgen/tgen-simple-mem.cfg create mode 100644 tests/quick/se/70.tgen/tgen-simple-mem.trc diff --git a/tests/SConscript b/tests/SConscript index d9c40ebe3..7ade8ffb6 100644 --- a/tests/SConscript +++ b/tests/SConscript @@ -315,7 +315,7 @@ if env['TARGET_ISA'] == 'x86': configs += ['simple-atomic', 'simple-timing', 'o3-timing', 'memtest', 'simple-atomic-mp', 'simple-timing-mp', 'o3-timing-mp', - 'inorder-timing', 'rubytest'] + 'inorder-timing', 'rubytest', 'tgen-simple-mem'] if env['PROTOCOL'] != 'None': if env['PROTOCOL'] == 'MI_example': diff --git a/tests/configs/tgen-simple-mem.py b/tests/configs/tgen-simple-mem.py new file mode 100644 index 000000000..1a95acb54 --- /dev/null +++ b/tests/configs/tgen-simple-mem.py @@ -0,0 +1,67 @@ +# Copyright (c) 2012 ARM Limited +# All rights reserved. +# +# The license below extends only to copyright in the software and shall +# not be construed as granting a license to any other intellectual +# property including but not limited to intellectual property relating +# to a hardware implementation of the functionality of the software +# licensed hereunder. You may use the software subject to the license +# terms below provided that you ensure that this notice is replicated +# unmodified and in its entirety in all distributions of the software, +# modified or unmodified, in source code or in binary form. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer; +# redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution; +# neither the name of the copyright holders nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Andreas Hansson + +import m5 +from m5.objects import * + +# even if this is only a traffic generator, call it cpu to make sure +# the scripts are happy +cpu = TrafficGen(config_file = "tests/quick/se/70.tgen/tgen-simple-mem.cfg") + +# system simulated +system = System(cpu = cpu, physmem = SimpleMemory(), + membus = NoncoherentBus(clock="1GHz", width = 16)) + +# add a communication monitor +system.monitor = CommMonitor() + +# connect the traffic generator to the bus via a communication monitor +system.cpu.port = system.monitor.slave +system.monitor.master = system.membus.slave + +# connect the system port even if it is not used in this example +system.system_port = system.membus.slave + +# connect memory to the membus +system.physmem.port = system.membus.master + +# ----------------------- +# run simulation +# ----------------------- + +root = Root(full_system = False, system = system) +root.system.mem_mode = 'timing' diff --git a/tests/quick/se/70.tgen/ref/arm/linux/tgen-simple-mem/simerr b/tests/quick/se/70.tgen/ref/arm/linux/tgen-simple-mem/simerr new file mode 100755 index 000000000..e69de29bb diff --git a/tests/quick/se/70.tgen/ref/arm/linux/tgen-simple-mem/simout b/tests/quick/se/70.tgen/ref/arm/linux/tgen-simple-mem/simout new file mode 100755 index 000000000..727a89c99 --- /dev/null +++ b/tests/quick/se/70.tgen/ref/arm/linux/tgen-simple-mem/simout @@ -0,0 +1,10 @@ +gem5 Simulator System. http://gem5.org +gem5 is copyrighted software; use the --copyright option for details. + +gem5 compiled Aug 25 2012 13:56:00 +gem5 started Aug 25 2012 13:58:17 +gem5 executing on Andreas-MacBook-Pro.local +command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/70.tgen/arm/linux/tgen-simple-mem -re tests/run.py build/ARM/tests/opt/quick/se/70.tgen/arm/linux/tgen-simple-mem +Global frequency set at 1000000000000 ticks per second +info: Entering event queue @ 0. Starting simulation... +Exiting @ tick 100000000000 because simulate() limit reached diff --git a/tests/quick/se/70.tgen/ref/arm/linux/tgen-simple-mem/stats.txt b/tests/quick/se/70.tgen/ref/arm/linux/tgen-simple-mem/stats.txt new file mode 100644 index 000000000..fd1ec361f --- /dev/null +++ b/tests/quick/se/70.tgen/ref/arm/linux/tgen-simple-mem/stats.txt @@ -0,0 +1,365 @@ + +---------- Begin Simulation Statistics ---------- +sim_seconds 0.100000 # Number of seconds simulated +sim_ticks 100000000000 # Number of ticks simulated +final_tick 100000000000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_freq 1000000000000 # Frequency of simulated ticks +host_tick_rate 31243111314 # Simulator tick rate (ticks/s) +host_mem_usage 230668 # Number of bytes of host memory used +host_seconds 3.20 # Real time elapsed on the host +system.physmem.bytes_read::cpu 64 # Number of bytes read from this memory +system.physmem.bytes_read::total 64 # Number of bytes read from this memory +system.physmem.bytes_written::cpu 213335552 # Number of bytes written to this memory +system.physmem.bytes_written::total 213335552 # Number of bytes written to this memory +system.physmem.num_reads::cpu 1 # Number of read requests responded to by this memory +system.physmem.num_reads::total 1 # Number of read requests responded to by this memory +system.physmem.num_writes::cpu 3333368 # Number of write requests responded to by this memory +system.physmem.num_writes::total 3333368 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu 640 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 640 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu 2133355520 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2133355520 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu 2133356160 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2133356160 # Total bandwidth to/from this memory (bytes/s) +system.monitor.readBurstLengthHist::samples 1 # Histogram of burst lengths of transmitted packets +system.monitor.readBurstLengthHist::mean 64 # Histogram of burst lengths of transmitted packets +system.monitor.readBurstLengthHist::gmean 64.000000 # Histogram of burst lengths of transmitted packets +system.monitor.readBurstLengthHist::stdev nan # Histogram of burst lengths of transmitted packets +system.monitor.readBurstLengthHist::0-3 0 0.00% 0.00% # Histogram of burst lengths of transmitted packets +system.monitor.readBurstLengthHist::4-7 0 0.00% 0.00% # Histogram of burst lengths of transmitted packets +system.monitor.readBurstLengthHist::8-11 0 0.00% 0.00% # Histogram of burst lengths of transmitted packets +system.monitor.readBurstLengthHist::12-15 0 0.00% 0.00% # Histogram of burst lengths of transmitted packets +system.monitor.readBurstLengthHist::16-19 0 0.00% 0.00% # Histogram of burst lengths of transmitted packets +system.monitor.readBurstLengthHist::20-23 0 0.00% 0.00% # Histogram of burst lengths of transmitted packets +system.monitor.readBurstLengthHist::24-27 0 0.00% 0.00% # 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Write request-response latency +system.monitor.writeLatencyHist::total 3333367 # Write request-response latency +system.monitor.ittReadRead::samples 0 # Read-to-read inter transaction time +system.monitor.ittReadRead::mean nan # Read-to-read inter transaction time +system.monitor.ittReadRead::stdev nan # Read-to-read inter transaction time +system.monitor.ittReadRead::underflows 0 # Read-to-read inter transaction time +system.monitor.ittReadRead::1-5000 0 # Read-to-read inter transaction time +system.monitor.ittReadRead::5001-10000 0 # Read-to-read inter transaction time +system.monitor.ittReadRead::10001-15000 0 # Read-to-read inter transaction time +system.monitor.ittReadRead::15001-20000 0 # Read-to-read inter transaction time +system.monitor.ittReadRead::20001-25000 0 # Read-to-read inter transaction time +system.monitor.ittReadRead::25001-30000 0 # Read-to-read inter transaction time +system.monitor.ittReadRead::30001-35000 0 # Read-to-read inter transaction time +system.monitor.ittReadRead::35001-40000 0 # Read-to-read inter transaction time +system.monitor.ittReadRead::40001-45000 0 # Read-to-read inter transaction time +system.monitor.ittReadRead::45001-50000 0 # Read-to-read inter transaction time +system.monitor.ittReadRead::50001-55000 0 # Read-to-read inter transaction time +system.monitor.ittReadRead::55001-60000 0 # Read-to-read inter transaction time +system.monitor.ittReadRead::60001-65000 0 # Read-to-read inter transaction time +system.monitor.ittReadRead::65001-70000 0 # Read-to-read inter transaction time +system.monitor.ittReadRead::70001-75000 0 # Read-to-read inter transaction time +system.monitor.ittReadRead::75001-80000 0 # Read-to-read inter transaction time +system.monitor.ittReadRead::80001-85000 0 # Read-to-read inter transaction time +system.monitor.ittReadRead::85001-90000 0 # Read-to-read inter transaction time +system.monitor.ittReadRead::90001-95000 0 # Read-to-read inter transaction time +system.monitor.ittReadRead::95001-100000 0 # Read-to-read inter transaction time +system.monitor.ittReadRead::overflows 0 # Read-to-read inter transaction time +system.monitor.ittReadRead::min_value 0 # Read-to-read inter transaction time +system.monitor.ittReadRead::max_value 0 # Read-to-read inter transaction time +system.monitor.ittReadRead::total 0 # Read-to-read inter transaction time +system.monitor.ittWriteWrite::samples 3333367 # Write-to-write inter transaction time +system.monitor.ittWriteWrite::mean 29999.695203 # Write-to-write inter transaction time +system.monitor.ittWriteWrite::stdev 539.134360 # Write-to-write inter transaction time +system.monitor.ittWriteWrite::underflows 0 0.00% 0.00% # Write-to-write inter transaction time +system.monitor.ittWriteWrite::1-5000 0 0.00% 0.00% # Write-to-write inter transaction time +system.monitor.ittWriteWrite::5001-10000 99 0.00% 0.00% # Write-to-write inter transaction time +system.monitor.ittWriteWrite::10001-15000 0 0.00% 0.00% # Write-to-write inter transaction time +system.monitor.ittWriteWrite::15001-20000 0 0.00% 0.00% # Write-to-write inter transaction time +system.monitor.ittWriteWrite::20001-25000 0 0.00% 0.00% # Write-to-write inter transaction time +system.monitor.ittWriteWrite::25001-30000 3333267 100.00% 100.00% # Write-to-write inter transaction time +system.monitor.ittWriteWrite::30001-35000 0 0.00% 100.00% # Write-to-write inter transaction time +system.monitor.ittWriteWrite::35001-40000 0 0.00% 100.00% # Write-to-write inter transaction time +system.monitor.ittWriteWrite::40001-45000 0 0.00% 100.00% # Write-to-write inter transaction time +system.monitor.ittWriteWrite::45001-50000 0 0.00% 100.00% # Write-to-write inter transaction time +system.monitor.ittWriteWrite::50001-55000 0 0.00% 100.00% # Write-to-write inter transaction time +system.monitor.ittWriteWrite::55001-60000 0 0.00% 100.00% # Write-to-write inter transaction time +system.monitor.ittWriteWrite::60001-65000 0 0.00% 100.00% # Write-to-write inter transaction time +system.monitor.ittWriteWrite::65001-70000 0 0.00% 100.00% # Write-to-write inter transaction time +system.monitor.ittWriteWrite::70001-75000 0 0.00% 100.00% # Write-to-write inter transaction time +system.monitor.ittWriteWrite::75001-80000 0 0.00% 100.00% # Write-to-write inter transaction time +system.monitor.ittWriteWrite::80001-85000 0 0.00% 100.00% # Write-to-write inter transaction time +system.monitor.ittWriteWrite::85001-90000 0 0.00% 100.00% # Write-to-write inter transaction time +system.monitor.ittWriteWrite::90001-95000 0 0.00% 100.00% # Write-to-write inter transaction time +system.monitor.ittWriteWrite::95001-100000 0 0.00% 100.00% # Write-to-write inter transaction time +system.monitor.ittWriteWrite::overflows 1 0.00% 100.00% # Write-to-write inter transaction time +system.monitor.ittWriteWrite::min_value 10000 # Write-to-write inter transaction time +system.monitor.ittWriteWrite::max_value 994000 # Write-to-write inter transaction time +system.monitor.ittWriteWrite::total 3333367 # Write-to-write inter transaction time +system.monitor.ittReqReq::samples 3333368 # Request-to-request inter transaction time +system.monitor.ittReqReq::mean 29999.687703 # Request-to-request inter transaction time +system.monitor.ittReqReq::stdev 539.308135 # Request-to-request inter transaction time +system.monitor.ittReqReq::underflows 0 0.00% 0.00% # Request-to-request inter transaction time +system.monitor.ittReqReq::1-5000 1 0.00% 0.00% # Request-to-request inter transaction time +system.monitor.ittReqReq::5001-10000 99 0.00% 0.00% # Request-to-request inter transaction time +system.monitor.ittReqReq::10001-15000 0 0.00% 0.00% # Request-to-request inter transaction time +system.monitor.ittReqReq::15001-20000 0 0.00% 0.00% # Request-to-request inter transaction time +system.monitor.ittReqReq::20001-25000 0 0.00% 0.00% # Request-to-request inter transaction time +system.monitor.ittReqReq::25001-30000 3333267 100.00% 100.00% # Request-to-request inter transaction time +system.monitor.ittReqReq::30001-35000 0 0.00% 100.00% # Request-to-request inter transaction time +system.monitor.ittReqReq::35001-40000 0 0.00% 100.00% # Request-to-request inter transaction time +system.monitor.ittReqReq::40001-45000 0 0.00% 100.00% # Request-to-request inter transaction time +system.monitor.ittReqReq::45001-50000 0 0.00% 100.00% # Request-to-request inter transaction time +system.monitor.ittReqReq::50001-55000 0 0.00% 100.00% # Request-to-request inter transaction time +system.monitor.ittReqReq::55001-60000 0 0.00% 100.00% # Request-to-request inter transaction time +system.monitor.ittReqReq::60001-65000 0 0.00% 100.00% # Request-to-request inter transaction time +system.monitor.ittReqReq::65001-70000 0 0.00% 100.00% # Request-to-request inter transaction time +system.monitor.ittReqReq::70001-75000 0 0.00% 100.00% # Request-to-request inter transaction time +system.monitor.ittReqReq::75001-80000 0 0.00% 100.00% # Request-to-request inter transaction time +system.monitor.ittReqReq::80001-85000 0 0.00% 100.00% # Request-to-request inter transaction time +system.monitor.ittReqReq::85001-90000 0 0.00% 100.00% # Request-to-request inter transaction time +system.monitor.ittReqReq::90001-95000 0 0.00% 100.00% # Request-to-request inter transaction time +system.monitor.ittReqReq::95001-100000 0 0.00% 100.00% # Request-to-request inter transaction time +system.monitor.ittReqReq::overflows 1 0.00% 100.00% # Request-to-request inter transaction time +system.monitor.ittReqReq::min_value 5000 # Request-to-request inter transaction time +system.monitor.ittReqReq::max_value 994000 # Request-to-request inter transaction time +system.monitor.ittReqReq::total 3333368 # Request-to-request inter transaction time +system.monitor.outstandingReadsHist::samples 100 # Outstanding read transactions +system.monitor.outstandingReadsHist::mean 0 # Outstanding read transactions +system.monitor.outstandingReadsHist::gmean 0 # Outstanding read transactions +system.monitor.outstandingReadsHist::stdev 0 # Outstanding read transactions +system.monitor.outstandingReadsHist::0 100 100.00% 100.00% # Outstanding read transactions +system.monitor.outstandingReadsHist::1 0 0.00% 100.00% # Outstanding read transactions +system.monitor.outstandingReadsHist::2 0 0.00% 100.00% # Outstanding read transactions +system.monitor.outstandingReadsHist::3 0 0.00% 100.00% # Outstanding read transactions +system.monitor.outstandingReadsHist::4 0 0.00% 100.00% # Outstanding read transactions +system.monitor.outstandingReadsHist::5 0 0.00% 100.00% # Outstanding read transactions +system.monitor.outstandingReadsHist::6 0 0.00% 100.00% # Outstanding read transactions +system.monitor.outstandingReadsHist::7 0 0.00% 100.00% # Outstanding read transactions +system.monitor.outstandingReadsHist::8 0 0.00% 100.00% # Outstanding read transactions +system.monitor.outstandingReadsHist::9 0 0.00% 100.00% # Outstanding read transactions +system.monitor.outstandingReadsHist::10 0 0.00% 100.00% # Outstanding read transactions +system.monitor.outstandingReadsHist::11 0 0.00% 100.00% # Outstanding read transactions +system.monitor.outstandingReadsHist::12 0 0.00% 100.00% # Outstanding read transactions +system.monitor.outstandingReadsHist::13 0 0.00% 100.00% # Outstanding read transactions +system.monitor.outstandingReadsHist::14 0 0.00% 100.00% # Outstanding read transactions +system.monitor.outstandingReadsHist::15 0 0.00% 100.00% # Outstanding read transactions +system.monitor.outstandingReadsHist::16 0 0.00% 100.00% # Outstanding read transactions +system.monitor.outstandingReadsHist::17 0 0.00% 100.00% # Outstanding read transactions +system.monitor.outstandingReadsHist::18 0 0.00% 100.00% # Outstanding read transactions +system.monitor.outstandingReadsHist::19 0 0.00% 100.00% # Outstanding read transactions +system.monitor.outstandingReadsHist::total 100 # Outstanding read transactions +system.monitor.outstandingWritesHist::samples 100 # Outstanding write transactions +system.monitor.outstandingWritesHist::mean 1 # Outstanding write transactions +system.monitor.outstandingWritesHist::gmean 1 # Outstanding write transactions +system.monitor.outstandingWritesHist::stdev 0 # Outstanding write transactions +system.monitor.outstandingWritesHist::0 0 0.00% 0.00% # Outstanding write transactions +system.monitor.outstandingWritesHist::1 100 100.00% 100.00% # Outstanding write transactions +system.monitor.outstandingWritesHist::2 0 0.00% 100.00% # Outstanding write transactions +system.monitor.outstandingWritesHist::3 0 0.00% 100.00% # Outstanding write transactions +system.monitor.outstandingWritesHist::4 0 0.00% 100.00% # Outstanding write transactions +system.monitor.outstandingWritesHist::5 0 0.00% 100.00% # Outstanding write transactions +system.monitor.outstandingWritesHist::6 0 0.00% 100.00% # Outstanding write transactions +system.monitor.outstandingWritesHist::7 0 0.00% 100.00% # Outstanding write transactions +system.monitor.outstandingWritesHist::8 0 0.00% 100.00% # Outstanding write transactions +system.monitor.outstandingWritesHist::9 0 0.00% 100.00% # Outstanding write transactions +system.monitor.outstandingWritesHist::10 0 0.00% 100.00% # Outstanding write transactions +system.monitor.outstandingWritesHist::11 0 0.00% 100.00% # Outstanding write transactions +system.monitor.outstandingWritesHist::12 0 0.00% 100.00% # Outstanding write transactions +system.monitor.outstandingWritesHist::13 0 0.00% 100.00% # Outstanding write transactions +system.monitor.outstandingWritesHist::14 0 0.00% 100.00% # Outstanding write transactions +system.monitor.outstandingWritesHist::15 0 0.00% 100.00% # Outstanding write transactions +system.monitor.outstandingWritesHist::16 0 0.00% 100.00% # Outstanding write transactions +system.monitor.outstandingWritesHist::17 0 0.00% 100.00% # Outstanding write transactions +system.monitor.outstandingWritesHist::18 0 0.00% 100.00% # Outstanding write transactions +system.monitor.outstandingWritesHist::19 0 0.00% 100.00% # Outstanding write transactions +system.monitor.outstandingWritesHist::total 100 # Outstanding write transactions +system.monitor.readTransHist::samples 100 # Histogram of read transactions per sample period +system.monitor.readTransHist::mean 0.010000 # Histogram of read transactions per sample period +system.monitor.readTransHist::gmean 0 # Histogram of read transactions per sample period +system.monitor.readTransHist::stdev 0.100000 # Histogram of read transactions per sample period +system.monitor.readTransHist::0 99 99.00% 99.00% # Histogram of read transactions per sample period +system.monitor.readTransHist::1 1 1.00% 100.00% # Histogram of read transactions per sample period +system.monitor.readTransHist::2 0 0.00% 100.00% # Histogram of read transactions per sample period +system.monitor.readTransHist::3 0 0.00% 100.00% # Histogram of read transactions per sample period +system.monitor.readTransHist::4 0 0.00% 100.00% # Histogram of read transactions per sample period +system.monitor.readTransHist::5 0 0.00% 100.00% # Histogram of read transactions per sample period +system.monitor.readTransHist::6 0 0.00% 100.00% # Histogram of read transactions per sample period +system.monitor.readTransHist::7 0 0.00% 100.00% # Histogram of read transactions per sample period +system.monitor.readTransHist::8 0 0.00% 100.00% # Histogram of read transactions per sample period +system.monitor.readTransHist::9 0 0.00% 100.00% # Histogram of read transactions per sample period +system.monitor.readTransHist::10 0 0.00% 100.00% # Histogram of read transactions per sample period +system.monitor.readTransHist::11 0 0.00% 100.00% # Histogram of read transactions per sample period +system.monitor.readTransHist::12 0 0.00% 100.00% # Histogram of read transactions per sample period +system.monitor.readTransHist::13 0 0.00% 100.00% # Histogram of read transactions per sample period +system.monitor.readTransHist::14 0 0.00% 100.00% # Histogram of read transactions per sample period +system.monitor.readTransHist::15 0 0.00% 100.00% # Histogram of read transactions per sample period +system.monitor.readTransHist::16 0 0.00% 100.00% # Histogram of read transactions per sample period +system.monitor.readTransHist::17 0 0.00% 100.00% # Histogram of read transactions per sample period +system.monitor.readTransHist::18 0 0.00% 100.00% # Histogram of read transactions per sample period +system.monitor.readTransHist::19 0 0.00% 100.00% # Histogram of read transactions per sample period +system.monitor.readTransHist::total 100 # Histogram of read transactions per sample period +system.monitor.writeTransHist::samples 100 # Histogram of read transactions per sample period +system.monitor.writeTransHist::mean 33333.680000 # Histogram of read transactions per sample period +system.monitor.writeTransHist::gmean 33333.679848 # Histogram of read transactions per sample period +system.monitor.writeTransHist::stdev 3.200000 # Histogram of read transactions per sample period +system.monitor.writeTransHist::0-2047 0 0.00% 0.00% # Histogram of read transactions per sample period +system.monitor.writeTransHist::2048-4095 0 0.00% 0.00% # Histogram of read transactions per sample period +system.monitor.writeTransHist::4096-6143 0 0.00% 0.00% # Histogram of read transactions per sample period +system.monitor.writeTransHist::6144-8191 0 0.00% 0.00% # Histogram of read transactions per sample period +system.monitor.writeTransHist::8192-10239 0 0.00% 0.00% # Histogram of read transactions per sample period +system.monitor.writeTransHist::10240-12287 0 0.00% 0.00% # Histogram of read transactions per sample period +system.monitor.writeTransHist::12288-14335 0 0.00% 0.00% # Histogram of read transactions per sample period +system.monitor.writeTransHist::14336-16383 0 0.00% 0.00% # Histogram of read transactions per sample period +system.monitor.writeTransHist::16384-18431 0 0.00% 0.00% # Histogram of read transactions per sample period +system.monitor.writeTransHist::18432-20479 0 0.00% 0.00% # Histogram of read transactions per sample period +system.monitor.writeTransHist::20480-22527 0 0.00% 0.00% # Histogram of read transactions per sample period +system.monitor.writeTransHist::22528-24575 0 0.00% 0.00% # Histogram of read transactions per sample period +system.monitor.writeTransHist::24576-26623 0 0.00% 0.00% # Histogram of read transactions per sample period +system.monitor.writeTransHist::26624-28671 0 0.00% 0.00% # Histogram of read transactions per sample period +system.monitor.writeTransHist::28672-30719 0 0.00% 0.00% # Histogram of read transactions per sample period +system.monitor.writeTransHist::30720-32767 0 0.00% 0.00% # Histogram of read transactions per sample period +system.monitor.writeTransHist::32768-34815 100 100.00% 100.00% # Histogram of read transactions per sample period +system.monitor.writeTransHist::34816-36863 0 0.00% 100.00% # Histogram of read transactions per sample period +system.monitor.writeTransHist::36864-38911 0 0.00% 100.00% # Histogram of read transactions per sample period +system.monitor.writeTransHist::38912-40959 0 0.00% 100.00% # Histogram of read transactions per sample period +system.monitor.writeTransHist::total 100 # Histogram of read transactions per sample period +system.monitor.readAddrDist::total 16 # Read address distribution +system.monitor.writeAddrDist::total 16 # Write address distribution + +---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/70.tgen/test-frfcfs-toy.trc b/tests/quick/se/70.tgen/test-frfcfs-toy.trc new file mode 100644 index 000000000..a1dd3088c --- /dev/null +++ b/tests/quick/se/70.tgen/test-frfcfs-toy.trc @@ -0,0 +1,7 @@ +r,64,64,4000 +r,128,64,5000 +r,196,64,6000 +r,256,64,7000 +r,3453276,64,8000 +r,320,64,9000 +r,232123,64,500000 diff --git a/tests/quick/se/70.tgen/test-open-ops.trc b/tests/quick/se/70.tgen/test-open-ops.trc new file mode 100644 index 000000000..26aef5257 --- /dev/null +++ b/tests/quick/se/70.tgen/test-open-ops.trc @@ -0,0 +1,6 @@ +r,64,64,4000 +r,2048,64,5000 +r,128,64,6000 +r,196,64,7000 +r,12433,64,8000 +r,23223,64,1000000 diff --git a/tests/quick/se/70.tgen/test-refresh.trc b/tests/quick/se/70.tgen/test-refresh.trc new file mode 100644 index 000000000..b8c02c7dc --- /dev/null +++ b/tests/quick/se/70.tgen/test-refresh.trc @@ -0,0 +1,3 @@ +r,64,64,4000 +r, 128, 64, 7800001 +r, 196, 64, 100000000 diff --git a/tests/quick/se/70.tgen/test-writebuffer.trc b/tests/quick/se/70.tgen/test-writebuffer.trc new file mode 100644 index 000000000..d0a719bfc --- /dev/null +++ b/tests/quick/se/70.tgen/test-writebuffer.trc @@ -0,0 +1,5 @@ +r, 64, 64, 4000 +w, 128, 64, 6000 +r, 196, 64, 8000 +r, 128, 64, 10000 +r, 123143,64,100000 diff --git a/tests/quick/se/70.tgen/test-writefrfcfs.trc b/tests/quick/se/70.tgen/test-writefrfcfs.trc new file mode 100644 index 000000000..a70e112f4 --- /dev/null +++ b/tests/quick/se/70.tgen/test-writefrfcfs.trc @@ -0,0 +1,26 @@ +w,64,64,4000 +w,128,64,5000 +w,196,64,6000 +w,256,64,7000 +w,345376,64,8000 +w,23223,64,10000 +w,12367,64,11000 +w,15328,64,12000 +w,19346,64,13000 +w,26456,64,14000 +w,34576,64,15000 +w,33620,64,16000 +w,2323,64,17000 +w,67354,64,18000 +w,1258,64,19000 +w,196,64,20000 +w,256,64,21000 +w,3276,64,22000 +w,14234,64,23000 +w,23123,64,24000 +w,23333,64,25000 +w,35318,64,26000 +w,32542,64,27000 +w,8576,64,28000 +w,34576,64,29000 +w,326660,64,30000000 diff --git a/tests/quick/se/70.tgen/test.py b/tests/quick/se/70.tgen/test.py new file mode 100644 index 000000000..097617821 --- /dev/null +++ b/tests/quick/se/70.tgen/test.py @@ -0,0 +1,38 @@ +# Copyright (c) 2012 ARM Limited +# All rights reserved. +# +# The license below extends only to copyright in the software and shall +# not be construed as granting a license to any other intellectual +# property including but not limited to intellectual property relating +# to a hardware implementation of the functionality of the software +# licensed hereunder. You may use the software subject to the license +# terms below provided that you ensure that this notice is replicated +# unmodified and in its entirety in all distributions of the software, +# modified or unmodified, in source code or in binary form. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer; +# redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution; +# neither the name of the copyright holders nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Andreas Hansson + +maxtick = 100000000000 diff --git a/tests/quick/se/70.tgen/tgen-simple-mem.cfg b/tests/quick/se/70.tgen/tgen-simple-mem.cfg new file mode 100644 index 000000000..532f1ef21 --- /dev/null +++ b/tests/quick/se/70.tgen/tgen-simple-mem.cfg @@ -0,0 +1,27 @@ +# This format supports comments using the '#' symbol as the leading +# character of the line +# +# The file format contains [STATE]+ [INIT] [TRANSITION]+ in any order, +# where the states are the nodes in the graph, init describes what +# state to start in, and transition describes the edges of the graph. +# +# STATE +# +# State IDLE idles +# +# States LINEAR and RANDOM have additional +# +# +# +# State TRACE plays back a pre-recorded trace once +# +# Addresses are expressed as decimal numbers, both in the +# configuration and the trace file. The period in the linear and +# random state is from a uniform random distribution over the +# interval. If a specific value is desired, then the min and max can +# be set to the same value. +STATE 0 1000000 TRACE tests/quick/se/70.tgen/tgen-simple-mem.trc 100 +STATE 1 1000000000 RANDOM 0 0 134217728 64 30000 30000 0 +INIT 0 +TRANSITION 0 1 1 +TRANSITION 1 1 1 diff --git a/tests/quick/se/70.tgen/tgen-simple-mem.trc b/tests/quick/se/70.tgen/tgen-simple-mem.trc new file mode 100644 index 000000000..e260f8a65 --- /dev/null +++ b/tests/quick/se/70.tgen/tgen-simple-mem.trc @@ -0,0 +1,2 @@ +r,19088743,64,1000 +w,48879,64,4000