Add in code that lays the ground work for setting flags.
--HG-- extra : convert_revision : e4fcb64d45804700a0ef34e8acf5615b66e2a527
This commit is contained in:
Gabe Black
parent
77aa98d0f8
commit
efce09e958
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@ -162,6 +162,7 @@ def template MicroRegOpExecute {{
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%(op_decl)s;
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%(op_rd)s;
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%(code)s;
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%(flag_code)s;
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//Write the resulting state to the execution context
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if(fault == NoFault)
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@ -181,6 +182,7 @@ def template MicroRegOpImmExecute {{
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%(op_decl)s;
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%(op_rd)s;
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%(code)s;
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%(flag_code)s;
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//Write the resulting state to the execution context
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if(fault == NoFault)
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@ -304,11 +306,11 @@ def template MicroRegOpImmConstructor {{
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let {{
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class RegOp(X86Microop):
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def __init__(self, dest, src1, src2):
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def __init__(self, dest, src1, src2, setStatus):
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self.dest = dest
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self.src1 = src1
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self.src2 = src2
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self.setStatus = False
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self.setStatus = setStatus
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self.dataSize = "env.dataSize"
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self.ext = 0
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@ -326,11 +328,11 @@ let {{
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return allocator
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class RegOpImm(X86Microop):
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def __init__(self, dest, src1, imm8):
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def __init__(self, dest, src1, imm8, setStatus):
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self.dest = dest
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self.src1 = src1
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self.imm8 = imm8
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self.setStatus = False
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self.setStatus = setStatus
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self.dataSize = "env.dataSize"
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self.ext = 0
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@ -356,20 +358,22 @@ let {{
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decoder_output = ""
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exec_output = ""
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def setUpMicroRegOp(name, Name, base, code, child):
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def setUpMicroRegOp(name, Name, base, code, child, flagCode):
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global header_output
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global decoder_output
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global exec_output
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global microopClasses
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iop = InstObjParams(name, Name, base, {"code" : code})
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iop = InstObjParams(name, Name, base,
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{"code" : code,
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"flag_code" : flagCode})
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header_output += MicroRegOpDeclare.subst(iop)
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decoder_output += MicroRegOpConstructor.subst(iop)
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exec_output += MicroRegOpExecute.subst(iop)
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microopClasses[name] = child
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def defineMicroRegOp(mnemonic, code):
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def defineMicroRegOp(mnemonic, code, flagCode):
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Name = mnemonic
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name = mnemonic.lower()
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@ -382,31 +386,31 @@ let {{
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# Build the all register version of this micro op
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class RegOpChild(RegOp):
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def __init__(self, dest, src1, src2):
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super(RegOpChild, self).__init__(dest, src1, src2)
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def __init__(self, dest, src1, src2, setStatus=False):
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super(RegOpChild, self).__init__(dest, src1, src2, setStatus)
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self.className = Name
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self.mnemonic = name
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setUpMicroRegOp(name, Name, "RegOp", regCode, RegOpChild);
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setUpMicroRegOp(name, Name, "RegOp", regCode, RegOpChild, flagCode);
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# Build the immediate version of this micro op
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class RegOpChildImm(RegOpImm):
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def __init__(self, dest, src1, src2):
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super(RegOpChildImm, self).__init__(dest, src1, src2)
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def __init__(self, dest, src1, src2, setStatus=False):
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super(RegOpChildImm, self).__init__(dest, src1, src2, setStatus)
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self.className = Name + "Imm"
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self.mnemonic = name + "i"
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setUpMicroRegOp(name + "i", Name + "Imm", "RegOpImm", immCode, RegOpChildImm);
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setUpMicroRegOp(name + "i", Name + "Imm", "RegOpImm", immCode, RegOpChildImm, flagCode);
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defineMicroRegOp('Add', 'DestReg = merge(DestReg, SrcReg1 + op2, dataSize)') #Needs to set OF,CF,SF
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defineMicroRegOp('Or', 'DestReg = merge(DestReg, SrcReg1 | op2, dataSize)')
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defineMicroRegOp('Adc', 'DestReg = merge(DestReg, SrcReg1 + op2, dataSize)') #Needs to add in CF, set OF,CF,SF
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defineMicroRegOp('Sbb', 'DestReg = merge(DestReg, SrcReg1 - op2, dataSize)') #Needs to subtract CF, set OF,CF,SF
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defineMicroRegOp('And', 'DestReg = merge(DestReg, SrcReg1 & op2, dataSize)')
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defineMicroRegOp('Sub', 'DestReg = merge(DestReg, SrcReg1 - op2, dataSize)') #Needs to set OF,CF,SF
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defineMicroRegOp('Xor', 'DestReg = merge(DestReg, SrcReg1 ^ op2, dataSize)')
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defineMicroRegOp('Cmp', 'DestReg = merge(DestReg, DestReg - op2, dataSize)') #Needs to set OF,CF,SF and not DestReg
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defineMicroRegOp('Mov', 'DestReg = merge(SrcReg1, op2, dataSize)')
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defineMicroRegOp('Add', 'DestReg = merge(DestReg, SrcReg1 + op2, dataSize)', "") #Needs to set OF,CF,SF
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defineMicroRegOp('Or', 'DestReg = merge(DestReg, SrcReg1 | op2, dataSize)', "")
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defineMicroRegOp('Adc', 'DestReg = merge(DestReg, SrcReg1 + op2, dataSize)', "") #Needs to add in CF, set OF,CF,SF
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defineMicroRegOp('Sbb', 'DestReg = merge(DestReg, SrcReg1 - op2, dataSize)', "") #Needs to subtract CF, set OF,CF,SF
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defineMicroRegOp('And', 'DestReg = merge(DestReg, SrcReg1 & op2, dataSize)', "")
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defineMicroRegOp('Sub', 'DestReg = merge(DestReg, SrcReg1 - op2, dataSize)', "") #Needs to set OF,CF,SF
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defineMicroRegOp('Xor', 'DestReg = merge(DestReg, SrcReg1 ^ op2, dataSize)', "")
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defineMicroRegOp('Cmp', 'DestReg = merge(DestReg, DestReg - op2, dataSize)', "") #Needs to set OF,CF,SF and not DestReg
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defineMicroRegOp('Mov', 'DestReg = merge(SrcReg1, op2, dataSize)', "")
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# This has it's own function because Wr ops have implicit destinations
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def defineMicroRegOpWr(mnemonic, code):
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@ -423,20 +427,20 @@ let {{
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# Build the all register version of this micro op
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class RegOpChild(RegOp):
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def __init__(self, src1, src2):
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super(RegOpChild, self).__init__("NUM_INTREGS", src1, src2)
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super(RegOpChild, self).__init__("NUM_INTREGS", src1, src2, False)
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self.className = Name
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self.mnemonic = name
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setUpMicroRegOp(name, Name, "RegOp", regCode, RegOpChild);
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setUpMicroRegOp(name, Name, "RegOp", regCode, RegOpChild, "");
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# Build the immediate version of this micro op
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class RegOpChildImm(RegOpImm):
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def __init__(self, src1, src2):
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super(RegOpChildImm, self).__init__("NUM_INTREGS", src1, src2)
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super(RegOpChildImm, self).__init__("NUM_INTREGS", src1, src2, False)
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self.className = Name + "Imm"
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self.mnemonic = name + "i"
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setUpMicroRegOp(name + "i", Name + "Imm", "RegOpImm", immCode, RegOpChildImm);
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setUpMicroRegOp(name + "i", Name + "Imm", "RegOpImm", immCode, RegOpChildImm, "");
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defineMicroRegOpWr('Wrip', 'RIP = SrcReg1 + op2')
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@ -447,11 +451,11 @@ let {{
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class RegOpChild(RegOp):
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def __init__(self, dest, src1 = "NUM_INTREGS"):
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super(RegOpChild, self).__init__(dest, src1, "NUM_INTREGS")
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super(RegOpChild, self).__init__(dest, src1, "NUM_INTREGS", False)
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self.className = Name
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self.mnemonic = name
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setUpMicroRegOp(name, Name, "RegOp", code, RegOpChild);
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setUpMicroRegOp(name, Name, "RegOp", code, RegOpChild, "");
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defineMicroRegOpRd('Rdip', 'DestReg = RIP')
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@ -461,11 +465,11 @@ let {{
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class RegOpChild(RegOpImm):
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def __init__(self, dest, src1, src2):
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super(RegOpChild, self).__init__(dest, src1, src2)
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super(RegOpChild, self).__init__(dest, src1, src2, False)
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self.className = Name
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self.mnemonic = name
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setUpMicroRegOp(name, Name, "RegOpImm", code, RegOpChild);
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setUpMicroRegOp(name, Name, "RegOpImm", code, RegOpChild, "");
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defineMicroRegOpImm('Sext', '''
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IntReg val = SrcReg1;
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