inorder: cleanup dprintfs in cache unit
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parent
078f914e69
commit
eedd04e894
2 changed files with 7 additions and 36 deletions
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@ -1370,11 +1370,6 @@ InOrderCPU::readMiscRegNoEffect(int misc_reg, ThreadID tid)
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MiscReg
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InOrderCPU::readMiscReg(int misc_reg, ThreadID tid)
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{
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DPRINTF(InOrderCPU, "MiscReg: %i\n", misc_reg);
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DPRINTF(InOrderCPU, "tid: %i\n", tid);
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DPRINTF(InOrderCPU, "tcBase: %x\n", tcBase(tid));
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DPRINTF(InOrderCPU, "isa-tid: %x\n", &isa[tid]);
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return isa[tid].readMiscReg(misc_reg, tcBase(tid));
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}
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@ -98,8 +98,6 @@ CacheUnit::CachePort::recvStatusChange(Status status)
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bool
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CacheUnit::CachePort::recvTiming(Packet *pkt)
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{
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DPRINTF(InOrderCachePort, "RecvTiming: Pkt %x,\n", pkt->getAddr());
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if (pkt->isError())
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DPRINTF(InOrderCachePort, "Got error packet back for address: %x\n",
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pkt->getAddr());
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@ -393,10 +391,9 @@ CacheUnit::setupMemRequest(DynInstPtr inst, CacheReqPtr cache_req,
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if (cache_req->memReq == NULL) {
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cache_req->memReq =
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new Request(cpu->asid[tid], aligned_addr, acc_size, flags,
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inst->instAddr(), cpu->readCpuId(), //@todo: use context id
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inst->instAddr(),
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cpu->readCpuId(), //@todo: use context id
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tid);
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DPRINTF(InOrderCachePort, "[sn:%i] Created memReq @%x, ->%x\n",
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inst->seqNum, &cache_req->memReq, cache_req->memReq);
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}
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} else {
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assert(inst->splitInst);
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@ -790,14 +787,6 @@ CacheUnit::execute(int slot_num)
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//@todo: check that timing translation is finished here
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RequestPtr mem_req = cache_req->memReq;
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DPRINTF(InOrderCachePort,
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"[tid:%i]: [sn:%i]: cSwap:%i LLSC:%i isSwap:%i isCond:%i\n",
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tid, inst->seqNum,
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mem_req->isCondSwap(),
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mem_req->isLLSC(),
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mem_req->isSwap(),
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inst->isStoreConditional());
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if (mem_req->isCondSwap() || mem_req->isLLSC() || mem_req->isSwap()) {
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DPRINTF(InOrderCachePort, "Detected Conditional Store Inst.\n");
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@ -820,7 +809,6 @@ CacheUnit::execute(int slot_num)
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DPRINTF(InOrderCachePort, "Store Instruction Finished Completion.\n");
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//@todo: if split inst save data
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finishCacheUnitReq(inst, cache_req);
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}
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break;
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@ -892,11 +880,9 @@ CacheUnit::buildDataPacket(CacheRequest *cache_req)
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cache_req->pktCmd,
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Packet::Broadcast,
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cache_req->instIdx);
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DPRINTF(InOrderCachePort, "[slot:%i]: Slot marked for %x [pkt:%x->%x]\n",
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DPRINTF(InOrderCachePort, "[slot:%i]: Slot marked for %x\n",
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cache_req->getSlot(),
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cache_req->dataPkt->getAddr(),
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&cache_req->dataPkt,
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cache_req->dataPkt);
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cache_req->dataPkt->getAddr());
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cache_req->dataPkt->hasSlot = true;
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cache_req->dataPkt->dataStatic(cache_req->reqData);
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@ -1062,10 +1048,8 @@ CacheUnit::processCacheCompletion(PacketPtr pkt)
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CacheReqPacket* cache_pkt = dynamic_cast<CacheReqPacket*>(pkt);
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assert(cache_pkt);
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DPRINTF(InOrderCachePort, "Finished request for %x [pkt:%x->%x]\n",
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pkt->getAddr(), &cache_pkt, cache_pkt);
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DPRINTF(InOrderCachePort, "Finished request for %x\n", pkt->getAddr());
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//@todo: process Squashed Completion
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if (processSquash(cache_pkt))
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return;
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@ -1156,8 +1140,6 @@ CacheUnit::processCacheCompletion(PacketPtr pkt)
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cache_pkt->getSize()));
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}
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DPRINTF(InOrderCachePort, "Deleting packets %x (%x).\n",
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cache_pkt, cache_req->dataPkt);
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if (split_pkt) {
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delete split_pkt;
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@ -1346,20 +1328,14 @@ CacheRequest::clearRequest()
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if (reqData && !splitAccess)
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delete [] reqData;
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if (memReq) {
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DPRINTF(InOrderCachePort, "Clearing request for %x...%x\n",
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memReq->getVaddr(), (memReq->hasPaddr()) ? memReq->getPaddr() : 0);
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if (memReq)
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delete memReq;
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}
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if (dataPkt)
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delete dataPkt;
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} else {
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if (dataPkt) {
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if (dataPkt)
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dataPkt->hasSlot = false;
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DPRINTF(InOrderCachePort, "[slot:%i]: Slot unmarked for %x for [pkt:%x->%x]\n",
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getSlot(), dataPkt->getAddr(), &dataPkt, dataPkt);
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}
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}
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memReq = NULL;
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