X86: Put the StoreCheck flag with the others, and don't collide with other flags.

src/arch/x86/insts/microldstop.hh

@@ -68,7 +68,8 @@ namespace X86ISA
     static const int FlagShift = 4;
     enum FlagBit {
         CPL0FlagBit = 1,
-        AddrSizeFlagBit = 2
+        AddrSizeFlagBit = 2,
+        StoreCheck = 4
     };
 
     /**

src/arch/x86/isa/microops/ldstop.isa

@@ -439,9 +439,9 @@ let {{
 
     defineMicroLoadOp('Ld', 'Data = merge(Data, Mem, dataSize);')
     defineMicroLoadOp('Ldst', 'Data = merge(Data, Mem, dataSize);',
-            'X86ISA::StoreCheck')
+            '(StoreCheck << FlagShift)')
     defineMicroLoadOp('Ldstl', 'Data = merge(Data, Mem, dataSize);',
-            'X86ISA::StoreCheck | Request::LOCKED')
+            '(StoreCheck << FlagShift) | Request::LOCKED')
     defineMicroLoadOp('Ldfp', 'FpData.uqw = Mem;')
 
     def defineMicroStoreOp(mnemonic, code, \

src/arch/x86/tlb.cc

@@ -193,7 +193,7 @@ TLB::translate(RequestPtr req, ThreadContext *tc, Translation *translation,
     Addr vaddr = req->getVaddr();
     DPRINTF(TLB, "Translating vaddr %#x.\n", vaddr);
     uint32_t flags = req->getFlags();
-    bool storeCheck = flags & StoreCheck;
+    bool storeCheck = flags & (StoreCheck << FlagShift);
 
     int seg = flags & SegmentFlagMask;
 

src/arch/x86/tlb.hh

@@ -79,8 +79,6 @@ namespace X86ISA
 {
     class Walker;
 
-    static const unsigned StoreCheck = 1 << NUM_SEGMENTREGS;
-
     class TLB : public BaseTLB
     {
       protected: