params: Convert the CPU objects to use the auto generated param structs.
A whole bunch of stuff has been converted to use the new params stuff, but the CPU wasn't one of them. While we're at it, make some things a bit more stylish. Most of the work was done by Gabe, I just cleaned stuff up a bit more at the end.
This commit is contained in:
parent
3448a12208
commit
ee62a0fec8
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@ -40,6 +40,8 @@
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#include "cpu/base.hh"
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#include "cpu/exetrace.hh"
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#include "params/DerivO3CPU.hh"
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using namespace std;
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std::string MiscRegFile::miscRegNames[NumMiscRegs] =
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@ -170,11 +172,12 @@ void
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MiscRegFile::reset(std::string core_name, unsigned num_threads,
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unsigned num_vpes, BaseCPU *_cpu)
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{
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DPRINTF(MipsPRA, "Resetting CP0 State with %i TCs and %i VPEs\n",
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num_threads, num_vpes);
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cpu = _cpu;
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const BaseCPU::Params *p = _cpu->params;
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TheISA::CoreSpecific &cp = cpu->coreParams;
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// Do Default CP0 initialization HERE
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// Do Initialization for MT cores here (eventually use
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@ -183,10 +186,10 @@ MiscRegFile::reset(std::string core_name, unsigned num_threads,
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DPRINTF(MipsPRA, "Initializing CP0 State.... ");
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MiscReg ProcID = readRegNoEffect(PRId);
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replaceBits(ProcID,PRIdCoOp_HI,PRIdCoOp_LO,p->coreParams.CP0_PRId_CompanyOptions);
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replaceBits(ProcID,PRIdCoID_HI,PRIdCoID_LO,p->coreParams.CP0_PRId_CompanyID);
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replaceBits(ProcID,PRIdProc_ID_HI,PRIdProc_ID_LO,p->coreParams.CP0_PRId_ProcessorID);
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replaceBits(ProcID,PRIdRev_HI,PRIdRev_LO,p->coreParams.CP0_PRId_Revision);
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replaceBits(ProcID,PRIdCoOp_HI,PRIdCoOp_LO,cp.CP0_PRId_CompanyOptions);
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replaceBits(ProcID,PRIdCoID_HI,PRIdCoID_LO,cp.CP0_PRId_CompanyID);
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replaceBits(ProcID,PRIdProc_ID_HI,PRIdProc_ID_LO,cp.CP0_PRId_ProcessorID);
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replaceBits(ProcID,PRIdRev_HI,PRIdRev_LO,cp.CP0_PRId_Revision);
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setRegNoEffect(PRId,ProcID);
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// Now, create Write Mask for ProcID register
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MiscReg ProcID_Mask = 0; // Read-Only register
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@ -195,11 +198,11 @@ MiscRegFile::reset(std::string core_name, unsigned num_threads,
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// Config
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MiscReg cfg = readRegNoEffect(Config);
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replaceBits(cfg, Config_BE_HI, Config_BE_LO, p->coreParams.CP0_Config_BE);
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replaceBits(cfg, Config_AT_HI, Config_AT_LO, p->coreParams.CP0_Config_AT);
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replaceBits(cfg, Config_AR_HI, Config_AR_LO, p->coreParams.CP0_Config_AR);
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replaceBits(cfg, Config_MT_HI, Config_MT_LO, p->coreParams.CP0_Config_MT);
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replaceBits(cfg, Config_VI_HI, Config_VI_LO, p->coreParams.CP0_Config_VI);
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replaceBits(cfg, Config_BE_HI, Config_BE_LO, cp.CP0_Config_BE);
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replaceBits(cfg, Config_AT_HI, Config_AT_LO, cp.CP0_Config_AT);
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replaceBits(cfg, Config_AR_HI, Config_AR_LO, cp.CP0_Config_AR);
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replaceBits(cfg, Config_MT_HI, Config_MT_LO, cp.CP0_Config_MT);
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replaceBits(cfg, Config_VI_HI, Config_VI_LO, cp.CP0_Config_VI);
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replaceBits(cfg, Config_M, 1);
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setRegNoEffect(Config, cfg);
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// Now, create Write Mask for Config register
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@ -209,20 +212,20 @@ MiscRegFile::reset(std::string core_name, unsigned num_threads,
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// Config1
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MiscReg cfg1 = readRegNoEffect(Config1);
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replaceBits(cfg1, Config1_MMUSize_HI, Config1_MMUSize_LO, p->coreParams.CP0_Config1_MMU);
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replaceBits(cfg1, Config1_IS_HI, Config1_IS_LO, p->coreParams.CP0_Config1_IS);
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replaceBits(cfg1, Config1_IL_HI, Config1_IL_LO, p->coreParams.CP0_Config1_IL);
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replaceBits(cfg1, Config1_IA_HI, Config1_IA_LO, p->coreParams.CP0_Config1_IA);
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replaceBits(cfg1, Config1_DS_HI, Config1_DS_LO, p->coreParams.CP0_Config1_DS);
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replaceBits(cfg1, Config1_DL_HI, Config1_DL_LO, p->coreParams.CP0_Config1_DL);
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replaceBits(cfg1, Config1_DA_HI, Config1_DA_LO, p->coreParams.CP0_Config1_DA);
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replaceBits(cfg1, Config1_FP_HI, Config1_FP_LO, p->coreParams.CP0_Config1_FP);
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replaceBits(cfg1, Config1_EP_HI, Config1_EP_LO, p->coreParams.CP0_Config1_EP);
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replaceBits(cfg1, Config1_WR_HI, Config1_WR_LO, p->coreParams.CP0_Config1_WR);
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replaceBits(cfg1, Config1_MD_HI, Config1_MD_LO, p->coreParams.CP0_Config1_MD);
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replaceBits(cfg1, Config1_C2_HI, Config1_C2_LO, p->coreParams.CP0_Config1_C2);
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replaceBits(cfg1, Config1_PC_HI, Config1_PC_LO, p->coreParams.CP0_Config1_PC);
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replaceBits(cfg1, Config1_M, p->coreParams.CP0_Config1_M);
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replaceBits(cfg1, Config1_MMUSize_HI, Config1_MMUSize_LO, cp.CP0_Config1_MMU);
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replaceBits(cfg1, Config1_IS_HI, Config1_IS_LO, cp.CP0_Config1_IS);
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replaceBits(cfg1, Config1_IL_HI, Config1_IL_LO, cp.CP0_Config1_IL);
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replaceBits(cfg1, Config1_IA_HI, Config1_IA_LO, cp.CP0_Config1_IA);
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replaceBits(cfg1, Config1_DS_HI, Config1_DS_LO, cp.CP0_Config1_DS);
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replaceBits(cfg1, Config1_DL_HI, Config1_DL_LO, cp.CP0_Config1_DL);
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replaceBits(cfg1, Config1_DA_HI, Config1_DA_LO, cp.CP0_Config1_DA);
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replaceBits(cfg1, Config1_FP_HI, Config1_FP_LO, cp.CP0_Config1_FP);
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replaceBits(cfg1, Config1_EP_HI, Config1_EP_LO, cp.CP0_Config1_EP);
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replaceBits(cfg1, Config1_WR_HI, Config1_WR_LO, cp.CP0_Config1_WR);
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replaceBits(cfg1, Config1_MD_HI, Config1_MD_LO, cp.CP0_Config1_MD);
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replaceBits(cfg1, Config1_C2_HI, Config1_C2_LO, cp.CP0_Config1_C2);
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replaceBits(cfg1, Config1_PC_HI, Config1_PC_LO, cp.CP0_Config1_PC);
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replaceBits(cfg1, Config1_M, cp.CP0_Config1_M);
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setRegNoEffect(Config1, cfg1);
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// Now, create Write Mask for Config register
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MiscReg cfg1_Mask = 0; // Read Only Register
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@ -231,15 +234,15 @@ MiscRegFile::reset(std::string core_name, unsigned num_threads,
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// Config2
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MiscReg cfg2 = readRegNoEffect(Config2);
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replaceBits(cfg2, Config2_TU_HI, Config2_TU_LO, p->coreParams.CP0_Config2_TU);
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replaceBits(cfg2, Config2_TS_HI, Config2_TS_LO, p->coreParams.CP0_Config2_TS);
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replaceBits(cfg2, Config2_TL_HI, Config2_TL_LO, p->coreParams.CP0_Config2_TL);
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replaceBits(cfg2, Config2_TA_HI, Config2_TA_LO, p->coreParams.CP0_Config2_TA);
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replaceBits(cfg2, Config2_SU_HI, Config2_SU_LO, p->coreParams.CP0_Config2_SU);
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replaceBits(cfg2, Config2_SS_HI, Config2_SS_LO, p->coreParams.CP0_Config2_SS);
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replaceBits(cfg2, Config2_SL_HI, Config2_SL_LO, p->coreParams.CP0_Config2_SL);
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replaceBits(cfg2, Config2_SA_HI, Config2_SA_LO, p->coreParams.CP0_Config2_SA);
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replaceBits(cfg2, Config2_M, p->coreParams.CP0_Config2_M);
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replaceBits(cfg2, Config2_TU_HI, Config2_TU_LO, cp.CP0_Config2_TU);
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replaceBits(cfg2, Config2_TS_HI, Config2_TS_LO, cp.CP0_Config2_TS);
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replaceBits(cfg2, Config2_TL_HI, Config2_TL_LO, cp.CP0_Config2_TL);
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replaceBits(cfg2, Config2_TA_HI, Config2_TA_LO, cp.CP0_Config2_TA);
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replaceBits(cfg2, Config2_SU_HI, Config2_SU_LO, cp.CP0_Config2_SU);
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replaceBits(cfg2, Config2_SS_HI, Config2_SS_LO, cp.CP0_Config2_SS);
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replaceBits(cfg2, Config2_SL_HI, Config2_SL_LO, cp.CP0_Config2_SL);
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replaceBits(cfg2, Config2_SA_HI, Config2_SA_LO, cp.CP0_Config2_SA);
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replaceBits(cfg2, Config2_M, cp.CP0_Config2_M);
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setRegNoEffect(Config2, cfg2);
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// Now, create Write Mask for Config register
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MiscReg cfg2_Mask = 0x7000F000; // Read Only Register
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@ -248,14 +251,14 @@ MiscRegFile::reset(std::string core_name, unsigned num_threads,
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// Config3
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MiscReg cfg3 = readRegNoEffect(Config3);
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replaceBits(cfg3, Config3_DSPP_HI, Config3_DSPP_LO, p->coreParams.CP0_Config3_DSPP);
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replaceBits(cfg3, Config3_LPA_HI, Config3_LPA_LO, p->coreParams.CP0_Config3_LPA);
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replaceBits(cfg3, Config3_VEIC_HI, Config3_VEIC_LO, p->coreParams.CP0_Config3_VEIC);
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replaceBits(cfg3, Config3_VINT_HI, Config3_VINT_LO, p->coreParams.CP0_Config3_VInt);
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replaceBits(cfg3, Config3_SP_HI, Config3_SP_LO, p->coreParams.CP0_Config3_SP);
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replaceBits(cfg3, Config3_MT_HI, Config3_MT_LO, p->coreParams.CP0_Config3_MT);
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replaceBits(cfg3, Config3_SM_HI, Config3_SM_LO, p->coreParams.CP0_Config3_SM);
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replaceBits(cfg3, Config3_TL_HI, Config3_TL_LO, p->coreParams.CP0_Config3_TL);
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replaceBits(cfg3, Config3_DSPP_HI, Config3_DSPP_LO, cp.CP0_Config3_DSPP);
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replaceBits(cfg3, Config3_LPA_HI, Config3_LPA_LO, cp.CP0_Config3_LPA);
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replaceBits(cfg3, Config3_VEIC_HI, Config3_VEIC_LO, cp.CP0_Config3_VEIC);
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replaceBits(cfg3, Config3_VINT_HI, Config3_VINT_LO, cp.CP0_Config3_VInt);
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replaceBits(cfg3, Config3_SP_HI, Config3_SP_LO, cp.CP0_Config3_SP);
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replaceBits(cfg3, Config3_MT_HI, Config3_MT_LO, cp.CP0_Config3_MT);
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replaceBits(cfg3, Config3_SM_HI, Config3_SM_LO, cp.CP0_Config3_SM);
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replaceBits(cfg3, Config3_TL_HI, Config3_TL_LO, cp.CP0_Config3_TL);
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setRegNoEffect(Config3, cfg3);
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// Now, create Write Mask for Config register
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MiscReg cfg3_Mask = 0; // Read Only Register
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@ -264,7 +267,7 @@ MiscRegFile::reset(std::string core_name, unsigned num_threads,
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// EBase - CPUNum
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MiscReg EB = readRegNoEffect(EBase);
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replaceBits(EB, EBase_CPUNum_HI, EBase_CPUNum_LO, p->coreParams.CP0_EBase_CPUNum);
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replaceBits(EB, EBase_CPUNum_HI, EBase_CPUNum_LO, cp.CP0_EBase_CPUNum);
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replaceBits(EB, 31, 31, 1);
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setRegNoEffect(EBase, EB);
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// Now, create Write Mask for Config register
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@ -275,7 +278,7 @@ MiscRegFile::reset(std::string core_name, unsigned num_threads,
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// SRS Control - HSS (Highest Shadow Set)
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MiscReg SC = readRegNoEffect(SRSCtl);
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replaceBits(SC, SRSCtl_HSS_HI,SRSCtl_HSS_LO,p->coreParams.CP0_SrsCtl_HSS);
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replaceBits(SC, SRSCtl_HSS_HI,SRSCtl_HSS_LO,cp.CP0_SrsCtl_HSS);
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setRegNoEffect(SRSCtl, SC);
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// Now, create Write Mask for the SRS Ctl register
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MiscReg SC_Mask = 0x0000F3C0;
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@ -284,8 +287,8 @@ MiscRegFile::reset(std::string core_name, unsigned num_threads,
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// IntCtl - IPTI, IPPCI
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MiscReg IC = readRegNoEffect(IntCtl);
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replaceBits(IC, IntCtl_IPTI_HI,IntCtl_IPTI_LO,p->coreParams.CP0_IntCtl_IPTI);
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replaceBits(IC, IntCtl_IPPCI_HI,IntCtl_IPPCI_LO,p->coreParams.CP0_IntCtl_IPPCI);
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replaceBits(IC, IntCtl_IPTI_HI,IntCtl_IPTI_LO,cp.CP0_IntCtl_IPTI);
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replaceBits(IC, IntCtl_IPPCI_HI,IntCtl_IPPCI_LO,cp.CP0_IntCtl_IPPCI);
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setRegNoEffect(IntCtl, IC);
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// Now, create Write Mask for the IntCtl register
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MiscReg IC_Mask = 0x000003E0;
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@ -294,7 +297,7 @@ MiscRegFile::reset(std::string core_name, unsigned num_threads,
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// Watch Hi - M - FIXME (More than 1 Watch register)
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MiscReg WHi = readRegNoEffect(WatchHi0);
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replaceBits(WHi, WatchHi_M, p->coreParams.CP0_WatchHi_M);
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replaceBits(WHi, WatchHi_M, cp.CP0_WatchHi_M);
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setRegNoEffect(WatchHi0, WHi);
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// Now, create Write Mask for the IntCtl register
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MiscReg wh_Mask = 0x7FFF0FFF;
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@ -303,8 +306,8 @@ MiscRegFile::reset(std::string core_name, unsigned num_threads,
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// Perf Ctr - M - FIXME (More than 1 PerfCnt Pair)
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MiscReg PCtr = readRegNoEffect(PerfCnt0);
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replaceBits(PCtr, PerfCntCtl_M, p->coreParams.CP0_PerfCtr_M);
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replaceBits(PCtr, PerfCntCtl_W, p->coreParams.CP0_PerfCtr_W);
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replaceBits(PCtr, PerfCntCtl_M, cp.CP0_PerfCtr_M);
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replaceBits(PCtr, PerfCntCtl_W, cp.CP0_PerfCtr_W);
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setRegNoEffect(PerfCnt0, PCtr);
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// Now, create Write Mask for the IntCtl register
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MiscReg pc_Mask = 0x00007FF;
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@ -322,7 +325,7 @@ MiscRegFile::reset(std::string core_name, unsigned num_threads,
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// PageGrain
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MiscReg pagegrain = readRegNoEffect(PageGrain);
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replaceBits(pagegrain,PageGrain_ESP,p->coreParams.CP0_Config3_SP);
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replaceBits(pagegrain,PageGrain_ESP,cp.CP0_Config3_SP);
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setRegNoEffect(PageGrain, pagegrain);
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// Now, create Write Mask for the IntCtl register
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MiscReg pg_Mask = 0x10000000;
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@ -26,7 +26,7 @@
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#
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# Authors: Nathan Binkert
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from m5.SimObject import SimObject
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from MemObject import MemObject
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from m5.params import *
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from m5.proxy import *
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from m5 import build_env
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elif build_env['TARGET_ISA'] == 'arm':
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from ArmTLB import ArmTLB, ArmDTB, ArmITB, ArmUTB
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class BaseCPU(SimObject):
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class BaseCPU(MemObject):
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type = 'BaseCPU'
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abstract = True
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system = Param.System(Parent.any, "system object")
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cpu_id = Param.Int("CPU identifier")
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numThreads = Param.Unsigned(1, "number of HW thread contexts")
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function_trace = Param.Bool(False, "Enable function trace")
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function_trace_start = Param.Tick(0, "Cycle to start function trace")
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checker = Param.BaseCPU("checker CPU")
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if build_env['FULL_SYSTEM']:
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profile = Param.Latency('0ns', "trace the kernel stack")
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do_quiesce = Param.Bool(True, "enable quiesce instructions")
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do_checkpoint_insts = Param.Bool(True,
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"enable checkpoint pseudo instructions")
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44
src/cpu/CheckerCPU.py
Normal file
44
src/cpu/CheckerCPU.py
Normal file
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# Copyright (c) 2007 The Regents of The University of Michigan
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# All rights reserved.
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#
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# Redistribution and use in source and binary forms, with or without
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# modification, are permitted provided that the following conditions are
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# met: redistributions of source code must retain the above copyright
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# notice, this list of conditions and the following disclaimer;
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# redistributions in binary form must reproduce the above copyright
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# notice, this list of conditions and the following disclaimer in the
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# documentation and/or other materials provided with the distribution;
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# neither the name of the copyright holders nor the names of its
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# contributors may be used to endorse or promote products derived from
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# this software without specific prior written permission.
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#
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# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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#
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# Authors: Nathan Binkert
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from m5.params import *
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from m5 import build_env
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from BaseCPU import BaseCPU
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class CheckerCPU(BaseCPU):
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type = 'CheckerCPU'
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abstract = True
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exitOnError = Param.Bool(False, "Exit on an error")
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updateOnError = Param.Bool(False,
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"Update the checker with the main CPU's state on an error")
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warnOnlyOnLoadError = Param.Bool(False,
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"If a load result is incorrect, only print a warning and do not exit")
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function_trace = Param.Bool(False, "Enable function trace")
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function_trace_start = Param.Tick(0, "Cycle to start function trace")
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if build_env['FULL_SYSTEM']:
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profile = Param.Latency('0ns', "trace the kernel stack")
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@ -71,6 +71,7 @@ temp_cpu_list = env['CPU_MODELS'][:]
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if env['USE_CHECKER']:
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temp_cpu_list.append('CheckerCPU')
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SimObject('CheckerCPU.py')
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# Generate header.
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def gen_cpu_exec_signatures(target, source, env):
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@ -37,17 +37,17 @@
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#include "base/loader/symtab.hh"
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#include "base/misc.hh"
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#include "base/output.hh"
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#include "base/trace.hh"
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#include "cpu/base.hh"
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#include "cpu/cpuevent.hh"
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#include "cpu/thread_context.hh"
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#include "cpu/profile.hh"
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#include "params/BaseCPU.hh"
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#include "sim/sim_exit.hh"
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#include "sim/process.hh"
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#include "sim/sim_events.hh"
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#include "sim/system.hh"
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#include "base/trace.hh"
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// Hack
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#include "sim/stat_control.hh"
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@ -95,13 +95,13 @@ CPUProgressEvent::description() const
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#if FULL_SYSTEM
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BaseCPU::BaseCPU(Params *p)
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: MemObject(makeParams(p->name)), clock(p->clock), instCnt(0),
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||||
params(p), number_of_threads(p->numberOfThreads), system(p->system),
|
||||
: MemObject(p), clock(p->clock), instCnt(0),
|
||||
number_of_threads(p->numThreads), system(p->system),
|
||||
phase(p->phase)
|
||||
#else
|
||||
BaseCPU::BaseCPU(Params *p)
|
||||
: MemObject(makeParams(p->name)), clock(p->clock), params(p),
|
||||
number_of_threads(p->numberOfThreads), system(p->system),
|
||||
: MemObject(p), clock(p->clock),
|
||||
number_of_threads(p->numThreads), system(p->system),
|
||||
phase(p->phase)
|
||||
#endif
|
||||
{
|
||||
|
@ -166,34 +166,25 @@ BaseCPU::BaseCPU(Params *p)
|
|||
}
|
||||
|
||||
functionTracingEnabled = false;
|
||||
if (p->functionTrace) {
|
||||
if (p->function_trace) {
|
||||
functionTraceStream = simout.find(csprintf("ftrace.%s", name()));
|
||||
currentFunctionStart = currentFunctionEnd = 0;
|
||||
functionEntryTick = p->functionTraceStart;
|
||||
functionEntryTick = p->function_trace_start;
|
||||
|
||||
if (p->functionTraceStart == 0) {
|
||||
if (p->function_trace_start == 0) {
|
||||
functionTracingEnabled = true;
|
||||
} else {
|
||||
new EventWrapper<BaseCPU, &BaseCPU::enableFunctionTrace>(this,
|
||||
p->functionTraceStart,
|
||||
true);
|
||||
new EventWrapper<BaseCPU,
|
||||
&BaseCPU::enableFunctionTrace>(
|
||||
this, p->function_trace_start, true);
|
||||
}
|
||||
}
|
||||
#if FULL_SYSTEM
|
||||
profileEvent = NULL;
|
||||
if (params->profile)
|
||||
profileEvent = new ProfileEvent(this, params->profile);
|
||||
if (params()->profile)
|
||||
profileEvent = new ProfileEvent(this, params()->profile);
|
||||
#endif
|
||||
tracer = params->tracer;
|
||||
}
|
||||
|
||||
BaseCPU::Params::Params()
|
||||
{
|
||||
#if FULL_SYSTEM
|
||||
profile = false;
|
||||
#endif
|
||||
checker = NULL;
|
||||
tracer = NULL;
|
||||
tracer = params()->tracer;
|
||||
}
|
||||
|
||||
void
|
||||
|
@ -209,7 +200,7 @@ BaseCPU::~BaseCPU()
|
|||
void
|
||||
BaseCPU::init()
|
||||
{
|
||||
if (!params->deferRegistration)
|
||||
if (!params()->defer_registration)
|
||||
registerThreadContexts();
|
||||
}
|
||||
|
||||
|
@ -217,13 +208,13 @@ void
|
|||
BaseCPU::startup()
|
||||
{
|
||||
#if FULL_SYSTEM
|
||||
if (!params->deferRegistration && profileEvent)
|
||||
if (!params()->defer_registration && profileEvent)
|
||||
profileEvent->schedule(curTick);
|
||||
#endif
|
||||
|
||||
if (params->progress_interval) {
|
||||
if (params()->progress_interval) {
|
||||
new CPUProgressEvent(&mainEventQueue,
|
||||
ticks(params->progress_interval),
|
||||
ticks(params()->progress_interval),
|
||||
this);
|
||||
}
|
||||
}
|
||||
|
@ -281,7 +272,7 @@ BaseCPU::registerThreadContexts()
|
|||
ThreadContext *tc = threadContexts[i];
|
||||
|
||||
#if FULL_SYSTEM
|
||||
int id = params->cpu_id;
|
||||
int id = params()->cpu_id;
|
||||
if (id != -1)
|
||||
id += i;
|
||||
|
||||
|
|
|
@ -45,6 +45,7 @@
|
|||
#include "arch/interrupts.hh"
|
||||
#endif
|
||||
|
||||
class BaseCPUParams;
|
||||
class BranchPred;
|
||||
class CheckerCPU;
|
||||
class ThreadContext;
|
||||
|
@ -162,40 +163,9 @@ class BaseCPU : public MemObject
|
|||
ThreadContext *getContext(int tn) { return threadContexts[tn]; }
|
||||
|
||||
public:
|
||||
struct Params
|
||||
{
|
||||
std::string name;
|
||||
int numberOfThreads;
|
||||
bool deferRegistration;
|
||||
Counter max_insts_any_thread;
|
||||
Counter max_insts_all_threads;
|
||||
Counter max_loads_any_thread;
|
||||
Counter max_loads_all_threads;
|
||||
Tick clock;
|
||||
bool functionTrace;
|
||||
Tick functionTraceStart;
|
||||
System *system;
|
||||
int cpu_id;
|
||||
Trace::InstTracer * tracer;
|
||||
|
||||
Tick phase;
|
||||
#if FULL_SYSTEM
|
||||
Tick profile;
|
||||
|
||||
bool do_statistics_insts;
|
||||
bool do_checkpoint_insts;
|
||||
bool do_quiesce;
|
||||
#endif
|
||||
Tick progress_interval;
|
||||
BaseCPU *checker;
|
||||
|
||||
TheISA::CoreSpecific coreParams; //ISA-Specific Params That Set Up State in Core
|
||||
|
||||
Params();
|
||||
};
|
||||
|
||||
const Params *params;
|
||||
|
||||
typedef BaseCPUParams Params;
|
||||
const Params *params() const
|
||||
{ return reinterpret_cast<const Params *>(_params); }
|
||||
BaseCPU(Params *params);
|
||||
virtual ~BaseCPU();
|
||||
|
||||
|
@ -221,6 +191,8 @@ class BaseCPU : public MemObject
|
|||
*/
|
||||
int number_of_threads;
|
||||
|
||||
TheISA::CoreSpecific coreParams; //ISA-Specific Params That Set Up State in Core
|
||||
|
||||
/**
|
||||
* Vector of per-thread instruction-based event queues. Used for
|
||||
* scheduling events based on number of instructions committed by
|
||||
|
|
|
@ -65,6 +65,7 @@ class Process;
|
|||
#endif // FULL_SYSTEM
|
||||
template <class>
|
||||
class BaseDynInst;
|
||||
class CheckerCPUParams;
|
||||
class ThreadContext;
|
||||
class MemInterface;
|
||||
class Checkpoint;
|
||||
|
@ -96,20 +97,10 @@ class CheckerCPU : public BaseCPU
|
|||
public:
|
||||
virtual void init();
|
||||
|
||||
struct Params : public BaseCPU::Params
|
||||
{
|
||||
#if FULL_SYSTEM
|
||||
TheISA::ITB *itb;
|
||||
TheISA::DTB *dtb;
|
||||
#else
|
||||
Process *process;
|
||||
#endif
|
||||
bool exitOnError;
|
||||
bool updateOnError;
|
||||
bool warnOnlyOnLoadError;
|
||||
};
|
||||
|
||||
public:
|
||||
typedef CheckerCPUParams Params;
|
||||
const Params *params() const
|
||||
{ return reinterpret_cast<const Params *>(_params); }
|
||||
CheckerCPU(Params *p);
|
||||
virtual ~CheckerCPU();
|
||||
|
||||
|
|
|
@ -38,10 +38,7 @@ if build_env['USE_CHECKER']:
|
|||
class DerivO3CPU(BaseCPU):
|
||||
type = 'DerivO3CPU'
|
||||
activity = Param.Unsigned(0, "Initial count")
|
||||
numThreads = Param.Unsigned(1, "number of HW thread contexts")
|
||||
|
||||
if build_env['FULL_SYSTEM']:
|
||||
profile = Param.Latency('0ns', "trace the kernel stack")
|
||||
if build_env['USE_CHECKER']:
|
||||
if not build_env['FULL_SYSTEM']:
|
||||
checker = Param.BaseCPU(O3Checker(workload=Parent.workload,
|
||||
|
@ -134,9 +131,6 @@ class DerivO3CPU(BaseCPU):
|
|||
|
||||
instShiftAmt = Param.Unsigned(2, "Number of bits to shift instructions by")
|
||||
|
||||
function_trace = Param.Bool(False, "Enable function trace")
|
||||
function_trace_start = Param.Tick(0, "Cycle to start function trace")
|
||||
|
||||
smtNumFetchingThreads = Param.Unsigned(1, "SMT Number of Fetching Threads")
|
||||
smtFetchPolicy = Param.String('SingleThread', "SMT Fetch policy")
|
||||
smtLSQPolicy = Param.String('Partitioned', "SMT LSQ Sharing Policy")
|
||||
|
|
|
@ -37,6 +37,7 @@
|
|||
#include "cpu/o3/cpu.hh"
|
||||
#include "sim/byteswap.hh"
|
||||
|
||||
class DerivO3CPUParams;
|
||||
class EndQuiesceEvent;
|
||||
namespace Kernel {
|
||||
class Statistics;
|
||||
|
@ -58,10 +59,9 @@ class AlphaO3CPU : public FullO3CPU<Impl>
|
|||
public:
|
||||
typedef O3ThreadState<Impl> ImplState;
|
||||
typedef O3ThreadState<Impl> Thread;
|
||||
typedef typename Impl::Params Params;
|
||||
|
||||
/** Constructs an AlphaO3CPU with the given parameters. */
|
||||
AlphaO3CPU(Params *params);
|
||||
AlphaO3CPU(DerivO3CPUParams *params);
|
||||
|
||||
/** Registers statistics. */
|
||||
void regStats();
|
||||
|
|
|
@ -34,14 +34,13 @@
|
|||
#include "cpu/base.hh"
|
||||
#include "cpu/o3/alpha/cpu.hh"
|
||||
#include "cpu/o3/alpha/impl.hh"
|
||||
#include "cpu/o3/alpha/params.hh"
|
||||
#include "cpu/o3/fu_pool.hh"
|
||||
#include "params/DerivO3CPU.hh"
|
||||
|
||||
class DerivO3CPU : public AlphaO3CPU<AlphaSimpleImpl>
|
||||
{
|
||||
public:
|
||||
DerivO3CPU(AlphaSimpleParams *p)
|
||||
DerivO3CPU(DerivO3CPUParams *p)
|
||||
: AlphaO3CPU<AlphaSimpleImpl>(p)
|
||||
{ }
|
||||
};
|
||||
|
@ -49,8 +48,6 @@ class DerivO3CPU : public AlphaO3CPU<AlphaSimpleImpl>
|
|||
DerivO3CPU *
|
||||
DerivO3CPUParams::create()
|
||||
{
|
||||
DerivO3CPU *cpu;
|
||||
|
||||
#if FULL_SYSTEM
|
||||
// Full-system only supports a single thread for the moment.
|
||||
int actual_num_threads = 1;
|
||||
|
@ -65,135 +62,18 @@ DerivO3CPUParams::create()
|
|||
}
|
||||
#endif
|
||||
|
||||
AlphaSimpleParams *params = new AlphaSimpleParams;
|
||||
|
||||
params->clock = clock;
|
||||
params->phase = phase;
|
||||
|
||||
params->tracer = tracer;
|
||||
|
||||
params->name = name;
|
||||
params->numberOfThreads = actual_num_threads;
|
||||
params->cpu_id = cpu_id;
|
||||
params->activity = activity;
|
||||
|
||||
params->itb = itb;
|
||||
params->dtb = dtb;
|
||||
|
||||
params->system = system;
|
||||
#if FULL_SYSTEM
|
||||
params->profile = profile;
|
||||
|
||||
params->do_quiesce = do_quiesce;
|
||||
params->do_checkpoint_insts = do_checkpoint_insts;
|
||||
params->do_statistics_insts = do_statistics_insts;
|
||||
#else
|
||||
params->workload = workload;
|
||||
#endif // FULL_SYSTEM
|
||||
|
||||
#if USE_CHECKER
|
||||
params->checker = checker;
|
||||
#endif
|
||||
|
||||
params->max_insts_any_thread = max_insts_any_thread;
|
||||
params->max_insts_all_threads = max_insts_all_threads;
|
||||
params->max_loads_any_thread = max_loads_any_thread;
|
||||
params->max_loads_all_threads = max_loads_all_threads;
|
||||
params->progress_interval = progress_interval;
|
||||
|
||||
//
|
||||
// Caches
|
||||
//
|
||||
params->cachePorts = cachePorts;
|
||||
|
||||
params->decodeToFetchDelay = decodeToFetchDelay;
|
||||
params->renameToFetchDelay = renameToFetchDelay;
|
||||
params->iewToFetchDelay = iewToFetchDelay;
|
||||
params->commitToFetchDelay = commitToFetchDelay;
|
||||
params->fetchWidth = fetchWidth;
|
||||
|
||||
params->renameToDecodeDelay = renameToDecodeDelay;
|
||||
params->iewToDecodeDelay = iewToDecodeDelay;
|
||||
params->commitToDecodeDelay = commitToDecodeDelay;
|
||||
params->fetchToDecodeDelay = fetchToDecodeDelay;
|
||||
params->decodeWidth = decodeWidth;
|
||||
|
||||
params->iewToRenameDelay = iewToRenameDelay;
|
||||
params->commitToRenameDelay = commitToRenameDelay;
|
||||
params->decodeToRenameDelay = decodeToRenameDelay;
|
||||
params->renameWidth = renameWidth;
|
||||
|
||||
params->commitToIEWDelay = commitToIEWDelay;
|
||||
params->renameToIEWDelay = renameToIEWDelay;
|
||||
params->issueToExecuteDelay = issueToExecuteDelay;
|
||||
params->dispatchWidth = dispatchWidth;
|
||||
params->issueWidth = issueWidth;
|
||||
params->wbWidth = wbWidth;
|
||||
params->wbDepth = wbDepth;
|
||||
params->fuPool = fuPool;
|
||||
|
||||
params->iewToCommitDelay = iewToCommitDelay;
|
||||
params->renameToROBDelay = renameToROBDelay;
|
||||
params->commitWidth = commitWidth;
|
||||
params->squashWidth = squashWidth;
|
||||
params->trapLatency = trapLatency;
|
||||
|
||||
params->backComSize = backComSize;
|
||||
params->forwardComSize = forwardComSize;
|
||||
|
||||
params->predType = predType;
|
||||
params->localPredictorSize = localPredictorSize;
|
||||
params->localCtrBits = localCtrBits;
|
||||
params->localHistoryTableSize = localHistoryTableSize;
|
||||
params->localHistoryBits = localHistoryBits;
|
||||
params->globalPredictorSize = globalPredictorSize;
|
||||
params->globalCtrBits = globalCtrBits;
|
||||
params->globalHistoryBits = globalHistoryBits;
|
||||
params->choicePredictorSize = choicePredictorSize;
|
||||
params->choiceCtrBits = choiceCtrBits;
|
||||
|
||||
params->BTBEntries = BTBEntries;
|
||||
params->BTBTagSize = BTBTagSize;
|
||||
|
||||
params->RASSize = RASSize;
|
||||
|
||||
params->LQEntries = LQEntries;
|
||||
params->SQEntries = SQEntries;
|
||||
|
||||
params->SSITSize = SSITSize;
|
||||
params->LFSTSize = LFSTSize;
|
||||
|
||||
params->numPhysIntRegs = numPhysIntRegs;
|
||||
params->numPhysFloatRegs = numPhysFloatRegs;
|
||||
params->numIQEntries = numIQEntries;
|
||||
params->numROBEntries = numROBEntries;
|
||||
|
||||
params->smtNumFetchingThreads = smtNumFetchingThreads;
|
||||
numThreads = actual_num_threads;
|
||||
|
||||
// Default smtFetchPolicy to "RoundRobin", if necessary.
|
||||
std::string round_robin_policy = "RoundRobin";
|
||||
std::string single_thread = "SingleThread";
|
||||
|
||||
if (actual_num_threads > 1 && single_thread.compare(smtFetchPolicy) == 0)
|
||||
params->smtFetchPolicy = round_robin_policy;
|
||||
smtFetchPolicy = round_robin_policy;
|
||||
else
|
||||
params->smtFetchPolicy = smtFetchPolicy;
|
||||
smtFetchPolicy = smtFetchPolicy;
|
||||
|
||||
params->smtIQPolicy = smtIQPolicy;
|
||||
params->smtLSQPolicy = smtLSQPolicy;
|
||||
params->smtLSQThreshold = smtLSQThreshold;
|
||||
params->smtROBPolicy = smtROBPolicy;
|
||||
params->smtROBThreshold = smtROBThreshold;
|
||||
params->smtCommitPolicy = smtCommitPolicy;
|
||||
instShiftAmt = 2;
|
||||
|
||||
params->instShiftAmt = 2;
|
||||
|
||||
params->deferRegistration = defer_registration;
|
||||
|
||||
params->functionTrace = function_trace;
|
||||
params->functionTraceStart = function_trace_start;
|
||||
|
||||
cpu = new DerivO3CPU(params);
|
||||
|
||||
return cpu;
|
||||
return new DerivO3CPU(this);
|
||||
}
|
||||
|
|
|
@ -40,7 +40,6 @@
|
|||
#include "sim/stats.hh"
|
||||
|
||||
#include "cpu/o3/alpha/cpu.hh"
|
||||
#include "cpu/o3/alpha/params.hh"
|
||||
#include "cpu/o3/alpha/thread_context.hh"
|
||||
#include "cpu/o3/comm.hh"
|
||||
#include "cpu/o3/thread_state.hh"
|
||||
|
@ -54,8 +53,11 @@
|
|||
#include "sim/system.hh"
|
||||
#endif
|
||||
|
||||
#include "params/DerivO3CPU.hh"
|
||||
|
||||
template <class Impl>
|
||||
AlphaO3CPU<Impl>::AlphaO3CPU(Params *params) : FullO3CPU<Impl>(this, params)
|
||||
AlphaO3CPU<Impl>::AlphaO3CPU(DerivO3CPUParams *params) :
|
||||
FullO3CPU<Impl>(this, params)
|
||||
{
|
||||
DPRINTF(O3CPU, "Creating AlphaO3CPU object.\n");
|
||||
|
||||
|
|
|
@ -33,7 +33,6 @@
|
|||
|
||||
#include "arch/alpha/isa_traits.hh"
|
||||
|
||||
#include "cpu/o3/alpha/params.hh"
|
||||
#include "cpu/o3/cpu_policy.hh"
|
||||
|
||||
|
||||
|
@ -77,9 +76,6 @@ struct AlphaSimpleImpl
|
|||
*/
|
||||
typedef O3CPU CPUType;
|
||||
|
||||
/** The Params to be passed to each stage. */
|
||||
typedef AlphaSimpleParams Params;
|
||||
|
||||
enum {
|
||||
MaxWidth = 8,
|
||||
MaxThreads = 4
|
||||
|
|
|
@ -1,61 +0,0 @@
|
|||
/*
|
||||
* Copyright (c) 2004-2006 The Regents of The University of Michigan
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are
|
||||
* met: redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer;
|
||||
* redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution;
|
||||
* neither the name of the copyright holders nor the names of its
|
||||
* contributors may be used to endorse or promote products derived from
|
||||
* this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
* Authors: Kevin Lim
|
||||
*/
|
||||
|
||||
#ifndef __CPU_O3_ALPHA_PARAMS_HH__
|
||||
#define __CPU_O3_ALPHA_PARAMS_HH__
|
||||
|
||||
#include "cpu/o3/cpu.hh"
|
||||
#include "cpu/o3/params.hh"
|
||||
|
||||
//Forward declarations
|
||||
namespace AlphaISA
|
||||
{
|
||||
class DTB;
|
||||
class ITB;
|
||||
}
|
||||
class MemObject;
|
||||
class Process;
|
||||
class System;
|
||||
|
||||
/**
|
||||
* This file defines the parameters that will be used for the AlphaO3CPU.
|
||||
* This must be defined externally so that the Impl can have a params class
|
||||
* defined that it can pass to all of the individual stages.
|
||||
*/
|
||||
|
||||
class AlphaSimpleParams : public O3Params
|
||||
{
|
||||
public:
|
||||
|
||||
AlphaISA::ITB *itb;
|
||||
AlphaISA::DTB *dtb;
|
||||
};
|
||||
|
||||
#endif // __CPU_O3_ALPHA_PARAMS_HH__
|
|
@ -43,6 +43,8 @@
|
|||
|
||||
#include <list>
|
||||
|
||||
class DerivO3CPUParams;
|
||||
|
||||
/**
|
||||
* Basically a wrapper class to hold both the branch predictor
|
||||
* and the BTB.
|
||||
|
@ -51,7 +53,6 @@ template<class Impl>
|
|||
class BPredUnit
|
||||
{
|
||||
private:
|
||||
typedef typename Impl::Params Params;
|
||||
typedef typename Impl::DynInstPtr DynInstPtr;
|
||||
|
||||
enum PredType {
|
||||
|
@ -66,7 +67,7 @@ class BPredUnit
|
|||
/**
|
||||
* @param params The params object, that has the size of the BP and BTB.
|
||||
*/
|
||||
BPredUnit(Params *params);
|
||||
BPredUnit(DerivO3CPUParams *params);
|
||||
|
||||
/**
|
||||
* Registers statistics.
|
||||
|
|
|
@ -34,8 +34,10 @@
|
|||
#include "base/traceflags.hh"
|
||||
#include "cpu/o3/bpred_unit.hh"
|
||||
|
||||
#include "params/DerivO3CPU.hh"
|
||||
|
||||
template<class Impl>
|
||||
BPredUnit<Impl>::BPredUnit(Params *params)
|
||||
BPredUnit<Impl>::BPredUnit(DerivO3CPUParams *params)
|
||||
: BTB(params->BTBEntries,
|
||||
params->BTBTagSize,
|
||||
params->instShiftAmt)
|
||||
|
|
|
@ -37,6 +37,8 @@
|
|||
#include "cpu/exetrace.hh"
|
||||
#include "cpu/inst_seq.hh"
|
||||
|
||||
class DerivO3CPUParams;
|
||||
|
||||
template <class>
|
||||
class O3ThreadState;
|
||||
|
||||
|
@ -69,7 +71,6 @@ class DefaultCommit
|
|||
// Typedefs from the Impl.
|
||||
typedef typename Impl::O3CPU O3CPU;
|
||||
typedef typename Impl::DynInstPtr DynInstPtr;
|
||||
typedef typename Impl::Params Params;
|
||||
typedef typename Impl::CPUPol CPUPol;
|
||||
|
||||
typedef typename CPUPol::RenameMap RenameMap;
|
||||
|
@ -136,7 +137,7 @@ class DefaultCommit
|
|||
|
||||
public:
|
||||
/** Construct a DefaultCommit with the given parameters. */
|
||||
DefaultCommit(O3CPU *_cpu, Params *params);
|
||||
DefaultCommit(O3CPU *_cpu, DerivO3CPUParams *params);
|
||||
|
||||
/** Returns the name of the DefaultCommit. */
|
||||
std::string name() const;
|
||||
|
|
|
@ -46,6 +46,8 @@
|
|||
#include "cpu/checker/cpu.hh"
|
||||
#endif
|
||||
|
||||
#include "params/DerivO3CPU.hh"
|
||||
|
||||
template <class Impl>
|
||||
DefaultCommit<Impl>::TrapEvent::TrapEvent(DefaultCommit<Impl> *_commit,
|
||||
unsigned _tid)
|
||||
|
@ -71,7 +73,7 @@ DefaultCommit<Impl>::TrapEvent::description() const
|
|||
}
|
||||
|
||||
template <class Impl>
|
||||
DefaultCommit<Impl>::DefaultCommit(O3CPU *_cpu, Params *params)
|
||||
DefaultCommit<Impl>::DefaultCommit(O3CPU *_cpu, DerivO3CPUParams *params)
|
||||
: cpu(_cpu),
|
||||
squashCounter(0),
|
||||
iewToCommitDelay(params->iewToCommitDelay),
|
||||
|
@ -80,7 +82,7 @@ DefaultCommit<Impl>::DefaultCommit(O3CPU *_cpu, Params *params)
|
|||
fetchToCommitDelay(params->commitToFetchDelay),
|
||||
renameWidth(params->renameWidth),
|
||||
commitWidth(params->commitWidth),
|
||||
numThreads(params->numberOfThreads),
|
||||
numThreads(params->numThreads),
|
||||
drainPending(false),
|
||||
switchedOut(false),
|
||||
trapLatency(params->trapLatency)
|
||||
|
|
|
@ -52,9 +52,11 @@
|
|||
#include "cpu/checker/cpu.hh"
|
||||
#endif
|
||||
|
||||
class BaseCPUParams;
|
||||
|
||||
using namespace TheISA;
|
||||
|
||||
BaseO3CPU::BaseO3CPU(Params *params)
|
||||
BaseO3CPU::BaseO3CPU(BaseCPUParams *params)
|
||||
: BaseCPU(params), cpu_id(0)
|
||||
{
|
||||
}
|
||||
|
@ -147,7 +149,7 @@ FullO3CPU<Impl>::DeallocateContextEvent::description() const
|
|||
}
|
||||
|
||||
template <class Impl>
|
||||
FullO3CPU<Impl>::FullO3CPU(O3CPU *o3_cpu, Params *params)
|
||||
FullO3CPU<Impl>::FullO3CPU(O3CPU *o3_cpu, DerivO3CPUParams *params)
|
||||
: BaseO3CPU(params),
|
||||
itb(params->itb),
|
||||
dtb(params->dtb),
|
||||
|
@ -162,16 +164,16 @@ FullO3CPU<Impl>::FullO3CPU(O3CPU *o3_cpu, Params *params)
|
|||
regFile(o3_cpu, params->numPhysIntRegs,
|
||||
params->numPhysFloatRegs),
|
||||
|
||||
freeList(params->numberOfThreads,
|
||||
freeList(params->numThreads,
|
||||
TheISA::NumIntRegs, params->numPhysIntRegs,
|
||||
TheISA::NumFloatRegs, params->numPhysFloatRegs),
|
||||
|
||||
rob(o3_cpu,
|
||||
params->numROBEntries, params->squashWidth,
|
||||
params->smtROBPolicy, params->smtROBThreshold,
|
||||
params->numberOfThreads),
|
||||
params->numThreads),
|
||||
|
||||
scoreboard(params->numberOfThreads,
|
||||
scoreboard(params->numThreads,
|
||||
TheISA::NumIntRegs, params->numPhysIntRegs,
|
||||
TheISA::NumFloatRegs, params->numPhysFloatRegs,
|
||||
TheISA::NumMiscRegs * number_of_threads,
|
||||
|
@ -192,7 +194,7 @@ FullO3CPU<Impl>::FullO3CPU(O3CPU *o3_cpu, Params *params)
|
|||
physmem(system->physmem),
|
||||
#endif // FULL_SYSTEM
|
||||
drainCount(0),
|
||||
deferRegistration(params->deferRegistration),
|
||||
deferRegistration(params->defer_registration),
|
||||
numThreads(number_of_threads)
|
||||
{
|
||||
if (!deferRegistration) {
|
||||
|
|
|
@ -53,6 +53,8 @@
|
|||
//#include "cpu/o3/thread_context.hh"
|
||||
#include "sim/process.hh"
|
||||
|
||||
#include "params/DerivO3CPU.hh"
|
||||
|
||||
template <class>
|
||||
class Checker;
|
||||
class ThreadContext;
|
||||
|
@ -63,13 +65,13 @@ class Checkpoint;
|
|||
class MemObject;
|
||||
class Process;
|
||||
|
||||
class BaseCPUParams;
|
||||
|
||||
class BaseO3CPU : public BaseCPU
|
||||
{
|
||||
//Stuff that's pretty ISA independent will go here.
|
||||
public:
|
||||
typedef BaseCPU::Params Params;
|
||||
|
||||
BaseO3CPU(Params *params);
|
||||
BaseO3CPU(BaseCPUParams *params);
|
||||
|
||||
void regStats();
|
||||
|
||||
|
@ -96,7 +98,6 @@ class FullO3CPU : public BaseO3CPU
|
|||
typedef typename Impl::CPUPol CPUPolicy;
|
||||
typedef typename Impl::DynInstPtr DynInstPtr;
|
||||
typedef typename Impl::O3CPU O3CPU;
|
||||
typedef typename Impl::Params Params;
|
||||
|
||||
typedef O3ThreadState<Impl> Thread;
|
||||
|
||||
|
@ -256,7 +257,7 @@ class FullO3CPU : public BaseO3CPU
|
|||
|
||||
public:
|
||||
/** Constructs a CPU with the given parameters. */
|
||||
FullO3CPU(O3CPU *o3_cpu, Params *params);
|
||||
FullO3CPU(O3CPU *o3_cpu, DerivO3CPUParams *params);
|
||||
/** Destructor. */
|
||||
~FullO3CPU();
|
||||
|
||||
|
|
|
@ -36,6 +36,8 @@
|
|||
#include "base/statistics.hh"
|
||||
#include "base/timebuf.hh"
|
||||
|
||||
class DerivO3CPUParams;
|
||||
|
||||
/**
|
||||
* DefaultDecode class handles both single threaded and SMT
|
||||
* decode. Its width is specified by the parameters; each cycles it
|
||||
|
@ -50,7 +52,6 @@ class DefaultDecode
|
|||
// Typedefs from the Impl.
|
||||
typedef typename Impl::O3CPU O3CPU;
|
||||
typedef typename Impl::DynInstPtr DynInstPtr;
|
||||
typedef typename Impl::Params Params;
|
||||
typedef typename Impl::CPUPol CPUPol;
|
||||
|
||||
// Typedefs from the CPU policy.
|
||||
|
@ -86,7 +87,7 @@ class DefaultDecode
|
|||
|
||||
public:
|
||||
/** DefaultDecode constructor. */
|
||||
DefaultDecode(O3CPU *_cpu, Params *params);
|
||||
DefaultDecode(O3CPU *_cpu, DerivO3CPUParams *params);
|
||||
|
||||
/** Returns the name of decode. */
|
||||
std::string name() const;
|
||||
|
|
|
@ -30,15 +30,17 @@
|
|||
|
||||
#include "cpu/o3/decode.hh"
|
||||
|
||||
#include "params/DerivO3CPU.hh"
|
||||
|
||||
template<class Impl>
|
||||
DefaultDecode<Impl>::DefaultDecode(O3CPU *_cpu, Params *params)
|
||||
DefaultDecode<Impl>::DefaultDecode(O3CPU *_cpu, DerivO3CPUParams *params)
|
||||
: cpu(_cpu),
|
||||
renameToDecodeDelay(params->renameToDecodeDelay),
|
||||
iewToDecodeDelay(params->iewToDecodeDelay),
|
||||
commitToDecodeDelay(params->commitToDecodeDelay),
|
||||
fetchToDecodeDelay(params->fetchToDecodeDelay),
|
||||
decodeWidth(params->decodeWidth),
|
||||
numThreads(params->numberOfThreads)
|
||||
numThreads(params->numThreads)
|
||||
{
|
||||
_status = Inactive;
|
||||
|
||||
|
|
|
@ -41,6 +41,8 @@
|
|||
#include "mem/port.hh"
|
||||
#include "sim/eventq.hh"
|
||||
|
||||
class DerivO3CPUParams;
|
||||
|
||||
/**
|
||||
* DefaultFetch class handles both single threaded and SMT fetch. Its
|
||||
* width is specified by the parameters; each cycle it tries to fetch
|
||||
|
@ -58,7 +60,6 @@ class DefaultFetch
|
|||
typedef typename Impl::DynInst DynInst;
|
||||
typedef typename Impl::DynInstPtr DynInstPtr;
|
||||
typedef typename Impl::O3CPU O3CPU;
|
||||
typedef typename Impl::Params Params;
|
||||
|
||||
/** Typedefs from the CPU policy. */
|
||||
typedef typename CPUPol::BPredUnit BPredUnit;
|
||||
|
@ -160,7 +161,7 @@ class DefaultFetch
|
|||
|
||||
public:
|
||||
/** DefaultFetch constructor. */
|
||||
DefaultFetch(O3CPU *_cpu, Params *params);
|
||||
DefaultFetch(O3CPU *_cpu, DerivO3CPUParams *params);
|
||||
|
||||
/** Returns the name of fetch. */
|
||||
std::string name() const;
|
||||
|
|
|
@ -51,6 +51,8 @@
|
|||
#include "sim/system.hh"
|
||||
#endif // FULL_SYSTEM
|
||||
|
||||
#include "params/DerivO3CPU.hh"
|
||||
|
||||
template<class Impl>
|
||||
void
|
||||
DefaultFetch<Impl>::IcachePort::setPeer(Port *port)
|
||||
|
@ -111,7 +113,7 @@ DefaultFetch<Impl>::IcachePort::recvRetry()
|
|||
}
|
||||
|
||||
template<class Impl>
|
||||
DefaultFetch<Impl>::DefaultFetch(O3CPU *_cpu, Params *params)
|
||||
DefaultFetch<Impl>::DefaultFetch(O3CPU *_cpu, DerivO3CPUParams *params)
|
||||
: cpu(_cpu),
|
||||
branchPred(params),
|
||||
predecoder(NULL),
|
||||
|
@ -123,7 +125,7 @@ DefaultFetch<Impl>::DefaultFetch(O3CPU *_cpu, Params *params)
|
|||
cacheBlocked(false),
|
||||
retryPkt(NULL),
|
||||
retryTid(-1),
|
||||
numThreads(params->numberOfThreads),
|
||||
numThreads(params->numThreads),
|
||||
numFetchingThreads(params->smtNumFetchingThreads),
|
||||
interruptPending(false),
|
||||
drainPending(false),
|
||||
|
|
|
@ -41,6 +41,7 @@
|
|||
#include "cpu/o3/scoreboard.hh"
|
||||
#include "cpu/o3/lsq.hh"
|
||||
|
||||
class DerivO3CPUParams;
|
||||
class FUPool;
|
||||
|
||||
/**
|
||||
|
@ -70,7 +71,6 @@ class DefaultIEW
|
|||
typedef typename Impl::CPUPol CPUPol;
|
||||
typedef typename Impl::DynInstPtr DynInstPtr;
|
||||
typedef typename Impl::O3CPU O3CPU;
|
||||
typedef typename Impl::Params Params;
|
||||
|
||||
typedef typename CPUPol::IQ IQ;
|
||||
typedef typename CPUPol::RenameMap RenameMap;
|
||||
|
@ -115,7 +115,7 @@ class DefaultIEW
|
|||
|
||||
public:
|
||||
/** Constructs a DefaultIEW with the given parameters. */
|
||||
DefaultIEW(O3CPU *_cpu, Params *params);
|
||||
DefaultIEW(O3CPU *_cpu, DerivO3CPUParams *params);
|
||||
|
||||
/** Returns the name of the DefaultIEW stage. */
|
||||
std::string name() const;
|
||||
|
|
|
@ -37,9 +37,10 @@
|
|||
#include "base/timebuf.hh"
|
||||
#include "cpu/o3/fu_pool.hh"
|
||||
#include "cpu/o3/iew.hh"
|
||||
#include "params/DerivO3CPU.hh"
|
||||
|
||||
template<class Impl>
|
||||
DefaultIEW<Impl>::DefaultIEW(O3CPU *_cpu, Params *params)
|
||||
DefaultIEW<Impl>::DefaultIEW(O3CPU *_cpu, DerivO3CPUParams *params)
|
||||
: issueToExecQueue(params->backComSize, params->forwardComSize),
|
||||
cpu(_cpu),
|
||||
instQueue(_cpu, this, params),
|
||||
|
@ -52,7 +53,7 @@ DefaultIEW<Impl>::DefaultIEW(O3CPU *_cpu, Params *params)
|
|||
issueWidth(params->issueWidth),
|
||||
wbOutstanding(0),
|
||||
wbWidth(params->wbWidth),
|
||||
numThreads(params->numberOfThreads),
|
||||
numThreads(params->numThreads),
|
||||
switchedOut(false)
|
||||
{
|
||||
_status = Active;
|
||||
|
|
|
@ -41,8 +41,10 @@
|
|||
#include "cpu/inst_seq.hh"
|
||||
#include "cpu/o3/dep_graph.hh"
|
||||
#include "cpu/op_class.hh"
|
||||
#include "sim/eventq.hh"
|
||||
#include "sim/host.hh"
|
||||
|
||||
class DerivO3CPUParams;
|
||||
class FUPool;
|
||||
class MemInterface;
|
||||
|
||||
|
@ -70,7 +72,6 @@ class InstructionQueue
|
|||
//Typedefs from the Impl.
|
||||
typedef typename Impl::O3CPU O3CPU;
|
||||
typedef typename Impl::DynInstPtr DynInstPtr;
|
||||
typedef typename Impl::Params Params;
|
||||
|
||||
typedef typename Impl::CPUPol::IEW IEW;
|
||||
typedef typename Impl::CPUPol::MemDepUnit MemDepUnit;
|
||||
|
@ -110,7 +111,7 @@ class InstructionQueue
|
|||
};
|
||||
|
||||
/** Constructs an IQ. */
|
||||
InstructionQueue(O3CPU *cpu_ptr, IEW *iew_ptr, Params *params);
|
||||
InstructionQueue(O3CPU *cpu_ptr, IEW *iew_ptr, DerivO3CPUParams *params);
|
||||
|
||||
/** Destructs the IQ. */
|
||||
~InstructionQueue();
|
||||
|
|
|
@ -37,6 +37,8 @@
|
|||
#include "enums/OpClass.hh"
|
||||
#include "sim/core.hh"
|
||||
|
||||
#include "params/DerivO3CPU.hh"
|
||||
|
||||
template <class Impl>
|
||||
InstructionQueue<Impl>::FUCompletion::FUCompletion(DynInstPtr &_inst,
|
||||
int fu_idx,
|
||||
|
@ -65,7 +67,7 @@ InstructionQueue<Impl>::FUCompletion::description() const
|
|||
|
||||
template <class Impl>
|
||||
InstructionQueue<Impl>::InstructionQueue(O3CPU *cpu_ptr, IEW *iew_ptr,
|
||||
Params *params)
|
||||
DerivO3CPUParams *params)
|
||||
: cpu(cpu_ptr),
|
||||
iewStage(iew_ptr),
|
||||
fuPool(params->fuPool),
|
||||
|
@ -79,7 +81,7 @@ InstructionQueue<Impl>::InstructionQueue(O3CPU *cpu_ptr, IEW *iew_ptr,
|
|||
|
||||
switchedOut = false;
|
||||
|
||||
numThreads = params->numberOfThreads;
|
||||
numThreads = params->numThreads;
|
||||
|
||||
// Set the number of physical registers as the number of int + float
|
||||
numPhysRegs = numPhysIntRegs + numPhysFloatRegs;
|
||||
|
|
|
@ -33,17 +33,14 @@
|
|||
#if THE_ISA == ALPHA_ISA
|
||||
#include "cpu/o3/alpha/cpu.hh"
|
||||
#include "cpu/o3/alpha/impl.hh"
|
||||
#include "cpu/o3/alpha/params.hh"
|
||||
#include "cpu/o3/alpha/dyn_inst.hh"
|
||||
#elif THE_ISA == MIPS_ISA
|
||||
#include "cpu/o3/mips/cpu.hh"
|
||||
#include "cpu/o3/mips/impl.hh"
|
||||
#include "cpu/o3/mips/params.hh"
|
||||
#include "cpu/o3/mips/dyn_inst.hh"
|
||||
#elif THE_ISA == SPARC_ISA
|
||||
#include "cpu/o3/sparc/cpu.hh"
|
||||
#include "cpu/o3/sparc/impl.hh"
|
||||
#include "cpu/o3/sparc/params.hh"
|
||||
#include "cpu/o3/sparc/dyn_inst.hh"
|
||||
#else
|
||||
#error "ISA-specific header files O3CPU not defined ISA"
|
||||
|
|
|
@ -40,10 +40,11 @@
|
|||
#include "mem/port.hh"
|
||||
#include "sim/sim_object.hh"
|
||||
|
||||
class DerivO3CPUParams;
|
||||
|
||||
template <class Impl>
|
||||
class LSQ {
|
||||
public:
|
||||
typedef typename Impl::Params Params;
|
||||
typedef typename Impl::O3CPU O3CPU;
|
||||
typedef typename Impl::DynInstPtr DynInstPtr;
|
||||
typedef typename Impl::CPUPol::IEW IEW;
|
||||
|
@ -57,7 +58,7 @@ class LSQ {
|
|||
};
|
||||
|
||||
/** Constructs an LSQ with the given parameters. */
|
||||
LSQ(O3CPU *cpu_ptr, IEW *iew_ptr, Params *params);
|
||||
LSQ(O3CPU *cpu_ptr, IEW *iew_ptr, DerivO3CPUParams *params);
|
||||
|
||||
/** Returns the name of the LSQ. */
|
||||
std::string name() const;
|
||||
|
|
|
@ -34,6 +34,8 @@
|
|||
|
||||
#include "cpu/o3/lsq.hh"
|
||||
|
||||
#include "params/DerivO3CPU.hh"
|
||||
|
||||
template<class Impl>
|
||||
void
|
||||
LSQ<Impl>::DcachePort::setPeer(Port *port)
|
||||
|
@ -111,11 +113,11 @@ LSQ<Impl>::DcachePort::recvRetry()
|
|||
}
|
||||
|
||||
template <class Impl>
|
||||
LSQ<Impl>::LSQ(O3CPU *cpu_ptr, IEW *iew_ptr, Params *params)
|
||||
LSQ<Impl>::LSQ(O3CPU *cpu_ptr, IEW *iew_ptr, DerivO3CPUParams *params)
|
||||
: cpu(cpu_ptr), iewStage(iew_ptr), dcachePort(this),
|
||||
LQEntries(params->LQEntries),
|
||||
SQEntries(params->SQEntries),
|
||||
numThreads(params->numberOfThreads),
|
||||
numThreads(params->numThreads),
|
||||
retryTid(-1)
|
||||
{
|
||||
dcachePort.snoopRangeSent = false;
|
||||
|
|
|
@ -46,6 +46,8 @@
|
|||
#include "mem/packet.hh"
|
||||
#include "mem/port.hh"
|
||||
|
||||
class DerivO3CPUParams;
|
||||
|
||||
/**
|
||||
* Class that implements the actual LQ and SQ for each specific
|
||||
* thread. Both are circular queues; load entries are freed upon
|
||||
|
@ -63,7 +65,6 @@ class LSQUnit {
|
|||
protected:
|
||||
typedef TheISA::IntReg IntReg;
|
||||
public:
|
||||
typedef typename Impl::Params Params;
|
||||
typedef typename Impl::O3CPU O3CPU;
|
||||
typedef typename Impl::DynInstPtr DynInstPtr;
|
||||
typedef typename Impl::CPUPol::IEW IEW;
|
||||
|
@ -75,8 +76,9 @@ class LSQUnit {
|
|||
LSQUnit();
|
||||
|
||||
/** Initializes the LSQ unit with the specified number of entries. */
|
||||
void init(O3CPU *cpu_ptr, IEW *iew_ptr, Params *params, LSQ *lsq_ptr,
|
||||
unsigned maxLQEntries, unsigned maxSQEntries, unsigned id);
|
||||
void init(O3CPU *cpu_ptr, IEW *iew_ptr, DerivO3CPUParams *params,
|
||||
LSQ *lsq_ptr, unsigned maxLQEntries, unsigned maxSQEntries,
|
||||
unsigned id);
|
||||
|
||||
/** Returns the name of the LSQ unit. */
|
||||
std::string name() const;
|
||||
|
|
|
@ -112,8 +112,9 @@ LSQUnit<Impl>::LSQUnit()
|
|||
|
||||
template<class Impl>
|
||||
void
|
||||
LSQUnit<Impl>::init(O3CPU *cpu_ptr, IEW *iew_ptr, Params *params, LSQ *lsq_ptr,
|
||||
unsigned maxLQEntries, unsigned maxSQEntries, unsigned id)
|
||||
LSQUnit<Impl>::init(O3CPU *cpu_ptr, IEW *iew_ptr, DerivO3CPUParams *params,
|
||||
LSQ *lsq_ptr, unsigned maxLQEntries, unsigned maxSQEntries,
|
||||
unsigned id)
|
||||
{
|
||||
cpu = cpu_ptr;
|
||||
iewStage = iew_ptr;
|
||||
|
|
|
@ -48,6 +48,8 @@ struct SNHash {
|
|||
}
|
||||
};
|
||||
|
||||
class DerivO3CPUParams;
|
||||
|
||||
template <class Impl>
|
||||
class InstructionQueue;
|
||||
|
||||
|
@ -65,14 +67,13 @@ class InstructionQueue;
|
|||
template <class MemDepPred, class Impl>
|
||||
class MemDepUnit {
|
||||
public:
|
||||
typedef typename Impl::Params Params;
|
||||
typedef typename Impl::DynInstPtr DynInstPtr;
|
||||
|
||||
/** Empty constructor. Must call init() prior to using in this case. */
|
||||
MemDepUnit();
|
||||
|
||||
/** Constructs a MemDepUnit with given parameters. */
|
||||
MemDepUnit(Params *params);
|
||||
MemDepUnit(DerivO3CPUParams *params);
|
||||
|
||||
/** Frees up any memory allocated. */
|
||||
~MemDepUnit();
|
||||
|
@ -81,7 +82,7 @@ class MemDepUnit {
|
|||
std::string name() const;
|
||||
|
||||
/** Initializes the unit with parameters and a thread id. */
|
||||
void init(Params *params, int tid);
|
||||
void init(DerivO3CPUParams *params, int tid);
|
||||
|
||||
/** Registers statistics. */
|
||||
void regStats();
|
||||
|
|
|
@ -33,6 +33,8 @@
|
|||
#include "cpu/o3/inst_queue.hh"
|
||||
#include "cpu/o3/mem_dep_unit.hh"
|
||||
|
||||
#include "params/DerivO3CPU.hh"
|
||||
|
||||
template <class MemDepPred, class Impl>
|
||||
MemDepUnit<MemDepPred, Impl>::MemDepUnit()
|
||||
: loadBarrier(false), loadBarrierSN(0), storeBarrier(false),
|
||||
|
@ -41,7 +43,7 @@ MemDepUnit<MemDepPred, Impl>::MemDepUnit()
|
|||
}
|
||||
|
||||
template <class MemDepPred, class Impl>
|
||||
MemDepUnit<MemDepPred, Impl>::MemDepUnit(Params *params)
|
||||
MemDepUnit<MemDepPred, Impl>::MemDepUnit(DerivO3CPUParams *params)
|
||||
: depPred(params->SSITSize, params->LFSTSize), loadBarrier(false),
|
||||
loadBarrierSN(0), storeBarrier(false), storeBarrierSN(0), iqPtr(NULL)
|
||||
{
|
||||
|
@ -82,7 +84,7 @@ MemDepUnit<MemDepPred, Impl>::name() const
|
|||
|
||||
template <class MemDepPred, class Impl>
|
||||
void
|
||||
MemDepUnit<MemDepPred, Impl>::init(Params *params, int tid)
|
||||
MemDepUnit<MemDepPred, Impl>::init(DerivO3CPUParams *params, int tid)
|
||||
{
|
||||
DPRINTF(MemDepUnit, "Creating MemDepUnit %i object.\n",tid);
|
||||
|
||||
|
|
|
@ -39,6 +39,7 @@
|
|||
#include "sim/byteswap.hh"
|
||||
#include "sim/faults.hh"
|
||||
|
||||
class DerivO3CPUParams;
|
||||
class EndQuiesceEvent;
|
||||
namespace Kernel {
|
||||
class Statistics;
|
||||
|
@ -60,10 +61,9 @@ class MipsO3CPU : public FullO3CPU<Impl>
|
|||
public:
|
||||
typedef O3ThreadState<Impl> ImplState;
|
||||
typedef O3ThreadState<Impl> Thread;
|
||||
typedef typename Impl::Params Params;
|
||||
|
||||
/** Constructs an MipsO3CPU with the given parameters. */
|
||||
MipsO3CPU(Params *params);
|
||||
MipsO3CPU(DerivO3CPUParams *params);
|
||||
|
||||
/** Registers statistics. */
|
||||
void regStats();
|
||||
|
|
|
@ -35,14 +35,13 @@
|
|||
#include "cpu/base.hh"
|
||||
#include "cpu/o3/mips/cpu.hh"
|
||||
#include "cpu/o3/mips/impl.hh"
|
||||
#include "cpu/o3/mips/params.hh"
|
||||
#include "cpu/o3/fu_pool.hh"
|
||||
#include "params/DerivO3CPU.hh"
|
||||
|
||||
class DerivO3CPU : public MipsO3CPU<MipsSimpleImpl>
|
||||
{
|
||||
public:
|
||||
DerivO3CPU(MipsSimpleParams *p)
|
||||
DerivO3CPU(DerivO3CPUParams *p)
|
||||
: MipsO3CPU<MipsSimpleImpl>(p)
|
||||
{ }
|
||||
};
|
||||
|
@ -50,8 +49,10 @@ class DerivO3CPU : public MipsO3CPU<MipsSimpleImpl>
|
|||
DerivO3CPU *
|
||||
DerivO3CPUParams::create()
|
||||
{
|
||||
DerivO3CPU *cpu;
|
||||
|
||||
#if FULL_SYSTEM
|
||||
// Full-system only supports a single thread for the moment.
|
||||
int actual_num_threads = 1;
|
||||
#else
|
||||
// In non-full-system mode, we infer the number of threads from
|
||||
// the workload if it's not explicitly specified.
|
||||
int actual_num_threads =
|
||||
|
@ -60,123 +61,20 @@ DerivO3CPUParams::create()
|
|||
if (workload.size() == 0) {
|
||||
fatal("Must specify at least one workload!");
|
||||
}
|
||||
|
||||
MipsSimpleParams *params = new MipsSimpleParams;
|
||||
|
||||
params->clock = clock;
|
||||
params->phase = phase;
|
||||
|
||||
params->tracer = tracer;
|
||||
|
||||
params->name = name;
|
||||
params->numberOfThreads = actual_num_threads;
|
||||
params->cpu_id = cpu_id;
|
||||
params->activity = activity;
|
||||
|
||||
params->workload = workload;
|
||||
|
||||
#if USE_CHECKER
|
||||
params->checker = checker;
|
||||
#endif
|
||||
|
||||
params->max_insts_any_thread = max_insts_any_thread;
|
||||
params->max_insts_all_threads = max_insts_all_threads;
|
||||
params->max_loads_any_thread = max_loads_any_thread;
|
||||
params->max_loads_all_threads = max_loads_all_threads;
|
||||
|
||||
//
|
||||
// Caches
|
||||
//
|
||||
params->cachePorts = cachePorts;
|
||||
|
||||
params->decodeToFetchDelay = decodeToFetchDelay;
|
||||
params->renameToFetchDelay = renameToFetchDelay;
|
||||
params->iewToFetchDelay = iewToFetchDelay;
|
||||
params->commitToFetchDelay = commitToFetchDelay;
|
||||
params->fetchWidth = fetchWidth;
|
||||
|
||||
params->renameToDecodeDelay = renameToDecodeDelay;
|
||||
params->iewToDecodeDelay = iewToDecodeDelay;
|
||||
params->commitToDecodeDelay = commitToDecodeDelay;
|
||||
params->fetchToDecodeDelay = fetchToDecodeDelay;
|
||||
params->decodeWidth = decodeWidth;
|
||||
|
||||
params->iewToRenameDelay = iewToRenameDelay;
|
||||
params->commitToRenameDelay = commitToRenameDelay;
|
||||
params->decodeToRenameDelay = decodeToRenameDelay;
|
||||
params->renameWidth = renameWidth;
|
||||
|
||||
params->commitToIEWDelay = commitToIEWDelay;
|
||||
params->renameToIEWDelay = renameToIEWDelay;
|
||||
params->issueToExecuteDelay = issueToExecuteDelay;
|
||||
params->dispatchWidth = dispatchWidth;
|
||||
params->issueWidth = issueWidth;
|
||||
params->wbWidth = wbWidth;
|
||||
params->wbDepth = wbDepth;
|
||||
params->fuPool = fuPool;
|
||||
|
||||
params->iewToCommitDelay = iewToCommitDelay;
|
||||
params->renameToROBDelay = renameToROBDelay;
|
||||
params->commitWidth = commitWidth;
|
||||
params->squashWidth = squashWidth;
|
||||
params->trapLatency = trapLatency;
|
||||
|
||||
params->backComSize = backComSize;
|
||||
params->forwardComSize = forwardComSize;
|
||||
|
||||
params->predType = predType;
|
||||
params->localPredictorSize = localPredictorSize;
|
||||
params->localCtrBits = localCtrBits;
|
||||
params->localHistoryTableSize = localHistoryTableSize;
|
||||
params->localHistoryBits = localHistoryBits;
|
||||
params->globalPredictorSize = globalPredictorSize;
|
||||
params->globalCtrBits = globalCtrBits;
|
||||
params->globalHistoryBits = globalHistoryBits;
|
||||
params->choicePredictorSize = choicePredictorSize;
|
||||
params->choiceCtrBits = choiceCtrBits;
|
||||
|
||||
params->BTBEntries = BTBEntries;
|
||||
params->BTBTagSize = BTBTagSize;
|
||||
|
||||
params->RASSize = RASSize;
|
||||
|
||||
params->LQEntries = LQEntries;
|
||||
params->SQEntries = SQEntries;
|
||||
|
||||
params->SSITSize = SSITSize;
|
||||
params->LFSTSize = LFSTSize;
|
||||
|
||||
params->numPhysIntRegs = numPhysIntRegs;
|
||||
params->numPhysFloatRegs = numPhysFloatRegs;
|
||||
params->numIQEntries = numIQEntries;
|
||||
params->numROBEntries = numROBEntries;
|
||||
|
||||
params->smtNumFetchingThreads = smtNumFetchingThreads;
|
||||
numThreads = actual_num_threads;
|
||||
|
||||
// Default smtFetchPolicy to "RoundRobin", if necessary.
|
||||
std::string round_robin_policy = "RoundRobin";
|
||||
std::string single_thread = "SingleThread";
|
||||
|
||||
if (actual_num_threads > 1 && single_thread.compare(smtFetchPolicy) == 0)
|
||||
params->smtFetchPolicy = round_robin_policy;
|
||||
smtFetchPolicy = round_robin_policy;
|
||||
else
|
||||
params->smtFetchPolicy = smtFetchPolicy;
|
||||
smtFetchPolicy = smtFetchPolicy;
|
||||
|
||||
params->smtIQPolicy = smtIQPolicy;
|
||||
params->smtLSQPolicy = smtLSQPolicy;
|
||||
params->smtLSQThreshold = smtLSQThreshold;
|
||||
params->smtROBPolicy = smtROBPolicy;
|
||||
params->smtROBThreshold = smtROBThreshold;
|
||||
params->smtCommitPolicy = smtCommitPolicy;
|
||||
instShiftAmt = 2;
|
||||
|
||||
params->instShiftAmt = 2;
|
||||
|
||||
params->deferRegistration = defer_registration;
|
||||
|
||||
params->functionTrace = function_trace;
|
||||
params->functionTraceStart = function_trace_start;
|
||||
|
||||
cpu = new DerivO3CPU(params);
|
||||
|
||||
return cpu;
|
||||
return new DerivO3CPU(this);
|
||||
}
|
||||
|
|
|
@ -40,13 +40,14 @@
|
|||
#include "sim/stats.hh"
|
||||
|
||||
#include "cpu/o3/mips/cpu.hh"
|
||||
#include "cpu/o3/mips/params.hh"
|
||||
#include "cpu/o3/mips/thread_context.hh"
|
||||
#include "cpu/o3/comm.hh"
|
||||
#include "cpu/o3/thread_state.hh"
|
||||
|
||||
#include "params/DerivO3CPU.hh"
|
||||
|
||||
template <class Impl>
|
||||
MipsO3CPU<Impl>::MipsO3CPU(Params *params)
|
||||
MipsO3CPU<Impl>::MipsO3CPU(DerivO3CPUParams *params)
|
||||
: FullO3CPU<Impl>(this, params)
|
||||
{
|
||||
DPRINTF(O3CPU, "Creating MipsO3CPU object.\n");
|
||||
|
|
|
@ -34,7 +34,6 @@
|
|||
|
||||
#include "arch/mips/isa_traits.hh"
|
||||
|
||||
#include "cpu/o3/mips/params.hh"
|
||||
#include "cpu/o3/cpu_policy.hh"
|
||||
|
||||
|
||||
|
@ -78,9 +77,6 @@ struct MipsSimpleImpl
|
|||
*/
|
||||
typedef O3CPU CPUType;
|
||||
|
||||
/** The Params to be passed to each stage. */
|
||||
typedef MipsSimpleParams Params;
|
||||
|
||||
enum {
|
||||
MaxWidth = 8,
|
||||
MaxThreads = 4
|
||||
|
|
|
@ -1,64 +0,0 @@
|
|||
/*
|
||||
* Copyright (c) 2006 The Regents of The University of Michigan
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are
|
||||
* met: redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer;
|
||||
* redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution;
|
||||
* neither the name of the copyright holders nor the names of its
|
||||
* contributors may be used to endorse or promote products derived from
|
||||
* this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
* Authors: Kevin Lim
|
||||
* Korey Sewell
|
||||
*/
|
||||
|
||||
#ifndef __CPU_O3_MIPS_PARAMS_HH__
|
||||
#define __CPU_O3_MIPS_PARAMS_HH__
|
||||
|
||||
#include "cpu/o3/cpu.hh"
|
||||
#include "cpu/o3/params.hh"
|
||||
|
||||
//Forward declarations
|
||||
namespace MipsISA
|
||||
{
|
||||
class MipsDTB;
|
||||
class MipsITB;
|
||||
}
|
||||
class MemObject;
|
||||
class Process;
|
||||
class System;
|
||||
|
||||
/**
|
||||
* This file defines the parameters that will be used for the MipsO3CPU.
|
||||
* This must be defined externally so that the Impl can have a params class
|
||||
* defined that it can pass to all of the individual stages.
|
||||
*/
|
||||
|
||||
class MipsSimpleParams : public O3Params
|
||||
{
|
||||
public:
|
||||
MipsSimpleParams() {}
|
||||
|
||||
//Full System Paramater Objects place here
|
||||
MipsISA::ITB *itb;
|
||||
MipsISA::DTB *dtb;
|
||||
};
|
||||
|
||||
#endif // __CPU_O3_MIPS_PARAMS_HH__
|
|
@ -1,180 +0,0 @@
|
|||
/*
|
||||
* Copyright (c) 2004-2006 The Regents of The University of Michigan
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are
|
||||
* met: redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer;
|
||||
* redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution;
|
||||
* neither the name of the copyright holders nor the names of its
|
||||
* contributors may be used to endorse or promote products derived from
|
||||
* this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
* Authors: Kevin Lim
|
||||
*/
|
||||
|
||||
#ifndef __CPU_O3_PARAMS_HH__
|
||||
#define __CPU_O3_PARAMS_HH__
|
||||
|
||||
#include "cpu/o3/cpu.hh"
|
||||
|
||||
//Forward declarations
|
||||
class FUPool;
|
||||
|
||||
/**
|
||||
* This file defines the parameters that will be used for the O3CPU.
|
||||
* This must be defined externally so that the Impl can have a params class
|
||||
* defined that it can pass to all of the individual stages.
|
||||
*/
|
||||
class O3Params : public BaseO3CPU::Params
|
||||
{
|
||||
public:
|
||||
unsigned activity;
|
||||
|
||||
//
|
||||
// Pointers to key objects
|
||||
//
|
||||
#if !FULL_SYSTEM
|
||||
std::vector<Process *> workload;
|
||||
Process *process;
|
||||
#endif // FULL_SYSTEM
|
||||
|
||||
BaseCPU *checker;
|
||||
|
||||
//
|
||||
// Caches
|
||||
//
|
||||
// MemInterface *icacheInterface;
|
||||
// MemInterface *dcacheInterface;
|
||||
|
||||
unsigned cachePorts;
|
||||
|
||||
//
|
||||
// Fetch
|
||||
//
|
||||
unsigned decodeToFetchDelay;
|
||||
unsigned renameToFetchDelay;
|
||||
unsigned iewToFetchDelay;
|
||||
unsigned commitToFetchDelay;
|
||||
unsigned fetchWidth;
|
||||
|
||||
//
|
||||
// Decode
|
||||
//
|
||||
unsigned renameToDecodeDelay;
|
||||
unsigned iewToDecodeDelay;
|
||||
unsigned commitToDecodeDelay;
|
||||
unsigned fetchToDecodeDelay;
|
||||
unsigned decodeWidth;
|
||||
|
||||
//
|
||||
// Rename
|
||||
//
|
||||
unsigned iewToRenameDelay;
|
||||
unsigned commitToRenameDelay;
|
||||
unsigned decodeToRenameDelay;
|
||||
unsigned renameWidth;
|
||||
|
||||
//
|
||||
// IEW
|
||||
//
|
||||
unsigned commitToIEWDelay;
|
||||
unsigned renameToIEWDelay;
|
||||
unsigned issueToExecuteDelay;
|
||||
unsigned dispatchWidth;
|
||||
unsigned issueWidth;
|
||||
unsigned wbWidth;
|
||||
unsigned wbDepth;
|
||||
FUPool *fuPool;
|
||||
|
||||
//
|
||||
// Commit
|
||||
//
|
||||
unsigned iewToCommitDelay;
|
||||
unsigned renameToROBDelay;
|
||||
unsigned commitWidth;
|
||||
unsigned squashWidth;
|
||||
Tick trapLatency;
|
||||
Tick fetchTrapLatency;
|
||||
|
||||
//
|
||||
// Timebuffer sizes
|
||||
//
|
||||
unsigned backComSize;
|
||||
unsigned forwardComSize;
|
||||
|
||||
//
|
||||
// Branch predictor (BP, BTB, RAS)
|
||||
//
|
||||
std::string predType;
|
||||
unsigned localPredictorSize;
|
||||
unsigned localCtrBits;
|
||||
unsigned localHistoryTableSize;
|
||||
unsigned localHistoryBits;
|
||||
unsigned globalPredictorSize;
|
||||
unsigned globalCtrBits;
|
||||
unsigned globalHistoryBits;
|
||||
unsigned choicePredictorSize;
|
||||
unsigned choiceCtrBits;
|
||||
|
||||
unsigned BTBEntries;
|
||||
unsigned BTBTagSize;
|
||||
|
||||
unsigned RASSize;
|
||||
|
||||
//
|
||||
// Load store queue
|
||||
//
|
||||
unsigned LQEntries;
|
||||
unsigned SQEntries;
|
||||
|
||||
//
|
||||
// Memory dependence
|
||||
//
|
||||
unsigned SSITSize;
|
||||
unsigned LFSTSize;
|
||||
|
||||
//
|
||||
// Miscellaneous
|
||||
//
|
||||
unsigned numPhysIntRegs;
|
||||
unsigned numPhysFloatRegs;
|
||||
unsigned numIQEntries;
|
||||
unsigned numROBEntries;
|
||||
|
||||
//SMT Parameters
|
||||
unsigned smtNumFetchingThreads;
|
||||
|
||||
std::string smtFetchPolicy;
|
||||
|
||||
std::string smtIQPolicy;
|
||||
unsigned smtIQThreshold;
|
||||
|
||||
std::string smtLSQPolicy;
|
||||
unsigned smtLSQThreshold;
|
||||
|
||||
std::string smtCommitPolicy;
|
||||
|
||||
std::string smtROBPolicy;
|
||||
unsigned smtROBThreshold;
|
||||
|
||||
// Probably can get this from somewhere.
|
||||
unsigned instShiftAmt;
|
||||
};
|
||||
|
||||
#endif // __CPU_O3_ALPHA_PARAMS_HH__
|
|
@ -33,6 +33,7 @@
|
|||
#define __CPU_O3_REGFILE_HH__
|
||||
|
||||
#include "arch/isa_traits.hh"
|
||||
#include "arch/regfile.hh"
|
||||
#include "arch/types.hh"
|
||||
#include "base/trace.hh"
|
||||
#include "config/full_system.hh"
|
||||
|
|
|
@ -36,6 +36,8 @@
|
|||
#include "base/statistics.hh"
|
||||
#include "base/timebuf.hh"
|
||||
|
||||
class DerivO3CPUParams;
|
||||
|
||||
/**
|
||||
* DefaultRename handles both single threaded and SMT rename. Its
|
||||
* width is specified by the parameters; each cycle it tries to rename
|
||||
|
@ -56,7 +58,6 @@ class DefaultRename
|
|||
typedef typename Impl::CPUPol CPUPol;
|
||||
typedef typename Impl::DynInstPtr DynInstPtr;
|
||||
typedef typename Impl::O3CPU O3CPU;
|
||||
typedef typename Impl::Params Params;
|
||||
|
||||
// Typedefs from the CPUPol
|
||||
typedef typename CPUPol::DecodeStruct DecodeStruct;
|
||||
|
@ -107,7 +108,7 @@ class DefaultRename
|
|||
|
||||
public:
|
||||
/** DefaultRename constructor. */
|
||||
DefaultRename(O3CPU *_cpu, Params *params);
|
||||
DefaultRename(O3CPU *_cpu, DerivO3CPUParams *params);
|
||||
|
||||
/** Returns the name of rename. */
|
||||
std::string name() const;
|
||||
|
|
|
@ -35,9 +35,10 @@
|
|||
#include "arch/regfile.hh"
|
||||
#include "config/full_system.hh"
|
||||
#include "cpu/o3/rename.hh"
|
||||
#include "params/DerivO3CPU.hh"
|
||||
|
||||
template <class Impl>
|
||||
DefaultRename<Impl>::DefaultRename(O3CPU *_cpu, Params *params)
|
||||
DefaultRename<Impl>::DefaultRename(O3CPU *_cpu, DerivO3CPUParams *params)
|
||||
: cpu(_cpu),
|
||||
iewToRenameDelay(params->iewToRenameDelay),
|
||||
decodeToRenameDelay(params->decodeToRenameDelay),
|
||||
|
@ -46,7 +47,7 @@ DefaultRename<Impl>::DefaultRename(O3CPU *_cpu, Params *params)
|
|||
commitWidth(params->commitWidth),
|
||||
resumeSerialize(false),
|
||||
resumeUnblocking(false),
|
||||
numThreads(params->numberOfThreads),
|
||||
numThreads(params->numThreads),
|
||||
maxPhysicalRegs(params->numPhysIntRegs + params->numPhysFloatRegs)
|
||||
{
|
||||
_status = Inactive;
|
||||
|
|
|
@ -37,6 +37,7 @@
|
|||
#include "cpu/o3/cpu.hh"
|
||||
#include "sim/byteswap.hh"
|
||||
|
||||
class DerivO3CPUParams;
|
||||
class EndQuiesceEvent;
|
||||
namespace Kernel {
|
||||
class Statistics;
|
||||
|
@ -58,10 +59,9 @@ class SparcO3CPU : public FullO3CPU<Impl>
|
|||
public:
|
||||
typedef O3ThreadState<Impl> ImplState;
|
||||
typedef O3ThreadState<Impl> Thread;
|
||||
typedef typename Impl::Params Params;
|
||||
|
||||
/** Constructs an AlphaO3CPU with the given parameters. */
|
||||
SparcO3CPU(Params *params);
|
||||
SparcO3CPU(DerivO3CPUParams *params);
|
||||
|
||||
/** Registers statistics. */
|
||||
void regStats();
|
||||
|
|
|
@ -35,14 +35,13 @@
|
|||
#include "cpu/base.hh"
|
||||
#include "cpu/o3/sparc/cpu.hh"
|
||||
#include "cpu/o3/sparc/impl.hh"
|
||||
#include "cpu/o3/sparc/params.hh"
|
||||
#include "cpu/o3/fu_pool.hh"
|
||||
#include "params/DerivO3CPU.hh"
|
||||
|
||||
class DerivO3CPU : public SparcO3CPU<SparcSimpleImpl>
|
||||
{
|
||||
public:
|
||||
DerivO3CPU(SparcSimpleParams *p)
|
||||
DerivO3CPU(DerivO3CPUParams *p)
|
||||
: SparcO3CPU<SparcSimpleImpl>(p)
|
||||
{ }
|
||||
};
|
||||
|
@ -50,8 +49,6 @@ class DerivO3CPU : public SparcO3CPU<SparcSimpleImpl>
|
|||
DerivO3CPU *
|
||||
DerivO3CPUParams::create()
|
||||
{
|
||||
DerivO3CPU *cpu;
|
||||
|
||||
#if FULL_SYSTEM
|
||||
// Full-system only supports a single thread for the moment.
|
||||
int actual_num_threads = 1;
|
||||
|
@ -66,135 +63,18 @@ DerivO3CPUParams::create()
|
|||
}
|
||||
#endif
|
||||
|
||||
SparcSimpleParams *params = new SparcSimpleParams;
|
||||
|
||||
params->clock = clock;
|
||||
params->phase = phase;
|
||||
|
||||
params->tracer = tracer;
|
||||
|
||||
params->name = name;
|
||||
params->numberOfThreads = actual_num_threads;
|
||||
params->cpu_id = cpu_id;
|
||||
params->activity = activity;
|
||||
|
||||
params->itb = itb;
|
||||
params->dtb = dtb;
|
||||
|
||||
params->system = system;
|
||||
#if FULL_SYSTEM
|
||||
params->profile = profile;
|
||||
|
||||
params->do_quiesce = do_quiesce;
|
||||
params->do_checkpoint_insts = do_checkpoint_insts;
|
||||
params->do_statistics_insts = do_statistics_insts;
|
||||
#else
|
||||
params->workload = workload;
|
||||
#endif // FULL_SYSTEM
|
||||
|
||||
#if USE_CHECKER
|
||||
params->checker = checker;
|
||||
#endif
|
||||
|
||||
params->max_insts_any_thread = max_insts_any_thread;
|
||||
params->max_insts_all_threads = max_insts_all_threads;
|
||||
params->max_loads_any_thread = max_loads_any_thread;
|
||||
params->max_loads_all_threads = max_loads_all_threads;
|
||||
params->progress_interval = progress_interval;
|
||||
|
||||
//
|
||||
// Caches
|
||||
//
|
||||
params->cachePorts = cachePorts;
|
||||
|
||||
params->decodeToFetchDelay = decodeToFetchDelay;
|
||||
params->renameToFetchDelay = renameToFetchDelay;
|
||||
params->iewToFetchDelay = iewToFetchDelay;
|
||||
params->commitToFetchDelay = commitToFetchDelay;
|
||||
params->fetchWidth = fetchWidth;
|
||||
|
||||
params->renameToDecodeDelay = renameToDecodeDelay;
|
||||
params->iewToDecodeDelay = iewToDecodeDelay;
|
||||
params->commitToDecodeDelay = commitToDecodeDelay;
|
||||
params->fetchToDecodeDelay = fetchToDecodeDelay;
|
||||
params->decodeWidth = decodeWidth;
|
||||
|
||||
params->iewToRenameDelay = iewToRenameDelay;
|
||||
params->commitToRenameDelay = commitToRenameDelay;
|
||||
params->decodeToRenameDelay = decodeToRenameDelay;
|
||||
params->renameWidth = renameWidth;
|
||||
|
||||
params->commitToIEWDelay = commitToIEWDelay;
|
||||
params->renameToIEWDelay = renameToIEWDelay;
|
||||
params->issueToExecuteDelay = issueToExecuteDelay;
|
||||
params->dispatchWidth = dispatchWidth;
|
||||
params->issueWidth = issueWidth;
|
||||
params->wbWidth = wbWidth;
|
||||
params->wbDepth = wbDepth;
|
||||
params->fuPool = fuPool;
|
||||
|
||||
params->iewToCommitDelay = iewToCommitDelay;
|
||||
params->renameToROBDelay = renameToROBDelay;
|
||||
params->commitWidth = commitWidth;
|
||||
params->squashWidth = squashWidth;
|
||||
params->trapLatency = trapLatency;
|
||||
|
||||
params->backComSize = backComSize;
|
||||
params->forwardComSize = forwardComSize;
|
||||
|
||||
params->predType = predType;
|
||||
params->localPredictorSize = localPredictorSize;
|
||||
params->localCtrBits = localCtrBits;
|
||||
params->localHistoryTableSize = localHistoryTableSize;
|
||||
params->localHistoryBits = localHistoryBits;
|
||||
params->globalPredictorSize = globalPredictorSize;
|
||||
params->globalCtrBits = globalCtrBits;
|
||||
params->globalHistoryBits = globalHistoryBits;
|
||||
params->choicePredictorSize = choicePredictorSize;
|
||||
params->choiceCtrBits = choiceCtrBits;
|
||||
|
||||
params->BTBEntries = BTBEntries;
|
||||
params->BTBTagSize = BTBTagSize;
|
||||
|
||||
params->RASSize = RASSize;
|
||||
|
||||
params->LQEntries = LQEntries;
|
||||
params->SQEntries = SQEntries;
|
||||
|
||||
params->SSITSize = SSITSize;
|
||||
params->LFSTSize = LFSTSize;
|
||||
|
||||
params->numPhysIntRegs = numPhysIntRegs;
|
||||
params->numPhysFloatRegs = numPhysFloatRegs;
|
||||
params->numIQEntries = numIQEntries;
|
||||
params->numROBEntries = numROBEntries;
|
||||
|
||||
params->smtNumFetchingThreads = smtNumFetchingThreads;
|
||||
numThreads = actual_num_threads;
|
||||
|
||||
// Default smtFetchPolicy to "RoundRobin", if necessary.
|
||||
std::string round_robin_policy = "RoundRobin";
|
||||
std::string single_thread = "SingleThread";
|
||||
|
||||
if (actual_num_threads > 1 && single_thread.compare(smtFetchPolicy) == 0)
|
||||
params->smtFetchPolicy = round_robin_policy;
|
||||
smtFetchPolicy = round_robin_policy;
|
||||
else
|
||||
params->smtFetchPolicy = smtFetchPolicy;
|
||||
smtFetchPolicy = smtFetchPolicy;
|
||||
|
||||
params->smtIQPolicy = smtIQPolicy;
|
||||
params->smtLSQPolicy = smtLSQPolicy;
|
||||
params->smtLSQThreshold = smtLSQThreshold;
|
||||
params->smtROBPolicy = smtROBPolicy;
|
||||
params->smtROBThreshold = smtROBThreshold;
|
||||
params->smtCommitPolicy = smtCommitPolicy;
|
||||
instShiftAmt = 2;
|
||||
|
||||
params->instShiftAmt = 2;
|
||||
|
||||
params->deferRegistration = defer_registration;
|
||||
|
||||
params->functionTrace = function_trace;
|
||||
params->functionTraceStart = function_trace_start;
|
||||
|
||||
cpu = new DerivO3CPU(params);
|
||||
|
||||
return cpu;
|
||||
return new DerivO3CPU(this);
|
||||
}
|
||||
|
|
|
@ -41,7 +41,6 @@
|
|||
#include "sim/stats.hh"
|
||||
|
||||
#include "cpu/o3/sparc/cpu.hh"
|
||||
#include "cpu/o3/sparc/params.hh"
|
||||
#include "cpu/o3/sparc/thread_context.hh"
|
||||
#include "cpu/o3/comm.hh"
|
||||
#include "cpu/o3/thread_state.hh"
|
||||
|
@ -54,8 +53,11 @@
|
|||
#include "sim/system.hh"
|
||||
#endif
|
||||
|
||||
#include "params/DerivO3CPU.hh"
|
||||
|
||||
template <class Impl>
|
||||
SparcO3CPU<Impl>::SparcO3CPU(Params *params) : FullO3CPU<Impl>(this, params)
|
||||
SparcO3CPU<Impl>::SparcO3CPU(DerivO3CPUParams *params) :
|
||||
FullO3CPU<Impl>(this, params)
|
||||
{
|
||||
DPRINTF(O3CPU, "Creating SparcO3CPU object.\n");
|
||||
|
||||
|
|
|
@ -33,7 +33,6 @@
|
|||
|
||||
#include "arch/sparc/isa_traits.hh"
|
||||
|
||||
#include "cpu/o3/sparc/params.hh"
|
||||
#include "cpu/o3/cpu_policy.hh"
|
||||
|
||||
|
||||
|
@ -77,9 +76,6 @@ struct SparcSimpleImpl
|
|||
*/
|
||||
typedef O3CPU CPUType;
|
||||
|
||||
/** The Params to be passed to each stage. */
|
||||
typedef SparcSimpleParams Params;
|
||||
|
||||
enum {
|
||||
MaxWidth = 8,
|
||||
MaxThreads = 4
|
||||
|
|
|
@ -1,61 +0,0 @@
|
|||
/*
|
||||
* Copyright (c) 2004-2006 The Regents of The University of Michigan
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are
|
||||
* met: redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer;
|
||||
* redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution;
|
||||
* neither the name of the copyright holders nor the names of its
|
||||
* contributors may be used to endorse or promote products derived from
|
||||
* this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
* Authors: Gabe Black
|
||||
*/
|
||||
|
||||
#ifndef __CPU_O3_SPARC_PARAMS_HH__
|
||||
#define __CPU_O3_SPARC_PARAMS_HH__
|
||||
|
||||
#include "cpu/o3/cpu.hh"
|
||||
#include "cpu/o3/params.hh"
|
||||
|
||||
//Forward declarations
|
||||
namespace SparcISA
|
||||
{
|
||||
class DTB;
|
||||
class ITB;
|
||||
}
|
||||
class MemObject;
|
||||
class Process;
|
||||
class System;
|
||||
|
||||
/**
|
||||
* This file defines the parameters that will be used for the AlphaO3CPU.
|
||||
* This must be defined externally so that the Impl can have a params class
|
||||
* defined that it can pass to all of the individual stages.
|
||||
*/
|
||||
|
||||
class SparcSimpleParams : public O3Params
|
||||
{
|
||||
public:
|
||||
|
||||
SparcISA::ITB *itb;
|
||||
SparcISA::DTB *dtb;
|
||||
};
|
||||
|
||||
#endif // __CPU_O3_SPARC_PARAMS_HH__
|
|
@ -80,8 +80,8 @@ struct O3ThreadState : public ThreadState {
|
|||
: ThreadState(_cpu, -1, _thread_num),
|
||||
cpu(_cpu), inSyscall(0), trapPending(0)
|
||||
{
|
||||
if (cpu->params->profile) {
|
||||
profile = new FunctionProfile(cpu->params->system->kernelSymtab);
|
||||
if (cpu->params()->profile) {
|
||||
profile = new FunctionProfile(cpu->params()->system->kernelSymtab);
|
||||
Callback *cb =
|
||||
new MakeCallback<O3ThreadState,
|
||||
&O3ThreadState::dumpFuncProfile>(this);
|
||||
|
|
|
@ -28,9 +28,9 @@
|
|||
|
||||
from m5.params import *
|
||||
from m5 import build_env
|
||||
from BaseCPU import BaseCPU
|
||||
from BaseSimpleCPU import BaseSimpleCPU
|
||||
|
||||
class AtomicSimpleCPU(BaseCPU):
|
||||
class AtomicSimpleCPU(BaseSimpleCPU):
|
||||
type = 'AtomicSimpleCPU'
|
||||
width = Param.Int(1, "CPU width")
|
||||
simulate_data_stalls = Param.Bool(False, "Simulate dcache stall cycles")
|
||||
|
@ -42,5 +42,5 @@ class AtomicSimpleCPU(BaseCPU):
|
|||
icache_port = Port("Instruction Port")
|
||||
dcache_port = Port("Data Port")
|
||||
physmem_port = Port("Physical Memory Port")
|
||||
_mem_ports = BaseCPU._mem_ports + \
|
||||
_mem_ports = BaseSimpleCPU._mem_ports + \
|
||||
['icache_port', 'dcache_port', 'physmem_port']
|
||||
|
|
34
src/cpu/simple/BaseSimpleCPU.py
Normal file
34
src/cpu/simple/BaseSimpleCPU.py
Normal file
|
@ -0,0 +1,34 @@
|
|||
# Copyright (c) 2008 The Hewlett-Packard Development Company
|
||||
# All rights reserved.
|
||||
#
|
||||
# Redistribution and use in source and binary forms, with or without
|
||||
# modification, are permitted provided that the following conditions are
|
||||
# met: redistributions of source code must retain the above copyright
|
||||
# notice, this list of conditions and the following disclaimer;
|
||||
# redistributions in binary form must reproduce the above copyright
|
||||
# notice, this list of conditions and the following disclaimer in the
|
||||
# documentation and/or other materials provided with the distribution;
|
||||
# neither the name of the copyright holders nor the names of its
|
||||
# contributors may be used to endorse or promote products derived from
|
||||
# this software without specific prior written permission.
|
||||
#
|
||||
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
#
|
||||
# Authors: Gabe Black
|
||||
|
||||
from m5.params import *
|
||||
from BaseCPU import BaseCPU
|
||||
|
||||
class BaseSimpleCPU(BaseCPU):
|
||||
type = 'BaseSimpleCPU'
|
||||
abstract = True
|
|
@ -47,3 +47,4 @@ if 'AtomicSimpleCPU' in env['CPU_MODELS'] or \
|
|||
|
||||
if need_simple_base:
|
||||
Source('base.cc')
|
||||
SimObject('BaseSimpleCPU.py')
|
||||
|
|
|
@ -28,9 +28,9 @@
|
|||
|
||||
from m5.params import *
|
||||
from m5 import build_env
|
||||
from BaseCPU import BaseCPU
|
||||
from BaseSimpleCPU import BaseSimpleCPU
|
||||
|
||||
class TimingSimpleCPU(BaseCPU):
|
||||
class TimingSimpleCPU(BaseSimpleCPU):
|
||||
type = 'TimingSimpleCPU'
|
||||
function_trace = Param.Bool(False, "Enable function trace")
|
||||
function_trace_start = Param.Tick(0, "Cycle to start function trace")
|
||||
|
@ -38,4 +38,4 @@ class TimingSimpleCPU(BaseCPU):
|
|||
profile = Param.Latency('0ns', "trace the kernel stack")
|
||||
icache_port = Port("Instruction Port")
|
||||
dcache_port = Port("Data Port")
|
||||
_mem_ports = BaseCPU._mem_ports + ['icache_port', 'dcache_port']
|
||||
_mem_ports = BaseSimpleCPU._mem_ports + ['icache_port', 'dcache_port']
|
||||
|
|
|
@ -152,7 +152,7 @@ AtomicSimpleCPU::DcachePort::setPeer(Port *port)
|
|||
#endif
|
||||
}
|
||||
|
||||
AtomicSimpleCPU::AtomicSimpleCPU(Params *p)
|
||||
AtomicSimpleCPU::AtomicSimpleCPU(AtomicSimpleCPUParams *p)
|
||||
: BaseSimpleCPU(p), tickEvent(this), width(p->width),
|
||||
simulate_data_stalls(p->simulate_data_stalls),
|
||||
simulate_inst_stalls(p->simulate_inst_stalls),
|
||||
|
@ -812,39 +812,10 @@ AtomicSimpleCPU::printAddr(Addr a)
|
|||
AtomicSimpleCPU *
|
||||
AtomicSimpleCPUParams::create()
|
||||
{
|
||||
AtomicSimpleCPU::Params *params = new AtomicSimpleCPU::Params();
|
||||
params->name = name;
|
||||
params->numberOfThreads = 1;
|
||||
params->max_insts_any_thread = max_insts_any_thread;
|
||||
params->max_insts_all_threads = max_insts_all_threads;
|
||||
params->max_loads_any_thread = max_loads_any_thread;
|
||||
params->max_loads_all_threads = max_loads_all_threads;
|
||||
params->progress_interval = progress_interval;
|
||||
params->deferRegistration = defer_registration;
|
||||
params->phase = phase;
|
||||
params->clock = clock;
|
||||
params->functionTrace = function_trace;
|
||||
params->functionTraceStart = function_trace_start;
|
||||
params->width = width;
|
||||
params->simulate_data_stalls = simulate_data_stalls;
|
||||
params->simulate_inst_stalls = simulate_inst_stalls;
|
||||
params->system = system;
|
||||
params->cpu_id = cpu_id;
|
||||
params->tracer = tracer;
|
||||
|
||||
params->itb = itb;
|
||||
params->dtb = dtb;
|
||||
#if FULL_SYSTEM
|
||||
params->profile = profile;
|
||||
params->do_quiesce = do_quiesce;
|
||||
params->do_checkpoint_insts = do_checkpoint_insts;
|
||||
params->do_statistics_insts = do_statistics_insts;
|
||||
#else
|
||||
numThreads = 1;
|
||||
#if !FULL_SYSTEM
|
||||
if (workload.size() != 1)
|
||||
panic("only one workload allowed");
|
||||
params->process = workload[0];
|
||||
#endif
|
||||
|
||||
AtomicSimpleCPU *cpu = new AtomicSimpleCPU(params);
|
||||
return cpu;
|
||||
return new AtomicSimpleCPU(this);
|
||||
}
|
||||
|
|
|
@ -32,18 +32,13 @@
|
|||
#define __CPU_SIMPLE_ATOMIC_HH__
|
||||
|
||||
#include "cpu/simple/base.hh"
|
||||
#include "params/AtomicSimpleCPU.hh"
|
||||
|
||||
class AtomicSimpleCPU : public BaseSimpleCPU
|
||||
{
|
||||
public:
|
||||
|
||||
struct Params : public BaseSimpleCPU::Params {
|
||||
int width;
|
||||
bool simulate_data_stalls;
|
||||
bool simulate_inst_stalls;
|
||||
};
|
||||
|
||||
AtomicSimpleCPU(Params *params);
|
||||
AtomicSimpleCPU(AtomicSimpleCPUParams *params);
|
||||
virtual ~AtomicSimpleCPU();
|
||||
|
||||
virtual void init();
|
||||
|
|
|
@ -65,16 +65,18 @@
|
|||
#include "mem/mem_object.hh"
|
||||
#endif // FULL_SYSTEM
|
||||
|
||||
#include "params/BaseSimpleCPU.hh"
|
||||
|
||||
using namespace std;
|
||||
using namespace TheISA;
|
||||
|
||||
BaseSimpleCPU::BaseSimpleCPU(Params *p)
|
||||
BaseSimpleCPU::BaseSimpleCPU(BaseSimpleCPUParams *p)
|
||||
: BaseCPU(p), traceData(NULL), thread(NULL), predecoder(NULL)
|
||||
{
|
||||
#if FULL_SYSTEM
|
||||
thread = new SimpleThread(this, 0, p->system, p->itb, p->dtb);
|
||||
#else
|
||||
thread = new SimpleThread(this, /* thread_num */ 0, p->process,
|
||||
thread = new SimpleThread(this, /* thread_num */ 0, p->workload[0],
|
||||
p->itb, p->dtb, /* asid */ 0);
|
||||
#endif // !FULL_SYSTEM
|
||||
|
||||
|
|
|
@ -76,6 +76,8 @@ namespace Trace {
|
|||
class InstRecord;
|
||||
}
|
||||
|
||||
class BaseSimpleCPUParams;
|
||||
|
||||
|
||||
class BaseSimpleCPU : public BaseCPU
|
||||
{
|
||||
|
@ -107,15 +109,7 @@ class BaseSimpleCPU : public BaseCPU
|
|||
};
|
||||
|
||||
public:
|
||||
struct Params : public BaseCPU::Params
|
||||
{
|
||||
TheISA::ITB *itb;
|
||||
TheISA::DTB *dtb;
|
||||
#if !FULL_SYSTEM
|
||||
Process *process;
|
||||
#endif
|
||||
};
|
||||
BaseSimpleCPU(Params *params);
|
||||
BaseSimpleCPU(BaseSimpleCPUParams *params);
|
||||
virtual ~BaseSimpleCPU();
|
||||
|
||||
public:
|
||||
|
|
|
@ -104,7 +104,7 @@ TimingSimpleCPU::CpuPort::TickEvent::schedule(PacketPtr _pkt, Tick t)
|
|||
Event::schedule(t);
|
||||
}
|
||||
|
||||
TimingSimpleCPU::TimingSimpleCPU(Params *p)
|
||||
TimingSimpleCPU::TimingSimpleCPU(TimingSimpleCPUParams *p)
|
||||
: BaseSimpleCPU(p), icachePort(this, p->clock), dcachePort(this, p->clock)
|
||||
{
|
||||
_status = Idle;
|
||||
|
@ -852,36 +852,10 @@ TimingSimpleCPU::printAddr(Addr a)
|
|||
TimingSimpleCPU *
|
||||
TimingSimpleCPUParams::create()
|
||||
{
|
||||
TimingSimpleCPU::Params *params = new TimingSimpleCPU::Params();
|
||||
params->name = name;
|
||||
params->numberOfThreads = 1;
|
||||
params->max_insts_any_thread = max_insts_any_thread;
|
||||
params->max_insts_all_threads = max_insts_all_threads;
|
||||
params->max_loads_any_thread = max_loads_any_thread;
|
||||
params->max_loads_all_threads = max_loads_all_threads;
|
||||
params->progress_interval = progress_interval;
|
||||
params->deferRegistration = defer_registration;
|
||||
params->clock = clock;
|
||||
params->phase = phase;
|
||||
params->functionTrace = function_trace;
|
||||
params->functionTraceStart = function_trace_start;
|
||||
params->system = system;
|
||||
params->cpu_id = cpu_id;
|
||||
params->tracer = tracer;
|
||||
|
||||
params->itb = itb;
|
||||
params->dtb = dtb;
|
||||
#if FULL_SYSTEM
|
||||
params->profile = profile;
|
||||
params->do_quiesce = do_quiesce;
|
||||
params->do_checkpoint_insts = do_checkpoint_insts;
|
||||
params->do_statistics_insts = do_statistics_insts;
|
||||
#else
|
||||
numThreads = 1;
|
||||
#if !FULL_SYSTEM
|
||||
if (workload.size() != 1)
|
||||
panic("only one workload allowed");
|
||||
params->process = workload[0];
|
||||
#endif
|
||||
|
||||
TimingSimpleCPU *cpu = new TimingSimpleCPU(params);
|
||||
return cpu;
|
||||
return new TimingSimpleCPU(this);
|
||||
}
|
||||
|
|
|
@ -33,14 +33,13 @@
|
|||
|
||||
#include "cpu/simple/base.hh"
|
||||
|
||||
#include "params/TimingSimpleCPU.hh"
|
||||
|
||||
class TimingSimpleCPU : public BaseSimpleCPU
|
||||
{
|
||||
public:
|
||||
|
||||
struct Params : public BaseSimpleCPU::Params {
|
||||
};
|
||||
|
||||
TimingSimpleCPU(Params *params);
|
||||
TimingSimpleCPU(TimingSimpleCPUParams * params);
|
||||
virtual ~TimingSimpleCPU();
|
||||
|
||||
virtual void init();
|
||||
|
|
|
@ -37,9 +37,11 @@
|
|||
#include "cpu/base.hh"
|
||||
#include "cpu/simple_thread.hh"
|
||||
#include "cpu/thread_context.hh"
|
||||
#include "params/BaseCPU.hh"
|
||||
|
||||
#if FULL_SYSTEM
|
||||
#include "arch/kernel_stats.hh"
|
||||
#include "arch/stacktrace.hh"
|
||||
#include "base/callback.hh"
|
||||
#include "base/cprintf.hh"
|
||||
#include "base/output.hh"
|
||||
|
@ -48,11 +50,10 @@
|
|||
#include "cpu/quiesce_event.hh"
|
||||
#include "sim/serialize.hh"
|
||||
#include "sim/sim_exit.hh"
|
||||
#include "arch/stacktrace.hh"
|
||||
#else
|
||||
#include "mem/translating_port.hh"
|
||||
#include "sim/process.hh"
|
||||
#include "sim/system.hh"
|
||||
#include "mem/translating_port.hh"
|
||||
#endif
|
||||
|
||||
using namespace std;
|
||||
|
@ -72,7 +73,7 @@ SimpleThread::SimpleThread(BaseCPU *_cpu, int _thread_num, System *_sys,
|
|||
|
||||
regs.clear();
|
||||
|
||||
if (cpu->params->profile) {
|
||||
if (cpu->params()->profile) {
|
||||
profile = new FunctionProfile(system->kernelSymtab);
|
||||
Callback *cb =
|
||||
new MakeCallback<SimpleThread,
|
||||
|
|
|
@ -35,12 +35,13 @@
|
|||
#include <fstream>
|
||||
#include <string>
|
||||
|
||||
#include "arch/kernel_stats.hh"
|
||||
#include "arch/vtophys.hh"
|
||||
#include "base/annotate.hh"
|
||||
#include "cpu/base.hh"
|
||||
#include "cpu/thread_context.hh"
|
||||
#include "cpu/quiesce_event.hh"
|
||||
#include "arch/kernel_stats.hh"
|
||||
#include "params/BaseCPU.hh"
|
||||
#include "sim/pseudo_inst.hh"
|
||||
#include "sim/serialize.hh"
|
||||
#include "sim/sim_exit.hh"
|
||||
|
@ -67,7 +68,7 @@ arm(ThreadContext *tc)
|
|||
void
|
||||
quiesce(ThreadContext *tc)
|
||||
{
|
||||
if (!tc->getCpuPtr()->params->do_quiesce)
|
||||
if (!tc->getCpuPtr()->params()->do_quiesce)
|
||||
return;
|
||||
|
||||
DPRINTF(Quiesce, "%s: quiesce()\n", tc->getCpuPtr()->name());
|
||||
|
@ -80,7 +81,7 @@ quiesce(ThreadContext *tc)
|
|||
void
|
||||
quiesceNs(ThreadContext *tc, uint64_t ns)
|
||||
{
|
||||
if (!tc->getCpuPtr()->params->do_quiesce || ns == 0)
|
||||
if (!tc->getCpuPtr()->params()->do_quiesce || ns == 0)
|
||||
return;
|
||||
|
||||
EndQuiesceEvent *quiesceEvent = tc->getQuiesceEvent();
|
||||
|
@ -100,7 +101,7 @@ quiesceNs(ThreadContext *tc, uint64_t ns)
|
|||
void
|
||||
quiesceCycles(ThreadContext *tc, uint64_t cycles)
|
||||
{
|
||||
if (!tc->getCpuPtr()->params->do_quiesce || cycles == 0)
|
||||
if (!tc->getCpuPtr()->params()->do_quiesce || cycles == 0)
|
||||
return;
|
||||
|
||||
EndQuiesceEvent *quiesceEvent = tc->getQuiesceEvent();
|
||||
|
@ -181,7 +182,7 @@ loadsymbol(ThreadContext *tc)
|
|||
void
|
||||
resetstats(ThreadContext *tc, Tick delay, Tick period)
|
||||
{
|
||||
if (!tc->getCpuPtr()->params->do_statistics_insts)
|
||||
if (!tc->getCpuPtr()->params()->do_statistics_insts)
|
||||
return;
|
||||
|
||||
|
||||
|
@ -194,7 +195,7 @@ resetstats(ThreadContext *tc, Tick delay, Tick period)
|
|||
void
|
||||
dumpstats(ThreadContext *tc, Tick delay, Tick period)
|
||||
{
|
||||
if (!tc->getCpuPtr()->params->do_statistics_insts)
|
||||
if (!tc->getCpuPtr()->params()->do_statistics_insts)
|
||||
return;
|
||||
|
||||
|
||||
|
@ -219,7 +220,7 @@ addsymbol(ThreadContext *tc, Addr addr, Addr symbolAddr)
|
|||
void
|
||||
dumpresetstats(ThreadContext *tc, Tick delay, Tick period)
|
||||
{
|
||||
if (!tc->getCpuPtr()->params->do_statistics_insts)
|
||||
if (!tc->getCpuPtr()->params()->do_statistics_insts)
|
||||
return;
|
||||
|
||||
|
||||
|
@ -232,7 +233,7 @@ dumpresetstats(ThreadContext *tc, Tick delay, Tick period)
|
|||
void
|
||||
m5checkpoint(ThreadContext *tc, Tick delay, Tick period)
|
||||
{
|
||||
if (!tc->getCpuPtr()->params->do_checkpoint_insts)
|
||||
if (!tc->getCpuPtr()->params()->do_checkpoint_insts)
|
||||
return;
|
||||
|
||||
Tick when = curTick + delay * Clock::Int::ns;
|
||||
|
|
Loading…
Reference in a new issue