ARM: Add PCIe support to VExpress_EMM model and remove deprecated ELT
This commit is contained in:
Geoffrey Blake
parent
15228694d0
commit
eced845a5e
1 changed files with 17 additions and 105 deletions
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@ -317,114 +317,10 @@ class RealViewEB(RealView):
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self.flash_fake.pio = bus.master
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self.smcreg_fake.pio = bus.master
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class VExpress_ELT(RealView):
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max_mem_size = '2GB'
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pci_cfg_base = 0xD0000000
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elba_uart = Pl011(pio_addr=0xE0009000, int_num=42)
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uart = Pl011(pio_addr=0xFF009000, int_num=121)
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realview_io = RealViewCtrl(proc_id0=0x0C000222, pio_addr=0xFF000000)
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gic = Gic(dist_addr=0xE0201000, cpu_addr=0xE0200100)
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local_cpu_timer = CpuLocalTimer(int_num_timer=29, int_num_watchdog=30, pio_addr=0xE0200600)
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v2m_timer0 = Sp804(int_num0=120, int_num1=120, pio_addr=0xFF011000)
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v2m_timer1 = Sp804(int_num0=121, int_num1=121, pio_addr=0xFF012000)
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elba_timer0 = Sp804(int_num0=36, int_num1=36, pio_addr=0xE0011000, clock0='50MHz', clock1='50MHz')
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elba_timer1 = Sp804(int_num0=37, int_num1=37, pio_addr=0xE0012000, clock0='50MHz', clock1='50MHz')
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clcd = Pl111(pio_addr=0xE0022000, int_num=46) # CLCD interrupt no. unknown
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kmi0 = Pl050(pio_addr=0xFF006000, int_num=124)
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kmi1 = Pl050(pio_addr=0xFF007000, int_num=125)
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elba_kmi0 = Pl050(pio_addr=0xE0006000, int_num=52)
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elba_kmi1 = Pl050(pio_addr=0xE0007000, int_num=53)
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a9scu = A9SCU(pio_addr=0xE0200000)
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cf_ctrl = IdeController(disks=[], pci_func=0, pci_dev=0, pci_bus=2,
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io_shift = 2, ctrl_offset = 2, Command = 0x1,
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BAR0 = 0xFF01A000, BAR0Size = '256B',
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BAR1 = 0xFF01A100, BAR1Size = '4096B',
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BAR0LegacyIO = True, BAR1LegacyIO = True)
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pciconfig = PciConfigAll()
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ethernet = IGbE_e1000(pci_bus=0, pci_dev=0, pci_func=0,
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InterruptLine=1, InterruptPin=1)
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ide = IdeController(disks = [], pci_bus=0, pci_dev=1, pci_func=0,
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InterruptLine=2, InterruptPin=2)
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l2x0_fake = IsaFake(pio_addr=0xE0202000, pio_size=0xfff)
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dmac_fake = AmbaFake(pio_addr=0xE0020000)
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uart1_fake = AmbaFake(pio_addr=0xE000A000)
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uart2_fake = AmbaFake(pio_addr=0xE000B000)
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uart3_fake = AmbaFake(pio_addr=0xE000C000)
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smc_fake = AmbaFake(pio_addr=0xEC000000)
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sp810_fake = AmbaFake(pio_addr=0xFF001000, ignore_access=True)
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watchdog_fake = AmbaFake(pio_addr=0xE0010000)
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aaci_fake = AmbaFake(pio_addr=0xFF004000)
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elba_aaci_fake = AmbaFake(pio_addr=0xE0004000)
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mmc_fake = AmbaFake(pio_addr=0xE0005000) # not sure if we need this
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rtc_fake = AmbaFake(pio_addr=0xE0017000, amba_id=0x41031)
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spsc_fake = IsaFake(pio_addr=0xE001B000, pio_size=0x2000)
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lan_fake = IsaFake(pio_addr=0xFA000000, pio_size=0xffff)
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usb_fake = IsaFake(pio_addr=0xFB000000, pio_size=0x1ffff)
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# Attach I/O devices that are on chip and also set the appropriate
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# ranges for the bridge
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def attachOnChipIO(self, bus, bridge):
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self.gic.pio = bus.master
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self.a9scu.pio = bus.master
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self.local_cpu_timer.pio = bus.master
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# Bridge ranges based on excluding what is part of on-chip I/O
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# (gic, a9scu)
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bridge.ranges = [AddrRange(self.pci_cfg_base, self.a9scu.pio_addr - 1),
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AddrRange(self.l2x0_fake.pio_addr, Addr.max)]
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# Attach I/O devices to specified bus object. Can't do this
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# earlier, since the bus object itself is typically defined at the
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# System level.
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def attachIO(self, bus):
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self.elba_uart.pio = bus.master
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self.uart.pio = bus.master
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self.realview_io.pio = bus.master
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self.v2m_timer0.pio = bus.master
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self.v2m_timer1.pio = bus.master
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self.elba_timer0.pio = bus.master
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self.elba_timer1.pio = bus.master
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self.clcd.pio = bus.master
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self.clcd.dma = bus.slave
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self.kmi0.pio = bus.master
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self.kmi1.pio = bus.master
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self.elba_kmi0.pio = bus.master
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self.elba_kmi1.pio = bus.master
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self.cf_ctrl.pio = bus.master
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self.cf_ctrl.config = bus.master
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self.cf_ctrl.dma = bus.slave
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self.ide.pio = bus.master
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self.ide.config = bus.master
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self.ide.dma = bus.slave
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self.ethernet.pio = bus.master
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self.ethernet.config = bus.master
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self.ethernet.dma = bus.slave
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self.pciconfig.pio = bus.default
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bus.use_default_range = True
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self.l2x0_fake.pio = bus.master
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self.dmac_fake.pio = bus.master
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self.uart1_fake.pio = bus.master
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self.uart2_fake.pio = bus.master
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self.uart3_fake.pio = bus.master
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self.smc_fake.pio = bus.master
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self.sp810_fake.pio = bus.master
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self.watchdog_fake.pio = bus.master
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self.aaci_fake.pio = bus.master
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self.elba_aaci_fake.pio = bus.master
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self.mmc_fake.pio = bus.master
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self.rtc_fake.pio = bus.master
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self.spsc_fake.pio = bus.master
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self.lan_fake.pio = bus.master
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self.usb_fake.pio = bus.master
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class VExpress_EMM(RealView):
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mem_start_addr = '2GB'
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max_mem_size = '2GB'
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pci_cfg_base = 0x30000000
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uart = Pl011(pio_addr=0x1c090000, int_num=37)
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realview_io = RealViewCtrl(proc_id0=0x14000000, proc_id1=0x14000000, pio_addr=0x1C010000)
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gic = Gic(dist_addr=0x2C001000, cpu_addr=0x2C002000)
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@ -439,6 +335,15 @@ class VExpress_EMM(RealView):
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BAR0 = 0x1C1A0000, BAR0Size = '256B',
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BAR1 = 0x1C1A0100, BAR1Size = '4096B',
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BAR0LegacyIO = True, BAR1LegacyIO = True)
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pciconfig = PciConfigAll(size='256MB')
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ethernet = IGbE_e1000(pci_bus=0, pci_dev=0, pci_func=0,
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InterruptLine=1, InterruptPin=1)
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ide = IdeController(disks = [], pci_bus=0, pci_dev=1, pci_func=0,
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InterruptLine=2, InterruptPin=2)
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vram = SimpleMemory(range = AddrRange(0x18000000, size='32MB'),
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zero = True)
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rtc = PL031(pio_addr=0x1C170000, int_num=36)
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@ -491,6 +396,13 @@ class VExpress_EMM(RealView):
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self.rtc.pio = bus.master
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bus.use_default_range = True
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self.vram.port = bus.master
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self.ide.pio = bus.master
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self.ide.config = bus.master
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self.ide.dma = bus.slave
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self.ethernet.pio = bus.master
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self.ethernet.config = bus.master
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self.ethernet.dma = bus.slave
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self.pciconfig.pio = bus.default
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self.l2x0_fake.pio = bus.master
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self.uart1_fake.pio = bus.master
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