Make the IPRs use regular miscreg indexes, and make a table or two to find the miscreg index of a specific IPR.
--HG-- extra : convert_revision : dd235261e7086d6667b1b2bdc4a81b2573e21d53
This commit is contained in:
Gabe Black
parent
3c19c5f0f2
commit
ece796ab8a
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@ -56,6 +56,7 @@ full_system_sources = Split('''
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tlb.cc
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tlb.cc
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arguments.cc
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arguments.cc
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ev5.cc
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ev5.cc
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ipr.cc
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osfpal.cc
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osfpal.cc
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stacktrace.cc
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stacktrace.cc
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vtophys.cc
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vtophys.cc
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@ -62,7 +62,7 @@ AlphaISA::initCPU(ThreadContext *tc, int cpuId)
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AlphaFault *reset = new ResetFault;
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AlphaFault *reset = new ResetFault;
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tc->setPC(tc->readMiscReg(IPR_PAL_BASE) + reset->vect());
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tc->setPC(tc->readMiscReg(MISCREG_IPR_PAL_BASE) + reset->vect());
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tc->setNextPC(tc->readPC() + sizeof(MachInst));
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tc->setNextPC(tc->readPC() + sizeof(MachInst));
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delete reset;
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delete reset;
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@ -79,9 +79,9 @@ AlphaISA::initIPRs(ThreadContext *tc, int cpuId)
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tc->setMiscReg(i, 0);
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tc->setMiscReg(i, 0);
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}
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}
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tc->setMiscReg(IPR_PAL_BASE, PalBase);
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tc->setMiscReg(MISCREG_IPR_PAL_BASE, PalBase);
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tc->setMiscReg(IPR_MCSR, 0x6);
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tc->setMiscReg(MISCREG_IPR_MCSR, 0x6);
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tc->setMiscReg(IPR_PALtemp16, cpuId);
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tc->setMiscReg(MISCREG_IPR_PALtemp16, cpuId);
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}
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}
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@ -96,13 +96,13 @@ AlphaISA::processInterrupts(CPU *cpu)
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cpu->checkInterrupts = false;
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cpu->checkInterrupts = false;
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if (cpu->readMiscReg(IPR_ASTRR))
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if (cpu->readMiscReg(MISCREG_IPR_ASTRR))
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panic("asynchronous traps not implemented\n");
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panic("asynchronous traps not implemented\n");
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if (cpu->readMiscReg(IPR_SIRR)) {
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if (cpu->readMiscReg(MISCREG_IPR_SIRR)) {
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for (int i = INTLEVEL_SOFTWARE_MIN;
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for (int i = INTLEVEL_SOFTWARE_MIN;
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i < INTLEVEL_SOFTWARE_MAX; i++) {
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i < INTLEVEL_SOFTWARE_MAX; i++) {
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if (cpu->readMiscReg(IPR_SIRR) & (ULL(1) << i)) {
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if (cpu->readMiscReg(MISCREG_IPR_SIRR) & (ULL(1) << i)) {
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// See table 4-19 of the 21164 hardware reference
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// See table 4-19 of the 21164 hardware reference
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ipl = (i - INTLEVEL_SOFTWARE_MIN) + 1;
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ipl = (i - INTLEVEL_SOFTWARE_MIN) + 1;
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summary |= (ULL(1) << i);
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summary |= (ULL(1) << i);
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@ -123,12 +123,12 @@ AlphaISA::processInterrupts(CPU *cpu)
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}
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}
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}
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}
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if (ipl && ipl > cpu->readMiscReg(IPR_IPLR)) {
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if (ipl && ipl > cpu->readMiscReg(MISCREG_IPR_IPLR)) {
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cpu->setMiscReg(IPR_ISR, summary);
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cpu->setMiscReg(MISCREG_IPR_ISR, summary);
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cpu->setMiscReg(IPR_INTID, ipl);
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cpu->setMiscReg(MISCREG_IPR_INTID, ipl);
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cpu->trap(new InterruptFault);
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cpu->trap(new InterruptFault);
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DPRINTF(Flow, "Interrupt! IPLR=%d ipl=%d summary=%x\n",
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DPRINTF(Flow, "Interrupt! IPLR=%d ipl=%d summary=%x\n",
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cpu->readMiscReg(IPR_IPLR), ipl, summary);
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cpu->readMiscReg(MISCREG_IPR_IPLR), ipl, summary);
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}
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}
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}
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}
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@ -150,7 +150,7 @@ SimpleThread::hwrei()
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if (!inPalMode())
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if (!inPalMode())
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return new UnimplementedOpcodeFault;
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return new UnimplementedOpcodeFault;
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setNextPC(readMiscReg(AlphaISA::IPR_EXC_ADDR));
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setNextPC(readMiscReg(AlphaISA::MISCREG_IPR_EXC_ADDR));
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if (!misspeculating()) {
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if (!misspeculating()) {
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if (kernelStats)
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if (kernelStats)
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@ -166,13 +166,13 @@ SimpleThread::hwrei()
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int
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int
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AlphaISA::MiscRegFile::getInstAsid()
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AlphaISA::MiscRegFile::getInstAsid()
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{
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{
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return EV5::ITB_ASN_ASN(ipr[IPR_ITB_ASN]);
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return EV5::ITB_ASN_ASN(ipr[MISCREG_IPR_ITB_ASN]);
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}
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}
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int
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int
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AlphaISA::MiscRegFile::getDataAsid()
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AlphaISA::MiscRegFile::getDataAsid()
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{
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{
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return EV5::DTB_ASN_ASN(ipr[IPR_DTB_ASN]);
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return EV5::DTB_ASN_ASN(ipr[MISCREG_IPR_DTB_ASN]);
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}
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}
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AlphaISA::MiscReg
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AlphaISA::MiscReg
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@ -181,71 +181,71 @@ AlphaISA::MiscRegFile::readIpr(int idx, Fault &fault, ThreadContext *tc)
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uint64_t retval = 0; // return value, default 0
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uint64_t retval = 0; // return value, default 0
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switch (idx) {
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switch (idx) {
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case AlphaISA::IPR_PALtemp0:
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case AlphaISA::MISCREG_IPR_PALtemp0:
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case AlphaISA::IPR_PALtemp1:
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case AlphaISA::MISCREG_IPR_PALtemp1:
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case AlphaISA::IPR_PALtemp2:
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case AlphaISA::MISCREG_IPR_PALtemp2:
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case AlphaISA::IPR_PALtemp3:
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case AlphaISA::MISCREG_IPR_PALtemp3:
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case AlphaISA::IPR_PALtemp4:
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case AlphaISA::MISCREG_IPR_PALtemp4:
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case AlphaISA::IPR_PALtemp5:
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case AlphaISA::MISCREG_IPR_PALtemp5:
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case AlphaISA::IPR_PALtemp6:
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case AlphaISA::MISCREG_IPR_PALtemp6:
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case AlphaISA::IPR_PALtemp7:
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case AlphaISA::MISCREG_IPR_PALtemp7:
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case AlphaISA::IPR_PALtemp8:
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case AlphaISA::MISCREG_IPR_PALtemp8:
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case AlphaISA::IPR_PALtemp9:
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case AlphaISA::MISCREG_IPR_PALtemp9:
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case AlphaISA::IPR_PALtemp10:
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case AlphaISA::MISCREG_IPR_PALtemp10:
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case AlphaISA::IPR_PALtemp11:
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case AlphaISA::MISCREG_IPR_PALtemp11:
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case AlphaISA::IPR_PALtemp12:
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case AlphaISA::MISCREG_IPR_PALtemp12:
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case AlphaISA::IPR_PALtemp13:
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case AlphaISA::MISCREG_IPR_PALtemp13:
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case AlphaISA::IPR_PALtemp14:
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case AlphaISA::MISCREG_IPR_PALtemp14:
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case AlphaISA::IPR_PALtemp15:
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case AlphaISA::MISCREG_IPR_PALtemp15:
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case AlphaISA::IPR_PALtemp16:
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case AlphaISA::MISCREG_IPR_PALtemp16:
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case AlphaISA::IPR_PALtemp17:
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case AlphaISA::MISCREG_IPR_PALtemp17:
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case AlphaISA::IPR_PALtemp18:
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case AlphaISA::MISCREG_IPR_PALtemp18:
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case AlphaISA::IPR_PALtemp19:
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case AlphaISA::MISCREG_IPR_PALtemp19:
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case AlphaISA::IPR_PALtemp20:
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case AlphaISA::MISCREG_IPR_PALtemp20:
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case AlphaISA::IPR_PALtemp21:
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case AlphaISA::MISCREG_IPR_PALtemp21:
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case AlphaISA::IPR_PALtemp22:
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case AlphaISA::MISCREG_IPR_PALtemp22:
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case AlphaISA::IPR_PALtemp23:
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case AlphaISA::MISCREG_IPR_PALtemp23:
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case AlphaISA::IPR_PAL_BASE:
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case AlphaISA::MISCREG_IPR_PAL_BASE:
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case AlphaISA::IPR_IVPTBR:
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case AlphaISA::MISCREG_IPR_IVPTBR:
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case AlphaISA::IPR_DC_MODE:
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case AlphaISA::MISCREG_IPR_DC_MODE:
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case AlphaISA::IPR_MAF_MODE:
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case AlphaISA::MISCREG_IPR_MAF_MODE:
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case AlphaISA::IPR_ISR:
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case AlphaISA::MISCREG_IPR_ISR:
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case AlphaISA::IPR_EXC_ADDR:
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case AlphaISA::MISCREG_IPR_EXC_ADDR:
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case AlphaISA::IPR_IC_PERR_STAT:
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case AlphaISA::MISCREG_IPR_IC_PERR_STAT:
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case AlphaISA::IPR_DC_PERR_STAT:
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case AlphaISA::MISCREG_IPR_DC_PERR_STAT:
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case AlphaISA::IPR_MCSR:
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case AlphaISA::MISCREG_IPR_MCSR:
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case AlphaISA::IPR_ASTRR:
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case AlphaISA::MISCREG_IPR_ASTRR:
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case AlphaISA::IPR_ASTER:
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case AlphaISA::MISCREG_IPR_ASTER:
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case AlphaISA::IPR_SIRR:
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case AlphaISA::MISCREG_IPR_SIRR:
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case AlphaISA::IPR_ICSR:
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case AlphaISA::MISCREG_IPR_ICSR:
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case AlphaISA::IPR_ICM:
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case AlphaISA::MISCREG_IPR_ICM:
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case AlphaISA::IPR_DTB_CM:
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case AlphaISA::MISCREG_IPR_DTB_CM:
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case AlphaISA::IPR_IPLR:
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case AlphaISA::MISCREG_IPR_IPLR:
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case AlphaISA::IPR_INTID:
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case AlphaISA::MISCREG_IPR_INTID:
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case AlphaISA::IPR_PMCTR:
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case AlphaISA::MISCREG_IPR_PMCTR:
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// no side-effect
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// no side-effect
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retval = ipr[idx];
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retval = ipr[idx];
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break;
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break;
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case AlphaISA::IPR_CC:
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case AlphaISA::MISCREG_IPR_CC:
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retval |= ipr[idx] & ULL(0xffffffff00000000);
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retval |= ipr[idx] & ULL(0xffffffff00000000);
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retval |= tc->getCpuPtr()->curCycle() & ULL(0x00000000ffffffff);
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retval |= tc->getCpuPtr()->curCycle() & ULL(0x00000000ffffffff);
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break;
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break;
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case AlphaISA::IPR_VA:
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case AlphaISA::MISCREG_IPR_VA:
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retval = ipr[idx];
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retval = ipr[idx];
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break;
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break;
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case AlphaISA::IPR_VA_FORM:
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case AlphaISA::MISCREG_IPR_VA_FORM:
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case AlphaISA::IPR_MM_STAT:
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case AlphaISA::MISCREG_IPR_MM_STAT:
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case AlphaISA::IPR_IFAULT_VA_FORM:
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case AlphaISA::MISCREG_IPR_IFAULT_VA_FORM:
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case AlphaISA::IPR_EXC_MASK:
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case AlphaISA::MISCREG_IPR_EXC_MASK:
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case AlphaISA::IPR_EXC_SUM:
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case AlphaISA::MISCREG_IPR_EXC_SUM:
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retval = ipr[idx];
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retval = ipr[idx];
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break;
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break;
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case AlphaISA::IPR_DTB_PTE:
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case AlphaISA::MISCREG_IPR_DTB_PTE:
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{
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{
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AlphaISA::PTE &pte = tc->getDTBPtr()->index(!tc->misspeculating());
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AlphaISA::PTE &pte = tc->getDTBPtr()->index(!tc->misspeculating());
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@ -260,15 +260,15 @@ AlphaISA::MiscRegFile::readIpr(int idx, Fault &fault, ThreadContext *tc)
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break;
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break;
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// write only registers
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// write only registers
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case AlphaISA::IPR_HWINT_CLR:
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case AlphaISA::MISCREG_IPR_HWINT_CLR:
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case AlphaISA::IPR_SL_XMIT:
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case AlphaISA::MISCREG_IPR_SL_XMIT:
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case AlphaISA::IPR_DC_FLUSH:
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case AlphaISA::MISCREG_IPR_DC_FLUSH:
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case AlphaISA::IPR_IC_FLUSH:
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case AlphaISA::MISCREG_IPR_IC_FLUSH:
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case AlphaISA::IPR_ALT_MODE:
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case AlphaISA::MISCREG_IPR_ALT_MODE:
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case AlphaISA::IPR_DTB_IA:
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case AlphaISA::MISCREG_IPR_DTB_IA:
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case AlphaISA::IPR_DTB_IAP:
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case AlphaISA::MISCREG_IPR_DTB_IAP:
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case AlphaISA::IPR_ITB_IA:
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case AlphaISA::MISCREG_IPR_ITB_IA:
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case AlphaISA::IPR_ITB_IAP:
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case AlphaISA::MISCREG_IPR_ITB_IAP:
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fault = new UnimplementedOpcodeFault;
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fault = new UnimplementedOpcodeFault;
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break;
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break;
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@ -295,52 +295,52 @@ AlphaISA::MiscRegFile::setIpr(int idx, uint64_t val, ThreadContext *tc)
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return NoFault;
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return NoFault;
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switch (idx) {
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switch (idx) {
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case AlphaISA::IPR_PALtemp0:
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case AlphaISA::MISCREG_IPR_PALtemp0:
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case AlphaISA::IPR_PALtemp1:
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case AlphaISA::MISCREG_IPR_PALtemp1:
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case AlphaISA::IPR_PALtemp2:
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case AlphaISA::MISCREG_IPR_PALtemp2:
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case AlphaISA::IPR_PALtemp3:
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case AlphaISA::MISCREG_IPR_PALtemp3:
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case AlphaISA::IPR_PALtemp4:
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case AlphaISA::MISCREG_IPR_PALtemp4:
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case AlphaISA::IPR_PALtemp5:
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case AlphaISA::MISCREG_IPR_PALtemp5:
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case AlphaISA::IPR_PALtemp6:
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case AlphaISA::MISCREG_IPR_PALtemp6:
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case AlphaISA::IPR_PALtemp7:
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case AlphaISA::MISCREG_IPR_PALtemp7:
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case AlphaISA::IPR_PALtemp8:
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case AlphaISA::MISCREG_IPR_PALtemp8:
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case AlphaISA::IPR_PALtemp9:
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case AlphaISA::MISCREG_IPR_PALtemp9:
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case AlphaISA::IPR_PALtemp10:
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case AlphaISA::MISCREG_IPR_PALtemp10:
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case AlphaISA::IPR_PALtemp11:
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case AlphaISA::MISCREG_IPR_PALtemp11:
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case AlphaISA::IPR_PALtemp12:
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case AlphaISA::MISCREG_IPR_PALtemp12:
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case AlphaISA::IPR_PALtemp13:
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case AlphaISA::MISCREG_IPR_PALtemp13:
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case AlphaISA::IPR_PALtemp14:
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case AlphaISA::MISCREG_IPR_PALtemp14:
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case AlphaISA::IPR_PALtemp15:
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case AlphaISA::MISCREG_IPR_PALtemp15:
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case AlphaISA::IPR_PALtemp16:
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case AlphaISA::MISCREG_IPR_PALtemp16:
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case AlphaISA::IPR_PALtemp17:
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case AlphaISA::MISCREG_IPR_PALtemp17:
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case AlphaISA::IPR_PALtemp18:
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case AlphaISA::MISCREG_IPR_PALtemp18:
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case AlphaISA::IPR_PALtemp19:
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case AlphaISA::MISCREG_IPR_PALtemp19:
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case AlphaISA::IPR_PALtemp20:
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case AlphaISA::MISCREG_IPR_PALtemp20:
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case AlphaISA::IPR_PALtemp21:
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case AlphaISA::MISCREG_IPR_PALtemp21:
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case AlphaISA::IPR_PALtemp22:
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case AlphaISA::MISCREG_IPR_PALtemp22:
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case AlphaISA::IPR_PAL_BASE:
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case AlphaISA::MISCREG_IPR_PAL_BASE:
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case AlphaISA::IPR_IC_PERR_STAT:
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case AlphaISA::MISCREG_IPR_IC_PERR_STAT:
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case AlphaISA::IPR_DC_PERR_STAT:
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case AlphaISA::MISCREG_IPR_DC_PERR_STAT:
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case AlphaISA::IPR_PMCTR:
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case AlphaISA::MISCREG_IPR_PMCTR:
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// write entire quad w/ no side-effect
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// write entire quad w/ no side-effect
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ipr[idx] = val;
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ipr[idx] = val;
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break;
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break;
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case AlphaISA::IPR_CC_CTL:
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case AlphaISA::MISCREG_IPR_CC_CTL:
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// This IPR resets the cycle counter. We assume this only
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// This IPR resets the cycle counter. We assume this only
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// happens once... let's verify that.
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// happens once... let's verify that.
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assert(ipr[idx] == 0);
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assert(ipr[idx] == 0);
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ipr[idx] = 1;
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ipr[idx] = 1;
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break;
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break;
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case AlphaISA::IPR_CC:
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case AlphaISA::MISCREG_IPR_CC:
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// This IPR only writes the upper 64 bits. It's ok to write
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// This IPR only writes the upper 64 bits. It's ok to write
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// all 64 here since we mask out the lower 32 in rpcc (see
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// all 64 here since we mask out the lower 32 in rpcc (see
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// isa_desc).
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// isa_desc).
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ipr[idx] = val;
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ipr[idx] = val;
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break;
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break;
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case AlphaISA::IPR_PALtemp23:
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case AlphaISA::MISCREG_IPR_PALtemp23:
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// write entire quad w/ no side-effect
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// write entire quad w/ no side-effect
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old = ipr[idx];
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old = ipr[idx];
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ipr[idx] = val;
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ipr[idx] = val;
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@ -348,23 +348,23 @@ AlphaISA::MiscRegFile::setIpr(int idx, uint64_t val, ThreadContext *tc)
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tc->getKernelStats()->context(old, val, tc);
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tc->getKernelStats()->context(old, val, tc);
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break;
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break;
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case AlphaISA::IPR_DTB_PTE:
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case AlphaISA::MISCREG_IPR_DTB_PTE:
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// write entire quad w/ no side-effect, tag is forthcoming
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// write entire quad w/ no side-effect, tag is forthcoming
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ipr[idx] = val;
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ipr[idx] = val;
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break;
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break;
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case AlphaISA::IPR_EXC_ADDR:
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case AlphaISA::MISCREG_IPR_EXC_ADDR:
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// second least significant bit in PC is always zero
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// second least significant bit in PC is always zero
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ipr[idx] = val & ~2;
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ipr[idx] = val & ~2;
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break;
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break;
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|
|
||||||
case AlphaISA::IPR_ASTRR:
|
case AlphaISA::MISCREG_IPR_ASTRR:
|
||||||
case AlphaISA::IPR_ASTER:
|
case AlphaISA::MISCREG_IPR_ASTER:
|
||||||
// only write least significant four bits - privilege mask
|
// only write least significant four bits - privilege mask
|
||||||
ipr[idx] = val & 0xf;
|
ipr[idx] = val & 0xf;
|
||||||
break;
|
break;
|
||||||
|
|
||||||
case AlphaISA::IPR_IPLR:
|
case AlphaISA::MISCREG_IPR_IPLR:
|
||||||
#ifdef DEBUG
|
#ifdef DEBUG
|
||||||
if (break_ipl != -1 && break_ipl == (val & 0x1f))
|
if (break_ipl != -1 && break_ipl == (val & 0x1f))
|
||||||
debug_break();
|
debug_break();
|
||||||
|
|
@ -376,7 +376,7 @@ AlphaISA::MiscRegFile::setIpr(int idx, uint64_t val, ThreadContext *tc)
|
||||||
tc->getKernelStats()->swpipl(ipr[idx]);
|
tc->getKernelStats()->swpipl(ipr[idx]);
|
||||||
break;
|
break;
|
||||||
|
|
||||||
case AlphaISA::IPR_DTB_CM:
|
case AlphaISA::MISCREG_IPR_DTB_CM:
|
||||||
if (val & 0x18) {
|
if (val & 0x18) {
|
||||||
if (tc->getKernelStats())
|
if (tc->getKernelStats())
|
||||||
tc->getKernelStats()->mode(Kernel::user, tc);
|
tc->getKernelStats()->mode(Kernel::user, tc);
|
||||||
|
|
@ -385,121 +385,121 @@ AlphaISA::MiscRegFile::setIpr(int idx, uint64_t val, ThreadContext *tc)
|
||||||
tc->getKernelStats()->mode(Kernel::kernel, tc);
|
tc->getKernelStats()->mode(Kernel::kernel, tc);
|
||||||
}
|
}
|
||||||
|
|
||||||
case AlphaISA::IPR_ICM:
|
case AlphaISA::MISCREG_IPR_ICM:
|
||||||
// only write two mode bits - processor mode
|
// only write two mode bits - processor mode
|
||||||
ipr[idx] = val & 0x18;
|
ipr[idx] = val & 0x18;
|
||||||
break;
|
break;
|
||||||
|
|
||||||
case AlphaISA::IPR_ALT_MODE:
|
case AlphaISA::MISCREG_IPR_ALT_MODE:
|
||||||
// only write two mode bits - processor mode
|
// only write two mode bits - processor mode
|
||||||
ipr[idx] = val & 0x18;
|
ipr[idx] = val & 0x18;
|
||||||
break;
|
break;
|
||||||
|
|
||||||
case AlphaISA::IPR_MCSR:
|
case AlphaISA::MISCREG_IPR_MCSR:
|
||||||
// more here after optimization...
|
// more here after optimization...
|
||||||
ipr[idx] = val;
|
ipr[idx] = val;
|
||||||
break;
|
break;
|
||||||
|
|
||||||
case AlphaISA::IPR_SIRR:
|
case AlphaISA::MISCREG_IPR_SIRR:
|
||||||
// only write software interrupt mask
|
// only write software interrupt mask
|
||||||
ipr[idx] = val & 0x7fff0;
|
ipr[idx] = val & 0x7fff0;
|
||||||
break;
|
break;
|
||||||
|
|
||||||
case AlphaISA::IPR_ICSR:
|
case AlphaISA::MISCREG_IPR_ICSR:
|
||||||
ipr[idx] = val & ULL(0xffffff0300);
|
ipr[idx] = val & ULL(0xffffff0300);
|
||||||
break;
|
break;
|
||||||
|
|
||||||
case AlphaISA::IPR_IVPTBR:
|
case AlphaISA::MISCREG_IPR_IVPTBR:
|
||||||
case AlphaISA::IPR_MVPTBR:
|
case AlphaISA::MISCREG_IPR_MVPTBR:
|
||||||
ipr[idx] = val & ULL(0xffffffffc0000000);
|
ipr[idx] = val & ULL(0xffffffffc0000000);
|
||||||
break;
|
break;
|
||||||
|
|
||||||
case AlphaISA::IPR_DC_TEST_CTL:
|
case AlphaISA::MISCREG_IPR_DC_TEST_CTL:
|
||||||
ipr[idx] = val & 0x1ffb;
|
ipr[idx] = val & 0x1ffb;
|
||||||
break;
|
break;
|
||||||
|
|
||||||
case AlphaISA::IPR_DC_MODE:
|
case AlphaISA::MISCREG_IPR_DC_MODE:
|
||||||
case AlphaISA::IPR_MAF_MODE:
|
case AlphaISA::MISCREG_IPR_MAF_MODE:
|
||||||
ipr[idx] = val & 0x3f;
|
ipr[idx] = val & 0x3f;
|
||||||
break;
|
break;
|
||||||
|
|
||||||
case AlphaISA::IPR_ITB_ASN:
|
case AlphaISA::MISCREG_IPR_ITB_ASN:
|
||||||
ipr[idx] = val & 0x7f0;
|
ipr[idx] = val & 0x7f0;
|
||||||
break;
|
break;
|
||||||
|
|
||||||
case AlphaISA::IPR_DTB_ASN:
|
case AlphaISA::MISCREG_IPR_DTB_ASN:
|
||||||
ipr[idx] = val & ULL(0xfe00000000000000);
|
ipr[idx] = val & ULL(0xfe00000000000000);
|
||||||
break;
|
break;
|
||||||
|
|
||||||
case AlphaISA::IPR_EXC_SUM:
|
case AlphaISA::MISCREG_IPR_EXC_SUM:
|
||||||
case AlphaISA::IPR_EXC_MASK:
|
case AlphaISA::MISCREG_IPR_EXC_MASK:
|
||||||
// any write to this register clears it
|
// any write to this register clears it
|
||||||
ipr[idx] = 0;
|
ipr[idx] = 0;
|
||||||
break;
|
break;
|
||||||
|
|
||||||
case AlphaISA::IPR_INTID:
|
case AlphaISA::MISCREG_IPR_INTID:
|
||||||
case AlphaISA::IPR_SL_RCV:
|
case AlphaISA::MISCREG_IPR_SL_RCV:
|
||||||
case AlphaISA::IPR_MM_STAT:
|
case AlphaISA::MISCREG_IPR_MM_STAT:
|
||||||
case AlphaISA::IPR_ITB_PTE_TEMP:
|
case AlphaISA::MISCREG_IPR_ITB_PTE_TEMP:
|
||||||
case AlphaISA::IPR_DTB_PTE_TEMP:
|
case AlphaISA::MISCREG_IPR_DTB_PTE_TEMP:
|
||||||
// read-only registers
|
// read-only registers
|
||||||
return new UnimplementedOpcodeFault;
|
return new UnimplementedOpcodeFault;
|
||||||
|
|
||||||
case AlphaISA::IPR_HWINT_CLR:
|
case AlphaISA::MISCREG_IPR_HWINT_CLR:
|
||||||
case AlphaISA::IPR_SL_XMIT:
|
case AlphaISA::MISCREG_IPR_SL_XMIT:
|
||||||
case AlphaISA::IPR_DC_FLUSH:
|
case AlphaISA::MISCREG_IPR_DC_FLUSH:
|
||||||
case AlphaISA::IPR_IC_FLUSH:
|
case AlphaISA::MISCREG_IPR_IC_FLUSH:
|
||||||
// the following are write only
|
// the following are write only
|
||||||
ipr[idx] = val;
|
ipr[idx] = val;
|
||||||
break;
|
break;
|
||||||
|
|
||||||
case AlphaISA::IPR_DTB_IA:
|
case AlphaISA::MISCREG_IPR_DTB_IA:
|
||||||
// really a control write
|
// really a control write
|
||||||
ipr[idx] = 0;
|
ipr[idx] = 0;
|
||||||
|
|
||||||
tc->getDTBPtr()->flushAll();
|
tc->getDTBPtr()->flushAll();
|
||||||
break;
|
break;
|
||||||
|
|
||||||
case AlphaISA::IPR_DTB_IAP:
|
case AlphaISA::MISCREG_IPR_DTB_IAP:
|
||||||
// really a control write
|
// really a control write
|
||||||
ipr[idx] = 0;
|
ipr[idx] = 0;
|
||||||
|
|
||||||
tc->getDTBPtr()->flushProcesses();
|
tc->getDTBPtr()->flushProcesses();
|
||||||
break;
|
break;
|
||||||
|
|
||||||
case AlphaISA::IPR_DTB_IS:
|
case AlphaISA::MISCREG_IPR_DTB_IS:
|
||||||
// really a control write
|
// really a control write
|
||||||
ipr[idx] = val;
|
ipr[idx] = val;
|
||||||
|
|
||||||
tc->getDTBPtr()->flushAddr(val,
|
tc->getDTBPtr()->flushAddr(val,
|
||||||
DTB_ASN_ASN(ipr[AlphaISA::IPR_DTB_ASN]));
|
DTB_ASN_ASN(ipr[AlphaISA::MISCREG_IPR_DTB_ASN]));
|
||||||
break;
|
break;
|
||||||
|
|
||||||
case AlphaISA::IPR_DTB_TAG: {
|
case AlphaISA::MISCREG_IPR_DTB_TAG: {
|
||||||
struct AlphaISA::PTE pte;
|
struct AlphaISA::PTE pte;
|
||||||
|
|
||||||
// FIXME: granularity hints NYI...
|
// FIXME: granularity hints NYI...
|
||||||
if (DTB_PTE_GH(ipr[AlphaISA::IPR_DTB_PTE]) != 0)
|
if (DTB_PTE_GH(ipr[AlphaISA::MISCREG_IPR_DTB_PTE]) != 0)
|
||||||
panic("PTE GH field != 0");
|
panic("PTE GH field != 0");
|
||||||
|
|
||||||
// write entire quad
|
// write entire quad
|
||||||
ipr[idx] = val;
|
ipr[idx] = val;
|
||||||
|
|
||||||
// construct PTE for new entry
|
// construct PTE for new entry
|
||||||
pte.ppn = DTB_PTE_PPN(ipr[AlphaISA::IPR_DTB_PTE]);
|
pte.ppn = DTB_PTE_PPN(ipr[AlphaISA::MISCREG_IPR_DTB_PTE]);
|
||||||
pte.xre = DTB_PTE_XRE(ipr[AlphaISA::IPR_DTB_PTE]);
|
pte.xre = DTB_PTE_XRE(ipr[AlphaISA::MISCREG_IPR_DTB_PTE]);
|
||||||
pte.xwe = DTB_PTE_XWE(ipr[AlphaISA::IPR_DTB_PTE]);
|
pte.xwe = DTB_PTE_XWE(ipr[AlphaISA::MISCREG_IPR_DTB_PTE]);
|
||||||
pte.fonr = DTB_PTE_FONR(ipr[AlphaISA::IPR_DTB_PTE]);
|
pte.fonr = DTB_PTE_FONR(ipr[AlphaISA::MISCREG_IPR_DTB_PTE]);
|
||||||
pte.fonw = DTB_PTE_FONW(ipr[AlphaISA::IPR_DTB_PTE]);
|
pte.fonw = DTB_PTE_FONW(ipr[AlphaISA::MISCREG_IPR_DTB_PTE]);
|
||||||
pte.asma = DTB_PTE_ASMA(ipr[AlphaISA::IPR_DTB_PTE]);
|
pte.asma = DTB_PTE_ASMA(ipr[AlphaISA::MISCREG_IPR_DTB_PTE]);
|
||||||
pte.asn = DTB_ASN_ASN(ipr[AlphaISA::IPR_DTB_ASN]);
|
pte.asn = DTB_ASN_ASN(ipr[AlphaISA::MISCREG_IPR_DTB_ASN]);
|
||||||
|
|
||||||
// insert new TAG/PTE value into data TLB
|
// insert new TAG/PTE value into data TLB
|
||||||
tc->getDTBPtr()->insert(val, pte);
|
tc->getDTBPtr()->insert(val, pte);
|
||||||
}
|
}
|
||||||
break;
|
break;
|
||||||
|
|
||||||
case AlphaISA::IPR_ITB_PTE: {
|
case AlphaISA::MISCREG_IPR_ITB_PTE: {
|
||||||
struct AlphaISA::PTE pte;
|
struct AlphaISA::PTE pte;
|
||||||
|
|
||||||
// FIXME: granularity hints NYI...
|
// FIXME: granularity hints NYI...
|
||||||
|
|
@ -516,33 +516,33 @@ AlphaISA::MiscRegFile::setIpr(int idx, uint64_t val, ThreadContext *tc)
|
||||||
pte.fonr = ITB_PTE_FONR(val);
|
pte.fonr = ITB_PTE_FONR(val);
|
||||||
pte.fonw = ITB_PTE_FONW(val);
|
pte.fonw = ITB_PTE_FONW(val);
|
||||||
pte.asma = ITB_PTE_ASMA(val);
|
pte.asma = ITB_PTE_ASMA(val);
|
||||||
pte.asn = ITB_ASN_ASN(ipr[AlphaISA::IPR_ITB_ASN]);
|
pte.asn = ITB_ASN_ASN(ipr[AlphaISA::MISCREG_IPR_ITB_ASN]);
|
||||||
|
|
||||||
// insert new TAG/PTE value into data TLB
|
// insert new TAG/PTE value into data TLB
|
||||||
tc->getITBPtr()->insert(ipr[AlphaISA::IPR_ITB_TAG], pte);
|
tc->getITBPtr()->insert(ipr[AlphaISA::MISCREG_IPR_ITB_TAG], pte);
|
||||||
}
|
}
|
||||||
break;
|
break;
|
||||||
|
|
||||||
case AlphaISA::IPR_ITB_IA:
|
case AlphaISA::MISCREG_IPR_ITB_IA:
|
||||||
// really a control write
|
// really a control write
|
||||||
ipr[idx] = 0;
|
ipr[idx] = 0;
|
||||||
|
|
||||||
tc->getITBPtr()->flushAll();
|
tc->getITBPtr()->flushAll();
|
||||||
break;
|
break;
|
||||||
|
|
||||||
case AlphaISA::IPR_ITB_IAP:
|
case AlphaISA::MISCREG_IPR_ITB_IAP:
|
||||||
// really a control write
|
// really a control write
|
||||||
ipr[idx] = 0;
|
ipr[idx] = 0;
|
||||||
|
|
||||||
tc->getITBPtr()->flushProcesses();
|
tc->getITBPtr()->flushProcesses();
|
||||||
break;
|
break;
|
||||||
|
|
||||||
case AlphaISA::IPR_ITB_IS:
|
case AlphaISA::MISCREG_IPR_ITB_IS:
|
||||||
// really a control write
|
// really a control write
|
||||||
ipr[idx] = val;
|
ipr[idx] = val;
|
||||||
|
|
||||||
tc->getITBPtr()->flushAddr(val,
|
tc->getITBPtr()->flushAddr(val,
|
||||||
ITB_ASN_ASN(ipr[AlphaISA::IPR_ITB_ASN]));
|
ITB_ASN_ASN(ipr[AlphaISA::MISCREG_IPR_ITB_ASN]));
|
||||||
break;
|
break;
|
||||||
|
|
||||||
default:
|
default:
|
||||||
|
|
|
||||||
140
src/arch/alpha/ipr.cc
Normal file
140
src/arch/alpha/ipr.cc
Normal file
|
|
@ -0,0 +1,140 @@
|
||||||
|
/*
|
||||||
|
* Copyright (c) 2003-2005 The Regents of The University of Michigan
|
||||||
|
* All rights reserved.
|
||||||
|
*
|
||||||
|
* Redistribution and use in source and binary forms, with or without
|
||||||
|
* modification, are permitted provided that the following conditions are
|
||||||
|
* met: redistributions of source code must retain the above copyright
|
||||||
|
* notice, this list of conditions and the following disclaimer;
|
||||||
|
* redistributions in binary form must reproduce the above copyright
|
||||||
|
* notice, this list of conditions and the following disclaimer in the
|
||||||
|
* documentation and/or other materials provided with the distribution;
|
||||||
|
* neither the name of the copyright holders nor the names of its
|
||||||
|
* contributors may be used to endorse or promote products derived from
|
||||||
|
* this software without specific prior written permission.
|
||||||
|
*
|
||||||
|
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||||
|
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||||
|
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||||
|
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||||
|
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||||
|
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||||
|
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||||
|
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||||
|
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||||
|
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||||
|
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||||
|
*
|
||||||
|
* Authors: Gabe Black
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include <assert.h>
|
||||||
|
#include <string.h>
|
||||||
|
|
||||||
|
#include "arch/alpha/ipr.hh"
|
||||||
|
|
||||||
|
namespace AlphaISA
|
||||||
|
{
|
||||||
|
md_ipr_names MiscRegIndexToIpr[NumInternalProcRegs] =
|
||||||
|
{
|
||||||
|
//Write only
|
||||||
|
IPR_HWINT_CLR, // H/W interrupt clear register
|
||||||
|
IPR_SL_XMIT, // serial line transmit register
|
||||||
|
IPR_DC_FLUSH,
|
||||||
|
IPR_IC_FLUSH, // instruction cache flush control
|
||||||
|
IPR_ALT_MODE, // alternate mode register
|
||||||
|
IPR_DTB_IA, // DTLB invalidate all register
|
||||||
|
IPR_DTB_IAP, // DTLB invalidate all process register
|
||||||
|
IPR_ITB_IA, // ITLB invalidate all register
|
||||||
|
IPR_ITB_IAP, // ITLB invalidate all process register
|
||||||
|
|
||||||
|
//Read only
|
||||||
|
IPR_INTID, // interrupt ID register
|
||||||
|
IPR_SL_RCV, // serial line receive register
|
||||||
|
IPR_MM_STAT, // data MMU fault status register
|
||||||
|
IPR_ITB_PTE_TEMP, // ITLB page table entry temp register
|
||||||
|
IPR_DTB_PTE_TEMP, // DTLB page table entry temporary register
|
||||||
|
|
||||||
|
IPR_ISR, // interrupt summary register
|
||||||
|
IPR_ITB_TAG, // ITLB tag register
|
||||||
|
IPR_ITB_PTE, // ITLB page table entry register
|
||||||
|
IPR_ITB_ASN, // ITLB address space register
|
||||||
|
IPR_ITB_IS, // ITLB invalidate select register
|
||||||
|
IPR_SIRR, // software interrupt request register
|
||||||
|
IPR_ASTRR, // asynchronous system trap request register
|
||||||
|
IPR_ASTER, // asynchronous system trap enable register
|
||||||
|
IPR_EXC_ADDR, // exception address register
|
||||||
|
IPR_EXC_SUM, // exception summary register
|
||||||
|
IPR_EXC_MASK, // exception mask register
|
||||||
|
IPR_PAL_BASE, // PAL base address register
|
||||||
|
IPR_ICM, // instruction current mode
|
||||||
|
IPR_IPLR, // interrupt priority level register
|
||||||
|
IPR_IFAULT_VA_FORM, // formatted faulting virtual addr register
|
||||||
|
IPR_IVPTBR, // virtual page table base register
|
||||||
|
IPR_ICSR, // instruction control and status register
|
||||||
|
IPR_IC_PERR_STAT, // inst cache parity error status register
|
||||||
|
IPR_PMCTR, // performance counter register
|
||||||
|
|
||||||
|
// PAL temporary registers...
|
||||||
|
// register meanings gleaned from osfpal.s source code
|
||||||
|
IPR_PALtemp0, // local scratch
|
||||||
|
IPR_PALtemp1, // local scratch
|
||||||
|
IPR_PALtemp2, // entUna
|
||||||
|
IPR_PALtemp3, // CPU specific impure area pointer
|
||||||
|
IPR_PALtemp4, // memory management temp
|
||||||
|
IPR_PALtemp5, // memory management temp
|
||||||
|
IPR_PALtemp6, // memory management temp
|
||||||
|
IPR_PALtemp7, // entIF
|
||||||
|
IPR_PALtemp8, // intmask
|
||||||
|
IPR_PALtemp9, // entSys
|
||||||
|
IPR_PALtemp10, // ??
|
||||||
|
IPR_PALtemp11, // entInt
|
||||||
|
IPR_PALtemp12, // entArith
|
||||||
|
IPR_PALtemp13, // reserved for platform specific PAL
|
||||||
|
IPR_PALtemp14, // reserved for platform specific PAL
|
||||||
|
IPR_PALtemp15, // reserved for platform specific PAL
|
||||||
|
IPR_PALtemp16, // scratch / whami<7:0> / mces<4:0>
|
||||||
|
IPR_PALtemp17, // sysval
|
||||||
|
IPR_PALtemp18, // usp
|
||||||
|
IPR_PALtemp19, // ksp
|
||||||
|
IPR_PALtemp20, // PTBR
|
||||||
|
IPR_PALtemp21, // entMM
|
||||||
|
IPR_PALtemp22, // kgp
|
||||||
|
IPR_PALtemp23, // PCBB
|
||||||
|
|
||||||
|
IPR_DTB_ASN, // DTLB address space number register
|
||||||
|
IPR_DTB_CM, // DTLB current mode register
|
||||||
|
IPR_DTB_TAG, // DTLB tag register
|
||||||
|
IPR_DTB_PTE, // DTLB page table entry register
|
||||||
|
|
||||||
|
IPR_VA, // fault virtual address register
|
||||||
|
IPR_VA_FORM, // formatted virtual address register
|
||||||
|
IPR_MVPTBR, // MTU virtual page table base register
|
||||||
|
IPR_DTB_IS, // DTLB invalidate single register
|
||||||
|
IPR_CC, // cycle counter register
|
||||||
|
IPR_CC_CTL, // cycle counter control register
|
||||||
|
IPR_MCSR, // MTU control register
|
||||||
|
|
||||||
|
IPR_DC_PERR_STAT, // Dcache parity error status register
|
||||||
|
IPR_DC_TEST_CTL, // Dcache test tag control register
|
||||||
|
IPR_DC_TEST_TAG, // Dcache test tag register
|
||||||
|
IPR_DC_TEST_TAG_TEMP, // Dcache test tag temporary register
|
||||||
|
IPR_DC_MODE, // Dcache mode register
|
||||||
|
IPR_MAF_MODE // miss address file mode register
|
||||||
|
};
|
||||||
|
|
||||||
|
int IprToMiscRegIndex[MaxInternalProcRegs];
|
||||||
|
|
||||||
|
void initializeIprTable()
|
||||||
|
{
|
||||||
|
static bool initialized = false;
|
||||||
|
if(initialized)
|
||||||
|
return;
|
||||||
|
|
||||||
|
memset(IprToMiscRegIndex, -1, MaxInternalProcRegs * sizeof(int));
|
||||||
|
|
||||||
|
for(int x = 0; x < NumInternalProcRegs; x++)
|
||||||
|
IprToMiscRegIndex[MiscRegIndexToIpr[x]] = x;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
228
src/arch/alpha/ipr.hh
Normal file
228
src/arch/alpha/ipr.hh
Normal file
|
|
@ -0,0 +1,228 @@
|
||||||
|
/*
|
||||||
|
* Copyright (c) 2003-2005 The Regents of The University of Michigan
|
||||||
|
* All rights reserved.
|
||||||
|
*
|
||||||
|
* Redistribution and use in source and binary forms, with or without
|
||||||
|
* modification, are permitted provided that the following conditions are
|
||||||
|
* met: redistributions of source code must retain the above copyright
|
||||||
|
* notice, this list of conditions and the following disclaimer;
|
||||||
|
* redistributions in binary form must reproduce the above copyright
|
||||||
|
* notice, this list of conditions and the following disclaimer in the
|
||||||
|
* documentation and/or other materials provided with the distribution;
|
||||||
|
* neither the name of the copyright holders nor the names of its
|
||||||
|
* contributors may be used to endorse or promote products derived from
|
||||||
|
* this software without specific prior written permission.
|
||||||
|
*
|
||||||
|
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||||
|
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||||
|
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||||
|
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||||
|
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||||
|
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||||
|
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||||
|
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||||
|
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||||
|
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||||
|
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||||
|
*
|
||||||
|
* Authors: Steve Reinhardt
|
||||||
|
* Gabe Black
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef __ARCH_ALPHA_IPR_HH__
|
||||||
|
#define __ARCH_ALPHA_IPR_HH__
|
||||||
|
|
||||||
|
namespace AlphaISA
|
||||||
|
{
|
||||||
|
////////////////////////////////////////////////////////////////////////
|
||||||
|
//
|
||||||
|
// Internal Processor Reigsters
|
||||||
|
//
|
||||||
|
enum md_ipr_names
|
||||||
|
{
|
||||||
|
IPR_ISR = 0x100, // interrupt summary register
|
||||||
|
IPR_ITB_TAG = 0x101, // ITLB tag register
|
||||||
|
IPR_ITB_PTE = 0x102, // ITLB page table entry register
|
||||||
|
IPR_ITB_ASN = 0x103, // ITLB address space register
|
||||||
|
IPR_ITB_PTE_TEMP = 0x104, // ITLB page table entry temp register
|
||||||
|
IPR_ITB_IA = 0x105, // ITLB invalidate all register
|
||||||
|
IPR_ITB_IAP = 0x106, // ITLB invalidate all process register
|
||||||
|
IPR_ITB_IS = 0x107, // ITLB invalidate select register
|
||||||
|
IPR_SIRR = 0x108, // software interrupt request register
|
||||||
|
IPR_ASTRR = 0x109, // asynchronous system trap request register
|
||||||
|
IPR_ASTER = 0x10a, // asynchronous system trap enable register
|
||||||
|
IPR_EXC_ADDR = 0x10b, // exception address register
|
||||||
|
IPR_EXC_SUM = 0x10c, // exception summary register
|
||||||
|
IPR_EXC_MASK = 0x10d, // exception mask register
|
||||||
|
IPR_PAL_BASE = 0x10e, // PAL base address register
|
||||||
|
IPR_ICM = 0x10f, // instruction current mode
|
||||||
|
IPR_IPLR = 0x110, // interrupt priority level register
|
||||||
|
IPR_INTID = 0x111, // interrupt ID register
|
||||||
|
IPR_IFAULT_VA_FORM = 0x112, // formatted faulting virtual addr register
|
||||||
|
IPR_IVPTBR = 0x113, // virtual page table base register
|
||||||
|
IPR_HWINT_CLR = 0x115, // H/W interrupt clear register
|
||||||
|
IPR_SL_XMIT = 0x116, // serial line transmit register
|
||||||
|
IPR_SL_RCV = 0x117, // serial line receive register
|
||||||
|
IPR_ICSR = 0x118, // instruction control and status register
|
||||||
|
IPR_IC_FLUSH = 0x119, // instruction cache flush control
|
||||||
|
IPR_IC_PERR_STAT = 0x11a, // inst cache parity error status register
|
||||||
|
IPR_PMCTR = 0x11c, // performance counter register
|
||||||
|
|
||||||
|
// PAL temporary registers...
|
||||||
|
// register meanings gleaned from osfpal.s source code
|
||||||
|
IPR_PALtemp0 = 0x140, // local scratch
|
||||||
|
IPR_PALtemp1 = 0x141, // local scratch
|
||||||
|
IPR_PALtemp2 = 0x142, // entUna
|
||||||
|
IPR_PALtemp3 = 0x143, // CPU specific impure area pointer
|
||||||
|
IPR_PALtemp4 = 0x144, // memory management temp
|
||||||
|
IPR_PALtemp5 = 0x145, // memory management temp
|
||||||
|
IPR_PALtemp6 = 0x146, // memory management temp
|
||||||
|
IPR_PALtemp7 = 0x147, // entIF
|
||||||
|
IPR_PALtemp8 = 0x148, // intmask
|
||||||
|
IPR_PALtemp9 = 0x149, // entSys
|
||||||
|
IPR_PALtemp10 = 0x14a, // ??
|
||||||
|
IPR_PALtemp11 = 0x14b, // entInt
|
||||||
|
IPR_PALtemp12 = 0x14c, // entArith
|
||||||
|
IPR_PALtemp13 = 0x14d, // reserved for platform specific PAL
|
||||||
|
IPR_PALtemp14 = 0x14e, // reserved for platform specific PAL
|
||||||
|
IPR_PALtemp15 = 0x14f, // reserved for platform specific PAL
|
||||||
|
IPR_PALtemp16 = 0x150, // scratch / whami<7:0> / mces<4:0>
|
||||||
|
IPR_PALtemp17 = 0x151, // sysval
|
||||||
|
IPR_PALtemp18 = 0x152, // usp
|
||||||
|
IPR_PALtemp19 = 0x153, // ksp
|
||||||
|
IPR_PALtemp20 = 0x154, // PTBR
|
||||||
|
IPR_PALtemp21 = 0x155, // entMM
|
||||||
|
IPR_PALtemp22 = 0x156, // kgp
|
||||||
|
IPR_PALtemp23 = 0x157, // PCBB
|
||||||
|
|
||||||
|
IPR_DTB_ASN = 0x200, // DTLB address space number register
|
||||||
|
IPR_DTB_CM = 0x201, // DTLB current mode register
|
||||||
|
IPR_DTB_TAG = 0x202, // DTLB tag register
|
||||||
|
IPR_DTB_PTE = 0x203, // DTLB page table entry register
|
||||||
|
IPR_DTB_PTE_TEMP = 0x204, // DTLB page table entry temporary register
|
||||||
|
|
||||||
|
IPR_MM_STAT = 0x205, // data MMU fault status register
|
||||||
|
IPR_VA = 0x206, // fault virtual address register
|
||||||
|
IPR_VA_FORM = 0x207, // formatted virtual address register
|
||||||
|
IPR_MVPTBR = 0x208, // MTU virtual page table base register
|
||||||
|
IPR_DTB_IAP = 0x209, // DTLB invalidate all process register
|
||||||
|
IPR_DTB_IA = 0x20a, // DTLB invalidate all register
|
||||||
|
IPR_DTB_IS = 0x20b, // DTLB invalidate single register
|
||||||
|
IPR_ALT_MODE = 0x20c, // alternate mode register
|
||||||
|
IPR_CC = 0x20d, // cycle counter register
|
||||||
|
IPR_CC_CTL = 0x20e, // cycle counter control register
|
||||||
|
IPR_MCSR = 0x20f, // MTU control register
|
||||||
|
|
||||||
|
IPR_DC_FLUSH = 0x210,
|
||||||
|
IPR_DC_PERR_STAT = 0x212, // Dcache parity error status register
|
||||||
|
IPR_DC_TEST_CTL = 0x213, // Dcache test tag control register
|
||||||
|
IPR_DC_TEST_TAG = 0x214, // Dcache test tag register
|
||||||
|
IPR_DC_TEST_TAG_TEMP = 0x215, // Dcache test tag temporary register
|
||||||
|
IPR_DC_MODE = 0x216, // Dcache mode register
|
||||||
|
IPR_MAF_MODE = 0x217, // miss address file mode register
|
||||||
|
|
||||||
|
MaxInternalProcRegs // number of IPR registers
|
||||||
|
};
|
||||||
|
|
||||||
|
enum MiscRegIpr
|
||||||
|
{
|
||||||
|
//Write only
|
||||||
|
MinWriteOnlyIpr,
|
||||||
|
MISCREG_IPR_HWINT_CLR = MinWriteOnlyIpr,
|
||||||
|
MISCREG_IPR_SL_XMIT,
|
||||||
|
MISCREG_IPR_DC_FLUSH,
|
||||||
|
MISCREG_IPR_IC_FLUSH,
|
||||||
|
MISCREG_IPR_ALT_MODE,
|
||||||
|
MISCREG_IPR_DTB_IA,
|
||||||
|
MISCREG_IPR_DTB_IAP,
|
||||||
|
MISCREG_IPR_ITB_IA,
|
||||||
|
MaxWriteOnlyIpr,
|
||||||
|
MISCREG_IPR_ITB_IAP = MaxWriteOnlyIpr,
|
||||||
|
|
||||||
|
//Read only
|
||||||
|
MinReadOnlyIpr,
|
||||||
|
MISCREG_IPR_INTID = MinReadOnlyIpr,
|
||||||
|
MISCREG_IPR_SL_RCV,
|
||||||
|
MISCREG_IPR_MM_STAT,
|
||||||
|
MISCREG_IPR_ITB_PTE_TEMP,
|
||||||
|
MaxReadOnlyIpr,
|
||||||
|
MISCREG_IPR_DTB_PTE_TEMP = MaxReadOnlyIpr,
|
||||||
|
|
||||||
|
MISCREG_IPR_ISR,
|
||||||
|
MISCREG_IPR_ITB_TAG,
|
||||||
|
MISCREG_IPR_ITB_PTE,
|
||||||
|
MISCREG_IPR_ITB_ASN,
|
||||||
|
MISCREG_IPR_ITB_IS,
|
||||||
|
MISCREG_IPR_SIRR,
|
||||||
|
MISCREG_IPR_ASTRR,
|
||||||
|
MISCREG_IPR_ASTER,
|
||||||
|
MISCREG_IPR_EXC_ADDR,
|
||||||
|
MISCREG_IPR_EXC_SUM,
|
||||||
|
MISCREG_IPR_EXC_MASK,
|
||||||
|
MISCREG_IPR_PAL_BASE,
|
||||||
|
MISCREG_IPR_ICM,
|
||||||
|
MISCREG_IPR_IPLR,
|
||||||
|
MISCREG_IPR_IFAULT_VA_FORM,
|
||||||
|
MISCREG_IPR_IVPTBR,
|
||||||
|
MISCREG_IPR_ICSR,
|
||||||
|
MISCREG_IPR_IC_PERR_STAT,
|
||||||
|
MISCREG_IPR_PMCTR,
|
||||||
|
|
||||||
|
// PAL temporary registers...
|
||||||
|
// register meanings gleaned from osfpal.s source code
|
||||||
|
MISCREG_IPR_PALtemp0,
|
||||||
|
MISCREG_IPR_PALtemp1,
|
||||||
|
MISCREG_IPR_PALtemp2,
|
||||||
|
MISCREG_IPR_PALtemp3,
|
||||||
|
MISCREG_IPR_PALtemp4,
|
||||||
|
MISCREG_IPR_PALtemp5,
|
||||||
|
MISCREG_IPR_PALtemp6,
|
||||||
|
MISCREG_IPR_PALtemp7,
|
||||||
|
MISCREG_IPR_PALtemp8,
|
||||||
|
MISCREG_IPR_PALtemp9,
|
||||||
|
MISCREG_IPR_PALtemp10,
|
||||||
|
MISCREG_IPR_PALtemp11,
|
||||||
|
MISCREG_IPR_PALtemp12,
|
||||||
|
MISCREG_IPR_PALtemp13,
|
||||||
|
MISCREG_IPR_PALtemp14,
|
||||||
|
MISCREG_IPR_PALtemp15,
|
||||||
|
MISCREG_IPR_PALtemp16,
|
||||||
|
MISCREG_IPR_PALtemp17,
|
||||||
|
MISCREG_IPR_PALtemp18,
|
||||||
|
MISCREG_IPR_PALtemp19,
|
||||||
|
MISCREG_IPR_PALtemp20,
|
||||||
|
MISCREG_IPR_PALtemp21,
|
||||||
|
MISCREG_IPR_PALtemp22,
|
||||||
|
MISCREG_IPR_PALtemp23,
|
||||||
|
|
||||||
|
MISCREG_IPR_DTB_ASN,
|
||||||
|
MISCREG_IPR_DTB_CM,
|
||||||
|
MISCREG_IPR_DTB_TAG,
|
||||||
|
MISCREG_IPR_DTB_PTE,
|
||||||
|
|
||||||
|
MISCREG_IPR_VA,
|
||||||
|
MISCREG_IPR_VA_FORM,
|
||||||
|
MISCREG_IPR_MVPTBR,
|
||||||
|
MISCREG_IPR_DTB_IS,
|
||||||
|
MISCREG_IPR_CC,
|
||||||
|
MISCREG_IPR_CC_CTL,
|
||||||
|
MISCREG_IPR_MCSR,
|
||||||
|
|
||||||
|
MISCREG_IPR_DC_PERR_STAT,
|
||||||
|
MISCREG_IPR_DC_TEST_CTL,
|
||||||
|
MISCREG_IPR_DC_TEST_TAG,
|
||||||
|
MISCREG_IPR_DC_TEST_TAG_TEMP,
|
||||||
|
MISCREG_IPR_DC_MODE,
|
||||||
|
MISCREG_IPR_MAF_MODE,
|
||||||
|
|
||||||
|
NumInternalProcRegs // number of IPR registers
|
||||||
|
};
|
||||||
|
|
||||||
|
|
||||||
|
extern md_ipr_names MiscRegIndexToIpr[NumInternalProcRegs];
|
||||||
|
extern int IprToMiscRegIndex[MaxInternalProcRegs];
|
||||||
|
|
||||||
|
void initializeIprTable();
|
||||||
|
}
|
||||||
|
|
||||||
|
#endif
|
||||||
|
|
@ -745,7 +745,13 @@ decode OPCODE default Unknown::unknown() {
|
||||||
0: OpcdecFault::hw_mfpr();
|
0: OpcdecFault::hw_mfpr();
|
||||||
format HwMoveIPR {
|
format HwMoveIPR {
|
||||||
1: hw_mfpr({{
|
1: hw_mfpr({{
|
||||||
Ra = xc->readMiscRegWithEffect(ipr_index, fault);
|
int miscRegIndex = IprToMiscRegIndex[ipr_index];
|
||||||
|
if(miscRegIndex < 0 ||
|
||||||
|
(miscRegIndex >= MinWriteOnlyIpr &&
|
||||||
|
miscRegIndex <= MaxWriteOnlyIpr))
|
||||||
|
fault = new UnimplementedOpcodeFault;
|
||||||
|
else
|
||||||
|
Ra = xc->readMiscRegWithEffect(ipr_index, fault);
|
||||||
}}, IsIprAccess);
|
}}, IsIprAccess);
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
@ -754,7 +760,13 @@ decode OPCODE default Unknown::unknown() {
|
||||||
0: OpcdecFault::hw_mtpr();
|
0: OpcdecFault::hw_mtpr();
|
||||||
format HwMoveIPR {
|
format HwMoveIPR {
|
||||||
1: hw_mtpr({{
|
1: hw_mtpr({{
|
||||||
xc->setMiscRegWithEffect(ipr_index, Ra);
|
int miscRegIndex = IprToMiscRegIndex[ipr_index];
|
||||||
|
if(miscRegIndex < 0 ||
|
||||||
|
(miscRegIndex >= MinReadOnlyIpr &&
|
||||||
|
miscRegIndex <= MaxWriteOnlyIpr))
|
||||||
|
fault = new UnimplementedOpcodeFault;
|
||||||
|
else
|
||||||
|
xc->setMiscRegWithEffect(ipr_index, Ra);
|
||||||
if (traceData) { traceData->setData(Ra); }
|
if (traceData) { traceData->setData(Ra); }
|
||||||
}}, IsIprAccess);
|
}}, IsIprAccess);
|
||||||
}
|
}
|
||||||
|
|
|
||||||
|
|
@ -71,6 +71,7 @@ output exec {{
|
||||||
#if FULL_SYSTEM
|
#if FULL_SYSTEM
|
||||||
#include "sim/pseudo_inst.hh"
|
#include "sim/pseudo_inst.hh"
|
||||||
#endif
|
#endif
|
||||||
|
#include "arch/alpha/ipr.hh"
|
||||||
#include "base/fenv.hh"
|
#include "base/fenv.hh"
|
||||||
#include "config/ss_compatible_fp.hh"
|
#include "config/ss_compatible_fp.hh"
|
||||||
#include "cpu/base.hh"
|
#include "cpu/base.hh"
|
||||||
|
|
|
||||||
|
|
@ -34,6 +34,7 @@
|
||||||
|
|
||||||
namespace LittleEndianGuest {}
|
namespace LittleEndianGuest {}
|
||||||
|
|
||||||
|
#include "arch/alpha/ipr.hh"
|
||||||
#include "arch/alpha/types.hh"
|
#include "arch/alpha/types.hh"
|
||||||
#include "config/full_system.hh"
|
#include "config/full_system.hh"
|
||||||
#include "sim/host.hh"
|
#include "sim/host.hh"
|
||||||
|
|
@ -132,100 +133,6 @@ namespace AlphaISA
|
||||||
|
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
#if FULL_SYSTEM
|
|
||||||
////////////////////////////////////////////////////////////////////////
|
|
||||||
//
|
|
||||||
// Internal Processor Reigsters
|
|
||||||
//
|
|
||||||
enum md_ipr_names
|
|
||||||
{
|
|
||||||
IPR_ISR = 0x100, // interrupt summary register
|
|
||||||
IPR_ITB_TAG = 0x101, // ITLB tag register
|
|
||||||
IPR_ITB_PTE = 0x102, // ITLB page table entry register
|
|
||||||
IPR_ITB_ASN = 0x103, // ITLB address space register
|
|
||||||
IPR_ITB_PTE_TEMP = 0x104, // ITLB page table entry temp register
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||||||
IPR_ITB_IA = 0x105, // ITLB invalidate all register
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||||||
IPR_ITB_IAP = 0x106, // ITLB invalidate all process register
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||||||
IPR_ITB_IS = 0x107, // ITLB invalidate select register
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|
||||||
IPR_SIRR = 0x108, // software interrupt request register
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||||||
IPR_ASTRR = 0x109, // asynchronous system trap request register
|
|
||||||
IPR_ASTER = 0x10a, // asynchronous system trap enable register
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|
||||||
IPR_EXC_ADDR = 0x10b, // exception address register
|
|
||||||
IPR_EXC_SUM = 0x10c, // exception summary register
|
|
||||||
IPR_EXC_MASK = 0x10d, // exception mask register
|
|
||||||
IPR_PAL_BASE = 0x10e, // PAL base address register
|
|
||||||
IPR_ICM = 0x10f, // instruction current mode
|
|
||||||
IPR_IPLR = 0x110, // interrupt priority level register
|
|
||||||
IPR_INTID = 0x111, // interrupt ID register
|
|
||||||
IPR_IFAULT_VA_FORM = 0x112, // formatted faulting virtual addr register
|
|
||||||
IPR_IVPTBR = 0x113, // virtual page table base register
|
|
||||||
IPR_HWINT_CLR = 0x115, // H/W interrupt clear register
|
|
||||||
IPR_SL_XMIT = 0x116, // serial line transmit register
|
|
||||||
IPR_SL_RCV = 0x117, // serial line receive register
|
|
||||||
IPR_ICSR = 0x118, // instruction control and status register
|
|
||||||
IPR_IC_FLUSH = 0x119, // instruction cache flush control
|
|
||||||
IPR_IC_PERR_STAT = 0x11a, // inst cache parity error status register
|
|
||||||
IPR_PMCTR = 0x11c, // performance counter register
|
|
||||||
|
|
||||||
// PAL temporary registers...
|
|
||||||
// register meanings gleaned from osfpal.s source code
|
|
||||||
IPR_PALtemp0 = 0x140, // local scratch
|
|
||||||
IPR_PALtemp1 = 0x141, // local scratch
|
|
||||||
IPR_PALtemp2 = 0x142, // entUna
|
|
||||||
IPR_PALtemp3 = 0x143, // CPU specific impure area pointer
|
|
||||||
IPR_PALtemp4 = 0x144, // memory management temp
|
|
||||||
IPR_PALtemp5 = 0x145, // memory management temp
|
|
||||||
IPR_PALtemp6 = 0x146, // memory management temp
|
|
||||||
IPR_PALtemp7 = 0x147, // entIF
|
|
||||||
IPR_PALtemp8 = 0x148, // intmask
|
|
||||||
IPR_PALtemp9 = 0x149, // entSys
|
|
||||||
IPR_PALtemp10 = 0x14a, // ??
|
|
||||||
IPR_PALtemp11 = 0x14b, // entInt
|
|
||||||
IPR_PALtemp12 = 0x14c, // entArith
|
|
||||||
IPR_PALtemp13 = 0x14d, // reserved for platform specific PAL
|
|
||||||
IPR_PALtemp14 = 0x14e, // reserved for platform specific PAL
|
|
||||||
IPR_PALtemp15 = 0x14f, // reserved for platform specific PAL
|
|
||||||
IPR_PALtemp16 = 0x150, // scratch / whami<7:0> / mces<4:0>
|
|
||||||
IPR_PALtemp17 = 0x151, // sysval
|
|
||||||
IPR_PALtemp18 = 0x152, // usp
|
|
||||||
IPR_PALtemp19 = 0x153, // ksp
|
|
||||||
IPR_PALtemp20 = 0x154, // PTBR
|
|
||||||
IPR_PALtemp21 = 0x155, // entMM
|
|
||||||
IPR_PALtemp22 = 0x156, // kgp
|
|
||||||
IPR_PALtemp23 = 0x157, // PCBB
|
|
||||||
|
|
||||||
IPR_DTB_ASN = 0x200, // DTLB address space number register
|
|
||||||
IPR_DTB_CM = 0x201, // DTLB current mode register
|
|
||||||
IPR_DTB_TAG = 0x202, // DTLB tag register
|
|
||||||
IPR_DTB_PTE = 0x203, // DTLB page table entry register
|
|
||||||
IPR_DTB_PTE_TEMP = 0x204, // DTLB page table entry temporary register
|
|
||||||
|
|
||||||
IPR_MM_STAT = 0x205, // data MMU fault status register
|
|
||||||
IPR_VA = 0x206, // fault virtual address register
|
|
||||||
IPR_VA_FORM = 0x207, // formatted virtual address register
|
|
||||||
IPR_MVPTBR = 0x208, // MTU virtual page table base register
|
|
||||||
IPR_DTB_IAP = 0x209, // DTLB invalidate all process register
|
|
||||||
IPR_DTB_IA = 0x20a, // DTLB invalidate all register
|
|
||||||
IPR_DTB_IS = 0x20b, // DTLB invalidate single register
|
|
||||||
IPR_ALT_MODE = 0x20c, // alternate mode register
|
|
||||||
IPR_CC = 0x20d, // cycle counter register
|
|
||||||
IPR_CC_CTL = 0x20e, // cycle counter control register
|
|
||||||
IPR_MCSR = 0x20f, // MTU control register
|
|
||||||
|
|
||||||
IPR_DC_FLUSH = 0x210,
|
|
||||||
IPR_DC_PERR_STAT = 0x212, // Dcache parity error status register
|
|
||||||
IPR_DC_TEST_CTL = 0x213, // Dcache test tag control register
|
|
||||||
IPR_DC_TEST_TAG = 0x214, // Dcache test tag register
|
|
||||||
IPR_DC_TEST_TAG_TEMP = 0x215, // Dcache test tag temporary register
|
|
||||||
IPR_DC_MODE = 0x216, // Dcache mode register
|
|
||||||
IPR_MAF_MODE = 0x217, // miss address file mode register
|
|
||||||
|
|
||||||
NumInternalProcRegs // number of IPR registers
|
|
||||||
};
|
|
||||||
#else
|
|
||||||
const int NumInternalProcRegs = 0;
|
|
||||||
#endif
|
|
||||||
|
|
||||||
// Constants Related to the number of registers
|
// Constants Related to the number of registers
|
||||||
|
|
||||||
const int NumIntArchRegs = 32;
|
const int NumIntArchRegs = 32;
|
||||||
|
|
|
||||||
|
|
@ -31,8 +31,9 @@
|
||||||
#ifndef __ARCH_ALPHA_REGFILE_HH__
|
#ifndef __ARCH_ALPHA_REGFILE_HH__
|
||||||
#define __ARCH_ALPHA_REGFILE_HH__
|
#define __ARCH_ALPHA_REGFILE_HH__
|
||||||
|
|
||||||
#include "arch/alpha/types.hh"
|
|
||||||
#include "arch/alpha/isa_traits.hh"
|
#include "arch/alpha/isa_traits.hh"
|
||||||
|
#include "arch/alpha/ipr.hh"
|
||||||
|
#include "arch/alpha/types.hh"
|
||||||
#include "sim/faults.hh"
|
#include "sim/faults.hh"
|
||||||
|
|
||||||
#include <string>
|
#include <string>
|
||||||
|
|
@ -112,6 +113,11 @@ namespace AlphaISA
|
||||||
int intr_flag;
|
int intr_flag;
|
||||||
|
|
||||||
public:
|
public:
|
||||||
|
MiscRegFile()
|
||||||
|
{
|
||||||
|
initializeIprTable();
|
||||||
|
}
|
||||||
|
|
||||||
MiscReg readReg(int misc_reg);
|
MiscReg readReg(int misc_reg);
|
||||||
|
|
||||||
MiscReg readRegWithEffect(int misc_reg, Fault &fault,
|
MiscReg readRegWithEffect(int misc_reg, Fault &fault,
|
||||||
|
|
|
||||||
Loading…
Reference in a new issue