From ecbb8debf672ee1463115319a24384eeb6b98ee3 Mon Sep 17 00:00:00 2001 From: Ali Saidi Date: Wed, 6 Dec 2006 14:29:10 -0500 Subject: [PATCH] Many more fixes for SPARC_FS. Gets us to the point where SOFTINT starts getting touched. configs/common/FSConfig.py: Physical memory on the T1 starts at 1MB, The first megabyte is unmapped to catch bugs src/arch/isa_parser.py: we should readmiscregwitheffect not readmiscreg src/arch/sparc/asi.cc: Fix AsiIsNucleus spelling with respect to header file Add ASI_LSU_CONTROL_REG to AsiSiMmu src/arch/sparc/asi.hh: Fix spelling of two ASIs src/arch/sparc/isa/decoder.isa: switch back to defaults letting the isa_parser insert readMiscRegWithEffect src/arch/sparc/isa/formats/mem/util.isa: Flesh out priviledgedString with hypervisor checks Make load alternate set the flags correctly src/arch/sparc/miscregfile.cc: insert some forgotten break statements src/arch/sparc/miscregfile.hh: Add some comments to make it easier to find which misc register is which number src/arch/sparc/tlb.cc: flesh out the tlb memory mapped registers a lot more src/base/traceflags.py: add an IPR traceflag src/mem/request.hh: Fix a bad assert() in request --HG-- extra : convert_revision : 1e11aa004e8f42c156e224c1d30d49479ebeed28 --- configs/common/FSConfig.py | 2 +- src/arch/isa_parser.py | 2 +- src/arch/sparc/asi.cc | 3 +- src/arch/sparc/asi.hh | 4 +- src/arch/sparc/isa/decoder.isa | 42 ++--- src/arch/sparc/isa/formats/mem/util.isa | 9 +- src/arch/sparc/miscregfile.cc | 13 +- src/arch/sparc/miscregfile.hh | 14 +- src/arch/sparc/tlb.cc | 195 +++++++++++++++++++++++- src/base/traceflags.py | 1 + src/mem/request.hh | 2 +- 11 files changed, 233 insertions(+), 54 deletions(-) diff --git a/configs/common/FSConfig.py b/configs/common/FSConfig.py index eb74346c8..72742775f 100644 --- a/configs/common/FSConfig.py +++ b/configs/common/FSConfig.py @@ -89,7 +89,7 @@ def makeSparcSystem(mem_mode, mdesc = None): self.bridge = Bridge() self.t1000 = T1000() self.t1000.attachIO(self.iobus) - self.physmem = PhysicalMemory(range = AddrRange('64MB'), zero = True) + self.physmem = PhysicalMemory(range = AddrRange(Addr('1MB'), size = '64MB'), zero = True) self.physmem2 = PhysicalMemory(range = AddrRange(Addr('2GB'), size ='256MB'), zero = True) self.bridge.side_a = self.iobus.port self.bridge.side_b = self.membus.port diff --git a/src/arch/isa_parser.py b/src/arch/isa_parser.py index 6504c7b32..2086473d6 100755 --- a/src/arch/isa_parser.py +++ b/src/arch/isa_parser.py @@ -1306,7 +1306,7 @@ class ControlRegOperand(Operand): bit_select = 0 if (self.ctype == 'float' or self.ctype == 'double'): error(0, 'Attempt to read control register as FP') - base = 'xc->readMiscReg(%s)' % self.reg_spec + base = 'xc->readMiscRegWithEffect(%s)' % self.reg_spec if self.size == self.dflt_size: return '%s = %s;\n' % (self.base_name, base) else: diff --git a/src/arch/sparc/asi.cc b/src/arch/sparc/asi.cc index 14e581e43..c8f2c1366 100644 --- a/src/arch/sparc/asi.cc +++ b/src/arch/sparc/asi.cc @@ -104,7 +104,7 @@ namespace SparcISA (asi == ASI_BLK_SL); } - bool AsiNucleus(ASI asi) + bool AsiIsNucleus(ASI asi) { return (asi == ASI_N) || @@ -259,6 +259,7 @@ namespace SparcISA bool AsiIsMmu(ASI asi) { return asi == ASI_MMU || + asi == ASI_LSU_CONTROL_REG || (asi >= ASI_DMMU_CTXT_ZERO_TSB_BASE_PS0 && asi <= ASI_IMMU_CTXT_ZERO_CONFIG) || (asi >= ASI_DMMU_CTXT_NONZERO_TSB_BASE_PS0 && diff --git a/src/arch/sparc/asi.hh b/src/arch/sparc/asi.hh index a0d667cf3..e683605e8 100644 --- a/src/arch/sparc/asi.hh +++ b/src/arch/sparc/asi.hh @@ -108,11 +108,11 @@ namespace SparcISA ASI_IMMU_CTXT_ZERO_CONFIG = 0x37, //0x38 implementation dependent ASI_DMMU_CTXT_NONZERO_TSB_BASE_PS0 = 0x39, - ASI_DMMU_CTXT_NONZERO_USB_BASE_PS1 = 0x3A, + ASI_DMMU_CTXT_NONZERO_TSB_BASE_PS1 = 0x3A, ASI_DMMU_CTXT_NONZERO_CONFIG = 0x3B, //0x3C implementation dependent ASI_IMMU_CTXT_NONZERO_TSB_BASE_PS0 = 0x3D, - ASI_IMMU_CTXT_NONZERO_USB_BASE_PS1 = 0x3E, + ASI_IMMU_CTXT_NONZERO_TSB_BASE_PS1 = 0x3E, ASI_IMMU_CTXT_NONZERO_CONFIG = 0x3F, ASI_STREAM_MA = 0x40, //0x41 implementation dependent diff --git a/src/arch/sparc/isa/decoder.isa b/src/arch/sparc/isa/decoder.isa index 781958c77..a355816ac 100644 --- a/src/arch/sparc/isa/decoder.isa +++ b/src/arch/sparc/isa/decoder.isa @@ -377,9 +377,7 @@ decode OP default Unknown::unknown() //1 should cause an illegal instruction exception 0x02: NoPriv::rdccr({{Rd = Ccr;}}); 0x03: NoPriv::rdasi({{Rd = Asi;}}); - 0x04: PrivCheck::rdtick( - {{ Rd = xc->readMiscRegWithEffect(MISCREG_TICK);}}, - {{Tick<63:>}}); + 0x04: PrivCheck::rdtick({{Rd = Tick;}}, {{Tick<63:>}}); 0x05: NoPriv::rdpc({{ if(Pstate<3:>) Rd = (xc->readPC())<31:0>; @@ -405,15 +403,9 @@ decode OP default Unknown::unknown() }}); //0x14-0x15 should cause an illegal instruction exception 0x16: Priv::rdsoftint({{Rd = Softint;}}); - 0x17: Priv::rdtick_cmpr({{ - Rd = xc->readMiscRegWithEffect(MISCREG_TICK_CMPR); - }}); - 0x18: PrivCheck::rdstick({{ - Rd = xc->readMiscRegWithEffect(MISCREG_STICK); - }}, {{Stick<63:>}}); - 0x19: Priv::rdstick_cmpr({{ - Rd = xc->readMiscRegWithEffect(MISCREG_STICK_CMPR); - }}); + 0x17: Priv::rdtick_cmpr({{Rd = TickCmpr;}}); + 0x18: PrivCheck::rdstick({{Rd = Stick}}, {{Stick<63:>}}); + 0x19: Priv::rdstick_cmpr({{Rd = StickCmpr;}}); 0x1A: Priv::rdstrand_sts_reg({{ if(Pstate<2:> && !Hpstate<2:>) Rd = StrandStsReg<0:>; @@ -437,9 +429,7 @@ decode OP default Unknown::unknown() 0x05: HPriv::rdhprhtba({{Rd = Htba;}}); 0x06: HPriv::rdhprhver({{Rd = Hver;}}); //0x07-0x1E should cause an illegal instruction exception - 0x1F: HPriv::rdhprhstick_cmpr({{ - Rd = xc->readMiscRegWithEffect(MISCREG_HSTICK_CMPR); - }}); + 0x1F: HPriv::rdhprhstick_cmpr({{Rd = HstickCmpr;}}); } 0x2A: decode RS1 { 0x00: Priv::rdprtpc({{ @@ -462,9 +452,7 @@ decode OP default Unknown::unknown() return new IllegalInstruction; Rd = Tt; }}); - 0x04: Priv::rdprtick({{ - Rd = xc->readMiscRegWithEffect(MISCREG_TICK); - }}); + 0x04: Priv::rdprtick({{Rd = Tick;}}); 0x05: Priv::rdprtba({{Rd = Tba;}}); 0x06: Priv::rdprpstate({{Rd = Pstate;}}); 0x07: Priv::rdprtl({{Rd = Tl;}}); @@ -554,17 +542,13 @@ decode OP default Unknown::unknown() 0x14: Priv::wrsoftint_set({{SoftintSet = Rs1 ^ Rs2_or_imm13;}}); 0x15: Priv::wrsoftint_clr({{SoftintClr = Rs1 ^ Rs2_or_imm13;}}); 0x16: Priv::wrsoftint({{Softint = Rs1 ^ Rs2_or_imm13;}}); - 0x17: Priv::wrtick_cmpr({{ - xc->setMiscRegWithEffect(MISCREG_TICK_CMPR, Rs1 ^ Rs2_or_imm13); - }}); + 0x17: Priv::wrtick_cmpr({{TickCmpr = Rs1 ^ Rs2_or_imm13;}}); 0x18: NoPriv::wrstick({{ if(!Hpstate<2:>) return new IllegalInstruction; - xc->setMiscRegWithEffect(MISCREG_STICK, Rs1 ^ Rs2_or_imm13); - }}); - 0x19: Priv::wrstick_cmpr({{ - xc->setMiscRegWithEffect(MISCREG_STICK_CMPR, Rs1 ^ Rs2_or_imm13); + Stick = Rs1 ^ Rs2_or_imm13; }}); + 0x19: Priv::wrstick_cmpr({{StickCmpr = Rs1 ^ Rs2_or_imm13;}}); 0x1A: Priv::wrstrand_sts_reg({{ if(Pstate<2:> && !Hpstate<2:>) StrandStsReg = StrandStsReg<63:1> | @@ -621,9 +605,7 @@ decode OP default Unknown::unknown() else Tt = Rs1 ^ Rs2_or_imm13; }}); - 0x04: HPriv::wrprtick({{ - xc->setMiscRegWithEffect(MISCREG_TICK, Rs1 ^ Rs2_or_imm13); - }}); + 0x04: HPriv::wrprtick({{Tick = Rs1 ^ Rs2_or_imm13;}}); 0x05: Priv::wrprtba({{Tba = Rs1 ^ Rs2_or_imm13;}}); 0x06: Priv::wrprpstate({{Pstate = Rs1 ^ Rs2_or_imm13;}}); 0x07: Priv::wrprtl({{ @@ -660,9 +642,7 @@ decode OP default Unknown::unknown() //0x04 should cause an illegal instruction exception 0x05: HPriv::wrhprhtba({{Htba = Rs1 ^ Rs2_or_imm13;}}); //0x06-0x01D should cause an illegal instruction exception - 0x1F: HPriv::wrhprhstick_cmpr({{ - xc->setMiscRegWithEffect(MISCREG_HSTICK_CMPR, Rs1 ^ Rs2_or_imm13); - }}); + 0x1F: HPriv::wrhprhstick_cmpr({{HstickCmpr = Rs1 ^ Rs2_or_imm13;}}); } 0x34: decode OPF{ format BasicOperate{ diff --git a/src/arch/sparc/isa/formats/mem/util.isa b/src/arch/sparc/isa/formats/mem/util.isa index 3c9d33cda..3e9fd7a7d 100644 --- a/src/arch/sparc/isa/formats/mem/util.isa +++ b/src/arch/sparc/isa/formats/mem/util.isa @@ -148,7 +148,7 @@ def template LoadExecute {{ %(fault_check)s; if(fault == NoFault) { - fault = xc->read(EA, (uint%(mem_acc_size)s_t&)Mem, 0); + fault = xc->read(EA, (uint%(mem_acc_size)s_t&)Mem, %(asi_val)s); } if(fault == NoFault) { @@ -175,7 +175,7 @@ def template LoadExecute {{ %(fault_check)s; if(fault == NoFault) { - fault = xc->read(EA, (uint%(mem_acc_size)s_t&)Mem, 0); + fault = xc->read(EA, (uint%(mem_acc_size)s_t&)Mem, %(asi_val)s); } return fault; } @@ -288,8 +288,9 @@ let {{ # are split into ones that are available in priv and hpriv, and # those that are only available in hpriv AlternateASIPrivFaultCheck = ''' - if(bits(Pstate,2,2) == 0 && (EXT_ASI & 0x80) == 0) - fault = new PrivilegedAction; + if(!bits(Pstate,2,2) && !bits(Hpstate,2,2) && !AsiIsUnPriv((ASI)EXT_ASI) || + !bits(Hpstate,2,2) && AsiIsHPriv((ASI)EXT_ASI)) + fault = new PrivilegedAction; else if(AsiIsAsIfUser((ASI)EXT_ASI) && !bits(Pstate,2,2)) fault = new PrivilegedAction; ''' diff --git a/src/arch/sparc/miscregfile.cc b/src/arch/sparc/miscregfile.cc index 67690bdb3..8f2bcf4ae 100644 --- a/src/arch/sparc/miscregfile.cc +++ b/src/arch/sparc/miscregfile.cc @@ -280,6 +280,7 @@ MiscReg MiscRegFile::readRegWithEffect(int miscReg, ThreadContext * tc) switch (miscReg) { // tick and stick are aliased to each other in niagra case MISCREG_TICK: + case MISCREG_STICK: case MISCREG_PRIVTICK: // I'm not sure why legion ignores the lowest two bits, but we'll go // with it @@ -296,10 +297,10 @@ MiscReg MiscRegFile::readRegWithEffect(int miscReg, ThreadContext * tc) /** Floating Point Status Register */ case MISCREG_FSR: panic("Floating Point not implemented\n"); - case MISCREG_STICK: - case MISCREG_SOFTINT: case MISCREG_SOFTINT_CLR: case MISCREG_SOFTINT_SET: + panic("Can read from softint clr/set\n"); + case MISCREG_SOFTINT: case MISCREG_TICK_CMPR: case MISCREG_STICK_CMPR: case MISCREG_HPSTATE: @@ -499,20 +500,28 @@ void MiscRegFile::setReg(int miscReg, const MiscReg &val) case MISCREG_SCRATCHPAD_R0: scratchPad[0] = val; + break; case MISCREG_SCRATCHPAD_R1: scratchPad[1] = val; + break; case MISCREG_SCRATCHPAD_R2: scratchPad[2] = val; + break; case MISCREG_SCRATCHPAD_R3: scratchPad[3] = val; + break; case MISCREG_SCRATCHPAD_R4: scratchPad[4] = val; + break; case MISCREG_SCRATCHPAD_R5: scratchPad[5] = val; + break; case MISCREG_SCRATCHPAD_R6: scratchPad[6] = val; + break; case MISCREG_SCRATCHPAD_R7: scratchPad[7] = val; + break; default: panic("Miscellaneous register %d not implemented\n", miscReg); diff --git a/src/arch/sparc/miscregfile.hh b/src/arch/sparc/miscregfile.hh index 916c23028..260a3344b 100644 --- a/src/arch/sparc/miscregfile.hh +++ b/src/arch/sparc/miscregfile.hh @@ -47,7 +47,7 @@ namespace SparcISA enum MiscRegIndex { /** Ancillary State Registers */ - MISCREG_Y, + MISCREG_Y, /* 0 */ MISCREG_CCR, MISCREG_ASI, MISCREG_TICK, @@ -57,7 +57,7 @@ namespace SparcISA MISCREG_GSR, MISCREG_SOFTINT_SET, MISCREG_SOFTINT_CLR, - MISCREG_SOFTINT, + MISCREG_SOFTINT, /* 10 */ MISCREG_TICK_CMPR, MISCREG_STICK, MISCREG_STICK_CMPR, @@ -69,7 +69,7 @@ namespace SparcISA MISCREG_TT, MISCREG_PRIVTICK, MISCREG_TBA, - MISCREG_PSTATE, + MISCREG_PSTATE, /* 20 */ MISCREG_TL, MISCREG_PIL, MISCREG_CWP, @@ -81,7 +81,7 @@ namespace SparcISA MISCREG_GL, /** Hyper privileged registers */ - MISCREG_HPSTATE, + MISCREG_HPSTATE, /* 30 */ MISCREG_HTSTATE, MISCREG_HINTP, MISCREG_HTBA, @@ -94,7 +94,7 @@ namespace SparcISA /** MMU Internal Registers */ MISCREG_MMU_P_CONTEXT, - MISCREG_MMU_S_CONTEXT, + MISCREG_MMU_S_CONTEXT, /* 40 */ MISCREG_MMU_PART_ID, MISCREG_MMU_LSU_CTRL, @@ -105,7 +105,7 @@ namespace SparcISA MISCREG_MMU_ITLB_CX_TSB_PS1, MISCREG_MMU_ITLB_CX_CONFIG, MISCREG_MMU_ITLB_SFSR, - MISCREG_MMU_ITLB_TAG_ACCESS, + MISCREG_MMU_ITLB_TAG_ACCESS, /* 50 */ MISCREG_MMU_DTLB_C0_TSB_PS0, MISCREG_MMU_DTLB_C0_TSB_PS1, @@ -118,7 +118,7 @@ namespace SparcISA MISCREG_MMU_DTLB_TAG_ACCESS, /** Scratchpad regiscers **/ - MISCREG_SCRATCHPAD_R0, + MISCREG_SCRATCHPAD_R0, /* 60 */ MISCREG_SCRATCHPAD_R1, MISCREG_SCRATCHPAD_R2, MISCREG_SCRATCHPAD_R3, diff --git a/src/arch/sparc/tlb.cc b/src/arch/sparc/tlb.cc index 51f867612..3ab40ce63 100644 --- a/src/arch/sparc/tlb.cc +++ b/src/arch/sparc/tlb.cc @@ -33,6 +33,9 @@ #include "arch/sparc/tlb.hh" #include "base/trace.hh" #include "cpu/thread_context.hh" +#include "cpu/base.hh" +#include "mem/packet_access.hh" +#include "mem/request.hh" #include "sim/builder.hh" /* @todo remove some of the magic constants. -- ali @@ -427,7 +430,7 @@ DTB::translate(RequestPtr &req, ThreadContext *tc, bool write) context = tc->readMiscReg(MISCREG_MMU_P_CONTEXT); } } else if (!hpriv && !red) { - if (tl > 0) { + if (tl > 0 || AsiIsNucleus(asi)) { ct = Nucleus; context = 0; } else if (AsiIsSecondary(asi)) { @@ -476,11 +479,14 @@ DTB::translate(RequestPtr &req, ThreadContext *tc, bool write) panic("Twin ASIs not supported\n"); if (AsiIsPartialStore(asi)) panic("Partial Store ASIs not supported\n"); + if (AsiIsMmu(asi)) goto handleMmuRegAccess; - if (AsiIsScratchPad(asi)) goto handleScratchRegAccess; + + if (!AsiIsReal(asi) && !AsiIsNucleus(asi)) + panic("Accessing ASI %#X. Should we?\n", asi); } if ((!lsuDm && !hpriv) || AsiIsReal(asi)) { @@ -546,13 +552,194 @@ handleMmuRegAccess: Tick DTB::doMmuRegRead(ThreadContext *tc, Packet *pkt) { - panic("need to implement DTB::doMmuRegRead()\n"); + Addr va = pkt->getAddr(); + ASI asi = (ASI)pkt->req->getAsi(); + + DPRINTF(IPR, "Memory Mapped IPR Read: asi=%#X a=%#x\n", + (uint32_t)pkt->req->getAsi(), pkt->getAddr()); + + switch (asi) { + case ASI_LSU_CONTROL_REG: + assert(va == 0); + pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_LSU_CTRL)); + break; + case ASI_MMU: + switch (va) { + case 0x8: + pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_P_CONTEXT)); + break; + case 0x10: + pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_S_CONTEXT)); + break; + default: + goto doMmuReadError; + } + break; + case ASI_DMMU_CTXT_ZERO_TSB_BASE_PS0: + assert(va == 0); + pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_C0_TSB_PS0)); + break; + case ASI_DMMU_CTXT_ZERO_TSB_BASE_PS1: + assert(va == 0); + pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_C0_TSB_PS1)); + break; + case ASI_DMMU_CTXT_ZERO_CONFIG: + assert(va == 0); + pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_C0_CONFIG)); + break; + case ASI_IMMU_CTXT_ZERO_TSB_BASE_PS0: + assert(va == 0); + pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_C0_TSB_PS0)); + break; + case ASI_IMMU_CTXT_ZERO_TSB_BASE_PS1: + assert(va == 0); + pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_C0_TSB_PS1)); + break; + case ASI_IMMU_CTXT_ZERO_CONFIG: + assert(va == 0); + pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_C0_CONFIG)); + break; + case ASI_DMMU_CTXT_NONZERO_TSB_BASE_PS0: + assert(va == 0); + pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_CX_TSB_PS0)); + break; + case ASI_DMMU_CTXT_NONZERO_TSB_BASE_PS1: + assert(va == 0); + pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_CX_TSB_PS1)); + break; + case ASI_DMMU_CTXT_NONZERO_CONFIG: + assert(va == 0); + pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_CX_CONFIG)); + break; + case ASI_IMMU_CTXT_NONZERO_TSB_BASE_PS0: + assert(va == 0); + pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_CX_TSB_PS0)); + break; + case ASI_IMMU_CTXT_NONZERO_TSB_BASE_PS1: + assert(va == 0); + pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_CX_TSB_PS1)); + break; + case ASI_IMMU_CTXT_NONZERO_CONFIG: + assert(va == 0); + pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_CX_CONFIG)); + break; + case ASI_HYP_SCRATCHPAD: + case ASI_SCRATCHPAD: + pkt->set(tc->readMiscRegWithEffect(MISCREG_SCRATCHPAD_R0 + (va >> 3))); + break; + case ASI_DMMU: + switch (va) { + case 0x80: + pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_PART_ID)); + break; + default: + goto doMmuReadError; + } + break; + default: +doMmuReadError: + panic("need to impl DTB::doMmuRegRead() got asi=%#x, va=%#x\n", + (uint32_t)asi, va); + } + pkt->result = Packet::Success; + return tc->getCpuPtr()->cycles(1); } Tick DTB::doMmuRegWrite(ThreadContext *tc, Packet *pkt) { - panic("need to implement DTB::doMmuRegWrite()\n"); + uint64_t data = gtoh(pkt->get()); + Addr va = pkt->getAddr(); + ASI asi = (ASI)pkt->req->getAsi(); + + DPRINTF(IPR, "Memory Mapped IPR Write: asi=#%X a=%#x d=%#X\n", + (uint32_t)asi, va, data); + + switch (asi) { + case ASI_LSU_CONTROL_REG: + assert(va == 0); + tc->setMiscRegWithEffect(MISCREG_MMU_LSU_CTRL, data); + break; + case ASI_MMU: + switch (va) { + case 0x8: + tc->setMiscRegWithEffect(MISCREG_MMU_P_CONTEXT, data); + break; + case 0x10: + tc->setMiscRegWithEffect(MISCREG_MMU_S_CONTEXT, data); + break; + default: + goto doMmuWriteError; + } + break; + case ASI_DMMU_CTXT_ZERO_TSB_BASE_PS0: + assert(va == 0); + tc->setMiscRegWithEffect(MISCREG_MMU_DTLB_C0_TSB_PS0, data); + break; + case ASI_DMMU_CTXT_ZERO_TSB_BASE_PS1: + assert(va == 0); + tc->setMiscRegWithEffect(MISCREG_MMU_DTLB_C0_TSB_PS1, data); + break; + case ASI_DMMU_CTXT_ZERO_CONFIG: + assert(va == 0); + tc->setMiscRegWithEffect(MISCREG_MMU_DTLB_C0_CONFIG, data); + break; + case ASI_IMMU_CTXT_ZERO_TSB_BASE_PS0: + assert(va == 0); + tc->setMiscRegWithEffect(MISCREG_MMU_ITLB_C0_TSB_PS0, data); + break; + case ASI_IMMU_CTXT_ZERO_TSB_BASE_PS1: + assert(va == 0); + tc->setMiscRegWithEffect(MISCREG_MMU_ITLB_C0_TSB_PS1, data); + break; + case ASI_IMMU_CTXT_ZERO_CONFIG: + assert(va == 0); + tc->setMiscRegWithEffect(MISCREG_MMU_ITLB_C0_CONFIG, data); + break; + case ASI_DMMU_CTXT_NONZERO_TSB_BASE_PS0: + assert(va == 0); + tc->setMiscRegWithEffect(MISCREG_MMU_DTLB_CX_TSB_PS0, data); + break; + case ASI_DMMU_CTXT_NONZERO_TSB_BASE_PS1: + assert(va == 0); + tc->setMiscRegWithEffect(MISCREG_MMU_DTLB_CX_TSB_PS1, data); + break; + case ASI_DMMU_CTXT_NONZERO_CONFIG: + assert(va == 0); + tc->setMiscRegWithEffect(MISCREG_MMU_DTLB_CX_CONFIG, data); + break; + case ASI_IMMU_CTXT_NONZERO_TSB_BASE_PS0: + assert(va == 0); + tc->setMiscRegWithEffect(MISCREG_MMU_ITLB_CX_TSB_PS0, data); + break; + case ASI_IMMU_CTXT_NONZERO_TSB_BASE_PS1: + assert(va == 0); + tc->setMiscRegWithEffect(MISCREG_MMU_ITLB_CX_TSB_PS1, data); + break; + case ASI_IMMU_CTXT_NONZERO_CONFIG: + assert(va == 0); + tc->setMiscRegWithEffect(MISCREG_MMU_ITLB_CX_CONFIG, data); + break; + case ASI_HYP_SCRATCHPAD: + case ASI_SCRATCHPAD: + tc->setMiscRegWithEffect(MISCREG_SCRATCHPAD_R0 + (va >> 3), data); + break; + case ASI_DMMU: + switch (va) { + case 0x80: + tc->setMiscRegWithEffect(MISCREG_MMU_PART_ID, data); + break; + default: + goto doMmuWriteError; + } + break; + default: +doMmuWriteError: + panic("need to impl DTB::doMmuRegWrite() got asi=%#x, va=%#x d=%#x\n", + (uint32_t)pkt->req->getAsi(), pkt->getAddr(), data); + } + pkt->result = Packet::Success; + return tc->getCpuPtr()->cycles(1); } void diff --git a/src/base/traceflags.py b/src/base/traceflags.py index 92735aa5f..c06399f81 100644 --- a/src/base/traceflags.py +++ b/src/base/traceflags.py @@ -109,6 +109,7 @@ baseFlags = [ 'IIC', 'IICMore', 'IPI', + 'IPR', 'IQ', 'ISP', 'IdeCtrl', diff --git a/src/mem/request.hh b/src/mem/request.hh index b01c02441..de0512e1c 100644 --- a/src/mem/request.hh +++ b/src/mem/request.hh @@ -234,7 +234,7 @@ class Request bool isMmapedIpr() { assert(validPaddr); return mmapedIpr; } /** Accessor function for asi.*/ - void setMmapedIpr(bool r) { assert(validPaddr); mmapedIpr = r; } + void setMmapedIpr(bool r) { assert(validAsidVaddr); mmapedIpr = r; } /** Accessor function to check if sc result is valid. */ bool scResultValid() { return validScResult; }