inorder: stage scheduler for front/back end schedule creation
add a stage scheduler class to replace InstStage in pipeline_traits.cc use that class to define a default front-end, resource schedule that all instructions will follow. This will also replace the back end schedule in pipeline_traits.cc. The reason for adding this is so that we can cache instruction schedules in the future instead of calling the same function over/over again as well as constantly dynamically alllocating memory on every instruction to try to figure out it's schedule
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2 changed files with 126 additions and 0 deletions
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@ -341,6 +341,7 @@ InOrderCPU::InOrderCPU(Params *params)
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dummyBufferInst->resetInstCount();
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dummyBufferInst->resetInstCount();
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endOfSkedIt = skedCache.end();
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endOfSkedIt = skedCache.end();
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frontEndSked = createFrontEndSked();
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lastRunningCycle = curTick();
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lastRunningCycle = curTick();
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@ -364,6 +365,102 @@ InOrderCPU::~InOrderCPU()
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std::map<InOrderCPU::SkedID, ThePipeline::RSkedPtr> InOrderCPU::skedCache;
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std::map<InOrderCPU::SkedID, ThePipeline::RSkedPtr> InOrderCPU::skedCache;
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RSkedPtr
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InOrderCPU::createFrontEndSked()
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{
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RSkedPtr res_sked = NULL;
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int stage_num = 0;
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StageScheduler F(res_sked, stage_num++);
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StageScheduler D(res_sked, stage_num++);
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// FETCH
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F.needs(FetchSeq, FetchSeqUnit::AssignNextPC);
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F.needs(ICache, FetchUnit::InitiateFetch);
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// DECODE
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D.needs(ICache, FetchUnit::CompleteFetch);
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D.needs(Decode, DecodeUnit::DecodeInst);
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D.needs(BPred, BranchPredictor::PredictBranch);
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D.needs(FetchSeq, FetchSeqUnit::UpdateTargetPC);
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return res_sked;
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}
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RSkedPtr
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InOrderCPU::createBackEndSked(DynInstPtr inst)
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{
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RSkedPtr res_sked = lookupSked(inst);
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if (res_sked != NULL) {
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return res_sked;
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}
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int stage_num = ThePipeline::BackEndStartStage;
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StageScheduler X(res_sked, stage_num++);
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StageScheduler M(res_sked, stage_num++);
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StageScheduler W(res_sked, stage_num++);
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if (!inst->staticInst) {
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warn_once("Static Instruction Object Not Set. Can't Create"
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" Back End Schedule");
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return false;
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}
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// EXECUTE
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for (int idx=0; idx < inst->numSrcRegs(); idx++) {
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if (!idx || !inst->isStore()) {
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X.needs(RegManager, UseDefUnit::ReadSrcReg, idx);
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}
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}
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if ( inst->isNonSpeculative() ) {
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// skip execution of non speculative insts until later
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} else if ( inst->isMemRef() ) {
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if ( inst->isLoad() ) {
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X.needs(AGEN, AGENUnit::GenerateAddr);
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}
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} else if (inst->opClass() == IntMultOp || inst->opClass() == IntDivOp) {
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X.needs(MDU, MultDivUnit::StartMultDiv);
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} else {
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X.needs(ExecUnit, ExecutionUnit::ExecuteInst);
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}
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if (inst->opClass() == IntMultOp || inst->opClass() == IntDivOp) {
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X.needs(MDU, MultDivUnit::EndMultDiv);
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}
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// MEMORY
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if ( inst->isLoad() ) {
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M.needs(DCache, CacheUnit::InitiateReadData);
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} else if ( inst->isStore() ) {
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if ( inst->numSrcRegs() >= 2 ) {
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M.needs(RegManager, UseDefUnit::ReadSrcReg, 1);
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}
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M.needs(AGEN, AGENUnit::GenerateAddr);
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M.needs(DCache, CacheUnit::InitiateWriteData);
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}
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// WRITEBACK
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if ( inst->isLoad() ) {
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W.needs(DCache, CacheUnit::CompleteReadData);
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} else if ( inst->isStore() ) {
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W.needs(DCache, CacheUnit::CompleteWriteData);
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}
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if ( inst->isNonSpeculative() ) {
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if ( inst->isMemRef() ) fatal("Non-Speculative Memory Instruction");
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W.needs(ExecUnit, ExecutionUnit::ExecuteInst);
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}
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for (int idx=0; idx < inst->numDestRegs(); idx++) {
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W.needs(RegManager, UseDefUnit::WriteDestReg, idx);
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}
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W.needs(Grad, GraduationUnit::GraduateInst);
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return res_sked;
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}
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void
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void
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InOrderCPU::regStats()
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InOrderCPU::regStats()
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{
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{
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@ -309,6 +309,8 @@ class InOrderCPU : public BaseCPU
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*/
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*/
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SkedCacheIt endOfSkedIt;
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SkedCacheIt endOfSkedIt;
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ThePipeline::RSkedPtr frontEndSked;
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/** Add a new instruction schedule to the schedule cache */
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/** Add a new instruction schedule to the schedule cache */
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void addToSkedCache(DynInstPtr inst, ThePipeline::RSkedPtr inst_sked)
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void addToSkedCache(DynInstPtr inst, ThePipeline::RSkedPtr inst_sked)
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{
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{
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@ -351,6 +353,33 @@ class InOrderCPU : public BaseCPU
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return id;
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return id;
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}
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}
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ThePipeline::RSkedPtr createFrontEndSked();
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ThePipeline::RSkedPtr createBackEndSked(DynInstPtr inst);
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class StageScheduler {
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private:
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ThePipeline::RSkedPtr rsked;
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int stageNum;
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int nextTaskPriority;
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public:
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StageScheduler(ThePipeline::RSkedPtr _rsked, int stage_num)
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: rsked(_rsked), stageNum(stage_num),
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nextTaskPriority(0)
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{ }
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void needs(int unit, int request) {
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rsked->push(new ScheduleEntry(
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stageNum, nextTaskPriority++, unit, request
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));
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}
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void needs(int unit, int request, int param) {
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rsked->push(new ScheduleEntry(
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stageNum, nextTaskPriority++, unit, request, param
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));
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}
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};
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public:
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public:
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