Added fastmem option.

Lets CPU accesses to physical memory bypass Bus.

--HG--
extra : convert_revision : e56e3879de47ee10951a19bfcd8b62b6acdfb30c

configs/common/Options.py

@@ -32,6 +32,7 @@ parser.add_option("-t", "--timing", action="store_true")
 parser.add_option("-n", "--num_cpus", type="int", default=1)
 parser.add_option("--caches", action="store_true")
 parser.add_option("--l2cache", action="store_true")
+parser.add_option("--fastmem", action="store_true")
 
 # Run duration options
 parser.add_option("-m", "--maxtick", type="int")

configs/example/fs.py

@@ -132,6 +132,9 @@ for i in xrange(np):
     else:
         test_sys.cpu[i].connectMemPorts(test_sys.membus)
 
+    if options.fastmem:
+        test_sys.cpu[i].physmem_port = test_sys.physmem.port
+
 if len(bm) == 2:
     if m5.build_env['TARGET_ISA'] == 'alpha':
         drive_sys = makeLinuxAlphaSystem(drive_mem_mode, bm[1])
@@ -139,6 +142,8 @@ if len(bm) == 2:
         drive_sys = makeSparcSystem(drive_mem_mode, bm[1])
     drive_sys.cpu = DriveCPUClass(cpu_id=0)
     drive_sys.cpu.connectMemPorts(drive_sys.membus)
+    if options.fastmem:
+        drive_sys.cpu.physmem_port = drive_sys.physmem.port
     if options.kernel is not None:
         drive_sys.kernel = binary(options.kernel)
 

configs/example/se.py

@@ -114,6 +114,9 @@ for i in xrange(np):
         system.cpu[i].connectMemPorts(system.membus)
     system.cpu[i].workload = process
 
+    if options.fastmem:
+        system.cpu[0].physmem_port = system.physmem.port
+
 root = Root(system = system)
 
 Simulation.run(options, root, system, FutureClass)

src/cpu/BaseCPU.py

@@ -93,10 +93,11 @@ class BaseCPU(SimObject):
 
     def connectMemPorts(self, bus):
         for p in self._mem_ports:
+            if p != 'physmem_port':
                 exec('self.%s = bus.port' % p)
 
     def addPrivateSplitL1Caches(self, ic, dc):
-        assert(len(self._mem_ports) == 2)
+        assert(len(self._mem_ports) == 2 or len(self._mem_ports) == 3)
         self.icache = ic
         self.dcache = dc
         self.icache_port = ic.cpu_side

src/cpu/simple/AtomicSimpleCPU.py

@@ -40,4 +40,5 @@ class AtomicSimpleCPU(BaseCPU):
         profile = Param.Latency('0ns', "trace the kernel stack")
     icache_port = Port("Instruction Port")
     dcache_port = Port("Data Port")
-    _mem_ports = ['icache_port', 'dcache_port']
+    physmem_port = Port("Physical Memory Port")
+    _mem_ports = ['icache_port', 'dcache_port', 'physmem_port']

src/cpu/simple/atomic.cc

@@ -67,6 +67,10 @@ AtomicSimpleCPU::getPort(const std::string &if_name, int idx)
         return &dcachePort;
     else if (if_name == "icache_port")
         return &icachePort;
+    else if (if_name == "physmem_port") {
+        hasPhysMemPort = true;
+        return &physmemPort;
+    }
     else
         panic("No Such Port\n");
 }
@@ -83,6 +87,12 @@ AtomicSimpleCPU::init()
         TheISA::initCPU(tc, tc->readCpuId());
     }
 #endif
+    if (hasPhysMemPort) {
+        bool snoop = false;
+        AddrRangeList pmAddrList;
+        physmemPort.getPeerAddressRanges(pmAddrList, snoop);
+        physMemAddr = *pmAddrList.begin();
+    }
 }
 
 bool
@@ -141,7 +151,8 @@ AtomicSimpleCPU::DcachePort::setPeer(Port *port)
 AtomicSimpleCPU::AtomicSimpleCPU(Params *p)
     : BaseSimpleCPU(p), tickEvent(this),
       width(p->width), simulate_stalls(p->simulate_stalls),
-      icachePort(name() + "-iport", this), dcachePort(name() + "-iport", this)
+      icachePort(name() + "-iport", this), dcachePort(name() + "-iport", this),
+      physmemPort(name() + "-iport", this), hasPhysMemPort(false)
 {
     _status = Idle;
 
@@ -293,8 +304,12 @@ AtomicSimpleCPU::read(Addr addr, T &data, unsigned flags)
 
         if (req->isMmapedIpr())
             dcache_latency = TheISA::handleIprRead(thread->getTC(), &pkt);
+        else {
+            if (hasPhysMemPort && pkt.getAddr() == physMemAddr)
+                dcache_latency = physmemPort.sendAtomic(&pkt);
             else
                 dcache_latency = dcachePort.sendAtomic(&pkt);
+        }
         dcache_access = true;
         assert(!pkt.isError());
 
@@ -402,6 +417,9 @@ AtomicSimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res)
                 dcache_latency = TheISA::handleIprWrite(thread->getTC(), &pkt);
             } else {
                 data = htog(data);
+                if (hasPhysMemPort && pkt.getAddr() == physMemAddr)
+                    dcache_latency = physmemPort.sendAtomic(&pkt);
+                else
                     dcache_latency = dcachePort.sendAtomic(&pkt);
             }
             dcache_access = true;
@@ -513,7 +531,12 @@ AtomicSimpleCPU::tick()
                                            Packet::Broadcast);
                 ifetch_pkt.dataStatic(&inst);
 
+                if (hasPhysMemPort && ifetch_pkt.getAddr() == physMemAddr)
+                    icache_latency = physmemPort.sendAtomic(&ifetch_pkt);
+                else
                     icache_latency = icachePort.sendAtomic(&ifetch_pkt);
+
+
                 // ifetch_req is initialized to read the instruction directly
                 // into the CPU object's inst field.
             //}

src/cpu/simple/atomic.hh

@@ -121,6 +121,8 @@ class AtomicSimpleCPU : public BaseSimpleCPU
     };
     DcachePort dcachePort;
 
+    CpuPort physmemPort;
+    bool hasPhysMemPort;
     Request ifetch_req;
     Request data_read_req;
     Request data_write_req;
@@ -128,6 +130,8 @@ class AtomicSimpleCPU : public BaseSimpleCPU
     bool dcache_access;
     Tick dcache_latency;
 
+    Range<Addr> physMemAddr;
+
   public:
 
     virtual Port *getPort(const std::string &if_name, int idx = -1);