SE/FS: Make SE vs. FS mode a runtime parameter.
This commit is contained in:
parent
eab5c60286
commit
ec20ee2f7c
47 changed files with 55 additions and 49 deletions
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@ -552,8 +552,8 @@ def makeLinuxX86System(mem_mode, numCPUs = 1, mdesc = None, Ruby = False):
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return self
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return self
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def makeDualRoot(testSystem, driveSystem, dumpfile):
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def makeDualRoot(full_system, testSystem, driveSystem, dumpfile):
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self = Root()
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self = Root(full_system = full_system)
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self.testsys = testSystem
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self.testsys = testSystem
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self.drivesys = driveSystem
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self.drivesys = driveSystem
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self.etherlink = EtherLink()
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self.etherlink = EtherLink()
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@ -198,9 +198,9 @@ if len(bm) == 2:
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drive_sys.kernel = binary(options.kernel)
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drive_sys.kernel = binary(options.kernel)
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drive_sys.init_param = options.init_param
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drive_sys.init_param = options.init_param
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root = makeDualRoot(test_sys, drive_sys, options.etherdump)
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root = makeDualRoot(True, test_sys, drive_sys, options.etherdump)
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elif len(bm) == 1:
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elif len(bm) == 1:
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root = Root(system=test_sys)
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root = Root(full_system=True, system=test_sys)
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else:
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else:
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print "Error I don't know how to create more than 2 systems."
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print "Error I don't know how to create more than 2 systems."
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sys.exit(1)
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sys.exit(1)
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@ -172,7 +172,7 @@ make_level(treespec, prototypes, system.physmem, "port")
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# run simulation
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# run simulation
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# -----------------------
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# -----------------------
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root = Root( system = system )
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root = Root( full_system = False, system = system )
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if options.atomic:
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if options.atomic:
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root.system.mem_mode = 'atomic'
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root.system.mem_mode = 'atomic'
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else:
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else:
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@ -111,7 +111,7 @@ for ruby_port in system.ruby._cpu_ruby_ports:
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# run simulation
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# run simulation
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# -----------------------
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# -----------------------
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root = Root( system = system )
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root = Root( full_system = False, system = system )
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root.system.mem_mode = 'timing'
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root.system.mem_mode = 'timing'
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# Not much point in this being higher than the L1 latency
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# Not much point in this being higher than the L1 latency
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@ -141,6 +141,6 @@ for (i, cpu) in enumerate(system.cpu):
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cpu.interrupts.pio = system.piobus.port
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cpu.interrupts.pio = system.piobus.port
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cpu.interrupts.int_port = system.piobus.port
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cpu.interrupts.int_port = system.piobus.port
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root = Root(system = system)
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root = Root(full_system = True, system = system)
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Simulation.run(options, root, system, FutureClass)
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Simulation.run(options, root, system, FutureClass)
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@ -162,7 +162,7 @@ for (i, dma) in enumerate(dmas):
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# run simulation
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# run simulation
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# -----------------------
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# -----------------------
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root = Root( system = system )
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root = Root( full_system = False, system = system )
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root.system.mem_mode = 'timing'
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root.system.mem_mode = 'timing'
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# Not much point in this being higher than the L1 latency
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# Not much point in this being higher than the L1 latency
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@ -121,7 +121,7 @@ for ruby_port in system.ruby._cpu_ruby_ports:
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# run simulation
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# run simulation
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# -----------------------
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# -----------------------
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root = Root( system = system )
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root = Root( full_system = False, system = system )
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root.system.mem_mode = 'timing'
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root.system.mem_mode = 'timing'
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# Not much point in this being higher than the L1 latency
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# Not much point in this being higher than the L1 latency
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@ -131,7 +131,7 @@ for ruby_port in system.ruby._cpu_ruby_ports:
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# run simulation
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# run simulation
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# -----------------------
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# -----------------------
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root = Root( system = system )
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root = Root( full_system = False, system = system )
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root.system.mem_mode = 'timing'
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root.system.mem_mode = 'timing'
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# Not much point in this being higher than the L1 latency
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# Not much point in this being higher than the L1 latency
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@ -200,6 +200,6 @@ for i in xrange(np):
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if options.fastmem:
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if options.fastmem:
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system.cpu[0].physmem_port = system.physmem.port
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system.cpu[0].physmem_port = system.physmem.port
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root = Root(system = system)
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root = Root(full_system = False, system = system)
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Simulation.run(options, root, system, FutureClass)
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Simulation.run(options, root, system, FutureClass)
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@ -239,7 +239,7 @@ for cluster in clusters:
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# Define the root
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# Define the root
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# ----------------------
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# ----------------------
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root = Root(system = system)
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root = Root(full_system = False, system = system)
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# --------------------
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# --------------------
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# Pick the correct Splash2 Benchmarks
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# Pick the correct Splash2 Benchmarks
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@ -225,7 +225,7 @@ for cpu in cpus:
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# Define the root
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# Define the root
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# ----------------------
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# ----------------------
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root = Root(system = system)
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root = Root(full_system = False, system = system)
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# --------------------
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# --------------------
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# Pick the correct Splash2 Benchmarks
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# Pick the correct Splash2 Benchmarks
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@ -28,6 +28,7 @@
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# Authors: Nathan Binkert
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# Authors: Nathan Binkert
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from m5.SimObject import SimObject
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from m5.SimObject import SimObject
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from m5.defines import buildEnv
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from m5.params import *
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from m5.params import *
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from m5.util import fatal
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from m5.util import fatal
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@ -58,6 +59,8 @@ class Root(SimObject):
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type = 'Root'
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type = 'Root'
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full_system = Param.Bool("if this is a full system simulation")
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# Time syncing prevents the simulation from running faster than real time.
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# Time syncing prevents the simulation from running faster than real time.
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time_sync_enable = Param.Bool(False, "whether time syncing is enabled")
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time_sync_enable = Param.Bool(False, "whether time syncing is enabled")
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time_sync_period = Param.Clock("100ms", "how often to sync with real time")
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time_sync_period = Param.Clock("100ms", "how often to sync with real time")
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@ -31,8 +31,6 @@
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#ifndef __SIM_FULL_SYSTEM_HH__
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#ifndef __SIM_FULL_SYSTEM_HH__
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#define __SIM_FULL_SYSTEM_HH__
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#define __SIM_FULL_SYSTEM_HH__
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#include "config/full_system.hh"
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extern bool FullSystem;
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static const bool FullSystem = FULL_SYSTEM;
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#endif // __SIM_FULL_SYSTEM_HH__
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#endif // __SIM_FULL_SYSTEM_HH__
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@ -33,6 +33,7 @@
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#include "base/misc.hh"
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#include "base/misc.hh"
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#include "debug/TimeSync.hh"
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#include "debug/TimeSync.hh"
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#include "sim/full_system.hh"
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#include "sim/root.hh"
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#include "sim/root.hh"
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Root *Root::_root = NULL;
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Root *Root::_root = NULL;
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@ -123,6 +124,8 @@ Root::loadState(Checkpoint *cp)
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timeSyncEnable(params()->time_sync_enable);
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timeSyncEnable(params()->time_sync_enable);
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}
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}
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bool FullSystem;
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Root *
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Root *
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RootParams::create()
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RootParams::create()
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{
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{
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@ -132,5 +135,7 @@ RootParams::create()
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created = true;
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created = true;
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FullSystem = full_system;
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return new Root(this);
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return new Root(this);
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}
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}
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@ -54,4 +54,4 @@ system.system_port = system.membus.port
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system.physmem.port = system.membus.port
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system.physmem.port = system.membus.port
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cpu.connectAllPorts(system.membus)
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cpu.connectAllPorts(system.membus)
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root = Root(system = system)
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root = Root(full_system = False, system = system)
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@ -117,7 +117,7 @@ system.system_port = system.ruby._sys_port_proxy.port
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# run simulation
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# run simulation
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# -----------------------
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# -----------------------
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root = Root(system = system)
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root = Root(full_system = False, system = system)
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root.system.mem_mode = 'timing'
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root.system.mem_mode = 'timing'
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# Not much point in this being higher than the L1 latency
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# Not much point in this being higher than the L1 latency
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@ -86,7 +86,7 @@ system.physmem.port = system.membus.port
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# run simulation
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# run simulation
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# -----------------------
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# -----------------------
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root = Root( system = system )
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root = Root( full_system = False, system = system )
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root.system.mem_mode = 'timing'
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root.system.mem_mode = 'timing'
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#root.trace.flags="Cache CachePort MemoryAccess"
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#root.trace.flags="Cache CachePort MemoryAccess"
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#root.trace.cycle=1
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#root.trace.cycle=1
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@ -51,5 +51,5 @@ system.physmem.port = system.membus.port
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# run simulation
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# run simulation
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# -----------------------
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# -----------------------
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root = Root(system = system)
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root = Root(full_system = False, system = system)
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root.system.mem_mode = 'timing'
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root.system.mem_mode = 'timing'
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@ -86,7 +86,7 @@ system.system_port = system.membus.port
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# run simulation
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# run simulation
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# -----------------------
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# -----------------------
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root = Root( system = system )
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root = Root( full_system = False, system = system )
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root.system.mem_mode = 'timing'
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root.system.mem_mode = 'timing'
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#root.trace.flags="Bus Cache"
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#root.trace.flags="Bus Cache"
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#root.trace.flags = "BusAddrRanges"
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#root.trace.flags = "BusAddrRanges"
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@ -43,4 +43,4 @@ system = System(cpu = cpu,
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system.physmem.port = system.membus.port
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system.physmem.port = system.membus.port
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cpu.connectAllPorts(system.membus)
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cpu.connectAllPorts(system.membus)
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root = Root(system = system)
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root = Root(full_system = False, system = system)
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@ -54,4 +54,4 @@ system.system_port = system.membus.port
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system.physmem.port = system.membus.port
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system.physmem.port = system.membus.port
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cpu.connectAllPorts(system.membus)
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cpu.connectAllPorts(system.membus)
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root = Root(system = system)
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root = Root(full_system = False, system = system)
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@ -108,6 +108,6 @@ cpu.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1),
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cpu.connectAllPorts(system.toL2Bus, system.membus)
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cpu.connectAllPorts(system.toL2Bus, system.membus)
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cpu.clock = '2GHz'
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cpu.clock = '2GHz'
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root = Root(system=system)
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root = Root(full_system=True, system=system)
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m5.ticks.setGlobalFrequency('1THz')
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m5.ticks.setGlobalFrequency('1THz')
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@ -110,6 +110,6 @@ cpu.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1),
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cpu.connectAllPorts(system.toL2Bus, system.membus)
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cpu.connectAllPorts(system.toL2Bus, system.membus)
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cpu.clock = '2GHz'
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cpu.clock = '2GHz'
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root = Root(system=system)
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root = Root(full_system=True, system=system)
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m5.ticks.setGlobalFrequency('1THz')
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m5.ticks.setGlobalFrequency('1THz')
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@ -110,6 +110,6 @@ cpu.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1),
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cpu.connectAllPorts(system.toL2Bus, system.membus)
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cpu.connectAllPorts(system.toL2Bus, system.membus)
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cpu.clock = '2GHz'
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cpu.clock = '2GHz'
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root = Root(system=system)
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root = Root(full_system=True, system=system)
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m5.ticks.setGlobalFrequency('1THz')
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m5.ticks.setGlobalFrequency('1THz')
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c.clock = '2GHz'
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c.clock = '2GHz'
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root = Root(system=system)
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root = Root(full_system=True, system=system)
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m5.ticks.setGlobalFrequency('1THz')
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m5.ticks.setGlobalFrequency('1THz')
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@ -92,6 +92,6 @@ cpu.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1),
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cpu.connectAllPorts(system.toL2Bus, system.membus)
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cpu.connectAllPorts(system.toL2Bus, system.membus)
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cpu.clock = '2GHz'
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cpu.clock = '2GHz'
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root = Root(system=system)
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root = Root(full_system=True, system=system)
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m5.ticks.setGlobalFrequency('1THz')
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m5.ticks.setGlobalFrequency('1THz')
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c.clock = '2GHz'
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c.clock = '2GHz'
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root = Root(system=system)
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root = Root(full_system=True, system=system)
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m5.ticks.setGlobalFrequency('1THz')
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m5.ticks.setGlobalFrequency('1THz')
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@ -90,6 +90,6 @@ cpu.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1),
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cpu.connectAllPorts(system.toL2Bus, system.membus)
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cpu.connectAllPorts(system.toL2Bus, system.membus)
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cpu.clock = '2GHz'
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cpu.clock = '2GHz'
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root = Root(system=system)
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root = Root(full_system=True, system=system)
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m5.ticks.setGlobalFrequency('1THz')
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m5.ticks.setGlobalFrequency('1THz')
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c.clock = '2GHz'
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c.clock = '2GHz'
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root = Root(system=system)
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root = Root(full_system=True, system=system)
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m5.ticks.setGlobalFrequency('1THz')
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m5.ticks.setGlobalFrequency('1THz')
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cpu.connectAllPorts(system.toL2Bus, system.membus)
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cpu.connectAllPorts(system.toL2Bus, system.membus)
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cpu.clock = '2GHz'
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cpu.clock = '2GHz'
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root = Root(system=system)
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root = Root(full_system=True, system=system)
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m5.ticks.setGlobalFrequency('1THz')
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m5.ticks.setGlobalFrequency('1THz')
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@ -112,7 +112,7 @@ system.system_port = system.ruby._sys_port_proxy.port
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# run simulation
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# run simulation
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# -----------------------
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# -----------------------
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root = Root( system = system )
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root = Root(full_system = False, system = system )
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root.system.mem_mode = 'timing'
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root.system.mem_mode = 'timing'
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# Not much point in this being higher than the L1 latency
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# Not much point in this being higher than the L1 latency
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@ -52,5 +52,5 @@ system.physmem.port = system.membus.port
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# run simulation
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# run simulation
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# -----------------------
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# -----------------------
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root = Root(system = system)
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root = Root(full_system = False, system = system)
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root.system.mem_mode = 'atomic'
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root.system.mem_mode = 'atomic'
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@ -85,5 +85,5 @@ system.system_port = system.membus.port
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# run simulation
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# run simulation
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# -----------------------
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# -----------------------
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root = Root( system = system )
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root = Root( full_system = False, system = system )
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root.system.mem_mode = 'atomic'
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root.system.mem_mode = 'atomic'
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@ -37,4 +37,4 @@ system.physmem.port = system.membus.port
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system.cpu.connectAllPorts(system.membus)
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system.cpu.connectAllPorts(system.membus)
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system.cpu.clock = '2GHz'
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system.cpu.clock = '2GHz'
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root = Root(system = system)
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root = Root(full_system = False, system = system)
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@ -95,7 +95,7 @@ system.system_port = system.ruby._sys_port_proxy.port
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# run simulation
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# run simulation
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# -----------------------
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# -----------------------
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root = Root( system = system )
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root = Root( full_system=False, system = system )
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root.system.mem_mode = 'timing'
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root.system.mem_mode = 'timing'
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# Not much point in this being higher than the L1 latency
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# Not much point in this being higher than the L1 latency
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@ -85,5 +85,5 @@ system.physmem.port = system.membus.port
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||||||
# run simulation
|
# run simulation
|
||||||
# -----------------------
|
# -----------------------
|
||||||
|
|
||||||
root = Root( system = system )
|
root = Root( full_system = False, system = system )
|
||||||
root.system.mem_mode = 'timing'
|
root.system.mem_mode = 'timing'
|
||||||
|
|
|
@ -91,7 +91,7 @@ system.system_port = system.ruby._sys_port_proxy.port
|
||||||
# run simulation
|
# run simulation
|
||||||
# -----------------------
|
# -----------------------
|
||||||
|
|
||||||
root = Root(system = system)
|
root = Root(full_system = False, system = system)
|
||||||
root.system.mem_mode = 'timing'
|
root.system.mem_mode = 'timing'
|
||||||
|
|
||||||
# Not much point in this being higher than the L1 latency
|
# Not much point in this being higher than the L1 latency
|
||||||
|
|
|
@ -51,4 +51,4 @@ system.physmem.port = system.membus.port
|
||||||
cpu.connectAllPorts(system.membus)
|
cpu.connectAllPorts(system.membus)
|
||||||
cpu.clock = '2GHz'
|
cpu.clock = '2GHz'
|
||||||
|
|
||||||
root = Root(system = system)
|
root = Root(full_system=False, system = system)
|
||||||
|
|
|
@ -36,6 +36,6 @@ system = FSConfig.makeSparcSystem('atomic')
|
||||||
system.cpu = cpu
|
system.cpu = cpu
|
||||||
cpu.connectAllPorts(system.membus)
|
cpu.connectAllPorts(system.membus)
|
||||||
|
|
||||||
root = Root(system=system)
|
root = Root(full_system=True, system=system)
|
||||||
|
|
||||||
m5.ticks.setGlobalFrequency('2GHz')
|
m5.ticks.setGlobalFrequency('2GHz')
|
||||||
|
|
|
@ -96,6 +96,6 @@ cpu.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1),
|
||||||
cpu.connectAllPorts(system.toL2Bus, system.membus)
|
cpu.connectAllPorts(system.toL2Bus, system.membus)
|
||||||
cpu.clock = '2GHz'
|
cpu.clock = '2GHz'
|
||||||
|
|
||||||
root = Root(system=system)
|
root = Root(full_system=True, system=system)
|
||||||
m5.ticks.setGlobalFrequency('1THz')
|
m5.ticks.setGlobalFrequency('1THz')
|
||||||
|
|
||||||
|
|
|
@ -95,6 +95,6 @@ for c in cpus:
|
||||||
c.connectAllPorts(system.toL2Bus, system.membus)
|
c.connectAllPorts(system.toL2Bus, system.membus)
|
||||||
c.clock = '2GHz'
|
c.clock = '2GHz'
|
||||||
|
|
||||||
root = Root(system=system)
|
root = Root(full_system=True, system=system)
|
||||||
m5.ticks.setGlobalFrequency('1THz')
|
m5.ticks.setGlobalFrequency('1THz')
|
||||||
|
|
||||||
|
|
|
@ -93,6 +93,6 @@ cpu.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1),
|
||||||
cpu.connectAllPorts(system.toL2Bus, system.membus)
|
cpu.connectAllPorts(system.toL2Bus, system.membus)
|
||||||
cpu.clock = '2GHz'
|
cpu.clock = '2GHz'
|
||||||
|
|
||||||
root = Root(system=system)
|
root = Root(full_system=True, system=system)
|
||||||
m5.ticks.setGlobalFrequency('1THz')
|
m5.ticks.setGlobalFrequency('1THz')
|
||||||
|
|
||||||
|
|
|
@ -93,5 +93,5 @@ for c in cpus:
|
||||||
c.connectAllPorts(system.toL2Bus, system.membus)
|
c.connectAllPorts(system.toL2Bus, system.membus)
|
||||||
c.clock = '2GHz'
|
c.clock = '2GHz'
|
||||||
|
|
||||||
root = Root(system=system)
|
root = Root(full_system=True, system=system)
|
||||||
m5.ticks.setGlobalFrequency('1THz')
|
m5.ticks.setGlobalFrequency('1THz')
|
||||||
|
|
|
@ -91,6 +91,6 @@ cpu.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1),
|
||||||
cpu.connectAllPorts(system.toL2Bus, system.membus)
|
cpu.connectAllPorts(system.toL2Bus, system.membus)
|
||||||
cpu.clock = '2GHz'
|
cpu.clock = '2GHz'
|
||||||
|
|
||||||
root = Root(system=system)
|
root = Root(full_system=True, system=system)
|
||||||
m5.ticks.setGlobalFrequency('1THz')
|
m5.ticks.setGlobalFrequency('1THz')
|
||||||
|
|
||||||
|
|
|
@ -93,7 +93,7 @@ for c in cpus:
|
||||||
c.connectAllPorts(system.toL2Bus, system.membus)
|
c.connectAllPorts(system.toL2Bus, system.membus)
|
||||||
c.clock = '2GHz'
|
c.clock = '2GHz'
|
||||||
|
|
||||||
root = Root(system=system)
|
root = Root(full_system=True, system=system)
|
||||||
m5.ticks.setGlobalFrequency('1THz')
|
m5.ticks.setGlobalFrequency('1THz')
|
||||||
|
|
||||||
|
|
||||||
|
|
|
@ -93,6 +93,6 @@ cpu.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1),
|
||||||
cpu.connectAllPorts(system.toL2Bus, system.membus)
|
cpu.connectAllPorts(system.toL2Bus, system.membus)
|
||||||
cpu.clock = '2GHz'
|
cpu.clock = '2GHz'
|
||||||
|
|
||||||
root = Root(system=system)
|
root = Root(full_system=True, system=system)
|
||||||
m5.ticks.setGlobalFrequency('1THz')
|
m5.ticks.setGlobalFrequency('1THz')
|
||||||
|
|
||||||
|
|
|
@ -53,6 +53,6 @@ drive_sys.iobridge = Bridge(delay='50ns', nack_delay='4ns',
|
||||||
drive_sys.iobridge.slave = drive_sys.iobus.port
|
drive_sys.iobridge.slave = drive_sys.iobus.port
|
||||||
drive_sys.iobridge.master = drive_sys.membus.port
|
drive_sys.iobridge.master = drive_sys.membus.port
|
||||||
|
|
||||||
root = makeDualRoot(test_sys, drive_sys, "ethertrace")
|
root = makeDualRoot(True, test_sys, drive_sys, "ethertrace")
|
||||||
|
|
||||||
maxtick = 199999999
|
maxtick = 199999999
|
||||||
|
|
Loading…
Reference in a new issue