arm, config: Add initial support for Ruby
Add initial support for creating an ARM system with a Ruby-based memory system. This support is currently experimental and limited to the new VExpress_GEM5_V1 platform. Change-Id: I36baeb68b0d891e34ea46aafe17b5e55217b4bfa Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Brad Beckmann <brad.beckmann@amd.com>
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2 changed files with 29 additions and 15 deletions
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@ -1,4 +1,4 @@
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# Copyright (c) 2010-2012, 2015 ARM Limited
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# Copyright (c) 2010-2012, 2015-2016 ARM Limited
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# All rights reserved.
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# All rights reserved.
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#
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#
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# The license below extends only to copyright in the software and shall
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# The license below extends only to copyright in the software and shall
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@ -203,7 +203,7 @@ def makeSparcSystem(mem_mode, mdesc=None, cmdline=None):
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def makeArmSystem(mem_mode, machine_type, num_cpus=1, mdesc=None,
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def makeArmSystem(mem_mode, machine_type, num_cpus=1, mdesc=None,
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dtb_filename=None, bare_metal=False, cmdline=None,
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dtb_filename=None, bare_metal=False, cmdline=None,
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external_memory=""):
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external_memory="", ruby=False):
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assert machine_type
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assert machine_type
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default_dtbs = {
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default_dtbs = {
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@ -233,10 +233,11 @@ def makeArmSystem(mem_mode, machine_type, num_cpus=1, mdesc=None,
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self.readfile = mdesc.script()
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self.readfile = mdesc.script()
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self.iobus = IOXBar()
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self.iobus = IOXBar()
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self.membus = MemBus()
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if not ruby:
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self.membus.badaddr_responder.warn_access = "warn"
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self.bridge = Bridge(delay='50ns')
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self.bridge = Bridge(delay='50ns')
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self.bridge.master = self.iobus.slave
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self.bridge.master = self.iobus.slave
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self.membus = MemBus()
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self.membus.badaddr_responder.warn_access = "warn"
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self.bridge.slave = self.membus.master
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self.bridge.slave = self.membus.master
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self.mem_mode = mem_mode
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self.mem_mode = mem_mode
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@ -318,7 +319,7 @@ def makeArmSystem(mem_mode, machine_type, num_cpus=1, mdesc=None,
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# iobus, as gem5's membus is only used for initialization and
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# iobus, as gem5's membus is only used for initialization and
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# SST doesn't use it. Attaching nvmem to iobus solves this issue.
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# SST doesn't use it. Attaching nvmem to iobus solves this issue.
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# During initialization, system_port -> membus -> iobus -> nvmem.
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# During initialization, system_port -> membus -> iobus -> nvmem.
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if external_memory:
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if external_memory or ruby:
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self.realview.setupBootLoader(self.iobus, self, binary)
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self.realview.setupBootLoader(self.iobus, self, binary)
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else:
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else:
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self.realview.setupBootLoader(self.membus, self, binary)
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self.realview.setupBootLoader(self.membus, self, binary)
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@ -366,19 +367,30 @@ def makeArmSystem(mem_mode, machine_type, num_cpus=1, mdesc=None,
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self.bridge.ranges = [self.realview.nvmem.range]
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self.bridge.ranges = [self.realview.nvmem.range]
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self.realview.attachOnChipIO(self.iobus)
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self.realview.attachOnChipIO(self.iobus)
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else:
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self.realview.attachOnChipIO(self.membus, self.bridge)
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# Attach off-chip devices
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# Attach off-chip devices
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self.realview.attachIO(self.iobus)
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self.realview.attachIO(self.iobus)
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elif ruby:
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self._dma_ports = [ ]
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self.realview.attachOnChipIO(self.iobus, dma_ports=self._dma_ports)
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# Force Ruby to treat the boot ROM as an IO device.
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self.realview.nvmem.in_addr_map = False
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self.realview.attachIO(self.iobus, dma_ports=self._dma_ports)
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else:
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self.realview.attachOnChipIO(self.membus, self.bridge)
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# Attach off-chip devices
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self.realview.attachIO(self.iobus)
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for dev_id, dev in enumerate(pci_devices):
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for dev_id, dev in enumerate(pci_devices):
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dev.pci_bus, dev.pci_dev, dev.pci_func = (0, dev_id + 1, 0)
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dev.pci_bus, dev.pci_dev, dev.pci_func = (0, dev_id + 1, 0)
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self.realview.attachPciDevice(dev, self.iobus)
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self.realview.attachPciDevice(
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dev, self.iobus,
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dma_ports=self._dma_ports if ruby else None)
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self.intrctrl = IntrControl()
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self.intrctrl = IntrControl()
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self.terminal = Terminal()
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self.terminal = Terminal()
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self.vncserver = VncServer()
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self.vncserver = VncServer()
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if not ruby:
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self.system_port = self.membus.slave
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self.system_port = self.membus.slave
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return self
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return self
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@ -1,4 +1,4 @@
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# Copyright (c) 2010-2013 ARM Limited
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# Copyright (c) 2010-2013, 2016 ARM Limited
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# All rights reserved.
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# All rights reserved.
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#
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#
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# The license below extends only to copyright in the software and shall
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# The license below extends only to copyright in the software and shall
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@ -99,7 +99,8 @@ def build_test_system(np):
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options.num_cpus, bm[0], options.dtb_filename,
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options.num_cpus, bm[0], options.dtb_filename,
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bare_metal=options.bare_metal,
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bare_metal=options.bare_metal,
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cmdline=cmdline,
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cmdline=cmdline,
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external_memory=options.external_memory_system)
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external_memory=options.external_memory_system,
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ruby=options.ruby)
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if options.enable_context_switch_stats_dump:
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if options.enable_context_switch_stats_dump:
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test_sys.enable_context_switch_stats_dump = True
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test_sys.enable_context_switch_stats_dump = True
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else:
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else:
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@ -172,10 +173,11 @@ def build_test_system(np):
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cpu.icache_port = test_sys.ruby._cpu_ports[i].slave
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cpu.icache_port = test_sys.ruby._cpu_ports[i].slave
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cpu.dcache_port = test_sys.ruby._cpu_ports[i].slave
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cpu.dcache_port = test_sys.ruby._cpu_ports[i].slave
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if buildEnv['TARGET_ISA'] == "x86":
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if buildEnv['TARGET_ISA'] in ("x86", "arm"):
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cpu.itb.walker.port = test_sys.ruby._cpu_ports[i].slave
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cpu.itb.walker.port = test_sys.ruby._cpu_ports[i].slave
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cpu.dtb.walker.port = test_sys.ruby._cpu_ports[i].slave
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cpu.dtb.walker.port = test_sys.ruby._cpu_ports[i].slave
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if buildEnv['TARGET_ISA'] in "x86":
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cpu.interrupts[0].pio = test_sys.ruby._cpu_ports[i].master
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cpu.interrupts[0].pio = test_sys.ruby._cpu_ports[i].master
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cpu.interrupts[0].int_master = test_sys.ruby._cpu_ports[i].slave
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cpu.interrupts[0].int_master = test_sys.ruby._cpu_ports[i].slave
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cpu.interrupts[0].int_slave = test_sys.ruby._cpu_ports[i].master
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cpu.interrupts[0].int_slave = test_sys.ruby._cpu_ports[i].master
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