Merge m5read@m5.eecs.umich.edu:/bk/m5

into zed.eecs.umich.edu:/z/benash/bk/m5

--HG--
extra : convert_revision : a27bb3737d8a7d5c1fadf27f4cb5018d0b6054da

cpu/base.cc

@@ -189,15 +189,15 @@ BaseCPU::registerExecContexts()
 {
     for (int i = 0; i < execContexts.size(); ++i) {
         ExecContext *xc = execContexts[i];
-        int cpu_id;
-
 #ifdef FULL_SYSTEM
-        cpu_id = system->registerExecContext(xc);
+        int id = params->cpu_id;
-#else
+        if (id != -1)
-        cpu_id = xc->process->registerExecContext(xc);
+            id += i;
-#endif
 
-        xc->cpu_id = cpu_id;
+        xc->cpu_id = system->registerExecContext(xc, id);
+#else
+        xc->cpu_id = xc->process->registerExecContext(xc);
+#endif
     }
 }
 

cpu/base.hh

@@ -111,6 +111,7 @@ class BaseCPU : public SimObject
         Tick functionTraceStart;
 #ifdef FULL_SYSTEM
         System *system;
+        int cpu_id;
 #endif
     };
 

cpu/o3/alpha_cpu_builder.cc

@@ -71,9 +71,9 @@ BEGIN_DECLARE_SIM_OBJECT_PARAMS(DerivAlphaFullCPU)
 
 #ifdef FULL_SYSTEM
 SimObjectParam<System *> system;
+Param<int> cpu_id;
 SimObjectParam<AlphaITB *> itb;
 SimObjectParam<AlphaDTB *> dtb;
-Param<int> mult;
 #else
 SimObjectVectorParam<Process *> workload;
 #endif // FULL_SYSTEM
@@ -164,9 +164,9 @@ BEGIN_INIT_SIM_OBJECT_PARAMS(DerivAlphaFullCPU)
 
 #ifdef FULL_SYSTEM
     INIT_PARAM(system, "System object"),
+    INIT_PARAM(cpu_id, "processor ID"),
     INIT_PARAM(itb, "Instruction translation buffer"),
     INIT_PARAM(dtb, "Data translation buffer"),
-    INIT_PARAM(mult, "System clock multiplier"),
 #else
     INIT_PARAM(workload, "Processes to run"),
 #endif // FULL_SYSTEM
@@ -274,9 +274,6 @@ CREATE_SIM_OBJECT(DerivAlphaFullCPU)
     DerivAlphaFullCPU *cpu;
 
 #ifdef FULL_SYSTEM
-    if (mult != 1)
-        panic("Processor clock multiplier must be 1?\n");
-
     // Full-system only supports a single thread for the moment.
     int actual_num_threads = 1;
 #else
@@ -300,6 +297,7 @@ CREATE_SIM_OBJECT(DerivAlphaFullCPU)
 
 #ifdef FULL_SYSTEM
     params.system = system;
+    params.cpu_id = cpu_id;
     params.itb = itb;
     params.dtb = dtb;
 #else

cpu/simple/cpu.cc

@@ -823,7 +823,7 @@ BEGIN_DECLARE_SIM_OBJECT_PARAMS(SimpleCPU)
     SimObjectParam<AlphaDTB *> dtb;
     SimObjectParam<FunctionalMemory *> mem;
     SimObjectParam<System *> system;
-    Param<int> mult;
+    Param<int> cpu_id;
 #else
     SimObjectParam<Process *> workload;
 #endif // FULL_SYSTEM
@@ -855,7 +855,7 @@ BEGIN_INIT_SIM_OBJECT_PARAMS(SimpleCPU)
     INIT_PARAM(dtb, "Data TLB"),
     INIT_PARAM(mem, "memory"),
     INIT_PARAM(system, "system object"),
-    INIT_PARAM(mult, "system clock multiplier"),
+    INIT_PARAM(cpu_id, "processor ID"),
 #else
     INIT_PARAM(workload, "processes to run"),
 #endif // FULL_SYSTEM
@@ -873,11 +873,6 @@ END_INIT_SIM_OBJECT_PARAMS(SimpleCPU)
 
 CREATE_SIM_OBJECT(SimpleCPU)
 {
-#ifdef FULL_SYSTEM
-    if (mult != 1)
-        panic("processor clock multiplier must be 1\n");
-#endif
-
     SimpleCPU::Params *params = new SimpleCPU::Params();
     params->name = getInstanceName();
     params->numberOfThreads = 1;
@@ -898,6 +893,7 @@ CREATE_SIM_OBJECT(SimpleCPU)
     params->dtb = dtb;
     params->mem = mem;
     params->system = system;
+    params->cpu_id = cpu_id;
 #else
     params->process = workload;
 #endif

dev/alpha_console.cc

@@ -56,7 +56,7 @@ using namespace std;
 
 AlphaConsole::AlphaConsole(const string &name, SimConsole *cons, SimpleDisk *d,
                            System *s, BaseCPU *c, Platform *p,
-                           int num_cpus, MemoryController *mmu, Addr a,
+                           MemoryController *mmu, Addr a,
                            HierParams *hier, Bus *bus)
     : PioDevice(name, p), disk(d), console(cons), system(s), cpu(c), addr(a)
 {
@@ -72,7 +72,6 @@ AlphaConsole::AlphaConsole(const string &name, SimConsole *cons, SimpleDisk *d,
     alphaAccess->last_offset = size - 1;
 
     alphaAccess->version = ALPHA_ACCESS_VERSION;
-    alphaAccess->numCPUs = num_cpus;
     alphaAccess->diskUnit = 1;
 
     alphaAccess->diskCount = 0;
@@ -89,8 +88,9 @@ AlphaConsole::AlphaConsole(const string &name, SimConsole *cons, SimpleDisk *d,
 }
 
 void
-AlphaConsole::init()
+AlphaConsole::startup()
 {
+    alphaAccess->numCPUs = system->getNumCPUs();
     alphaAccess->kernStart = system->getKernelStart();
     alphaAccess->kernEnd = system->getKernelEnd();
     alphaAccess->entryPoint = system->getKernelEntry();
@@ -330,7 +330,6 @@ BEGIN_DECLARE_SIM_OBJECT_PARAMS(AlphaConsole)
 
     SimObjectParam<SimConsole *> sim_console;
     SimObjectParam<SimpleDisk *> disk;
-    Param<int> num_cpus;
     SimObjectParam<MemoryController *> mmu;
     Param<Addr> addr;
     SimObjectParam<System *> system;
@@ -346,7 +345,6 @@ BEGIN_INIT_SIM_OBJECT_PARAMS(AlphaConsole)
 
     INIT_PARAM(sim_console, "The Simulator Console"),
     INIT_PARAM(disk, "Simple Disk"),
-    INIT_PARAM_DFLT(num_cpus, "Number of CPU's", 1),
     INIT_PARAM(mmu, "Memory Controller"),
     INIT_PARAM(addr, "Device Address"),
     INIT_PARAM(system, "system object"),
@@ -361,8 +359,7 @@ END_INIT_SIM_OBJECT_PARAMS(AlphaConsole)
 CREATE_SIM_OBJECT(AlphaConsole)
 {
     return new AlphaConsole(getInstanceName(), sim_console, disk,
-                            system, cpu, platform, num_cpus, mmu,
+                            system, cpu, platform, mmu, addr, hier, io_bus);
-                            addr, hier, io_bus);
 }
 
 REGISTER_SIM_OBJECT("AlphaConsole", AlphaConsole)

dev/alpha_console.hh

@@ -102,10 +102,10 @@ class AlphaConsole : public PioDevice
     /** Standard Constructor */
     AlphaConsole(const std::string &name, SimConsole *cons, SimpleDisk *d,
                  System *s, BaseCPU *c, Platform *platform,
-                 int num_cpus, MemoryController *mmu, Addr addr,
+                 MemoryController *mmu, Addr addr,
                  HierParams *hier, Bus *bus);
 
-    virtual void init();
+    virtual void startup();
 
     /**
      * memory mapped reads and writes

python/m5/objects/AlphaConsole.py

@@ -5,6 +5,5 @@ class AlphaConsole(PioDevice):
     type = 'AlphaConsole'
     cpu = Param.BaseCPU(Parent.any, "Processor")
     disk = Param.SimpleDisk("Simple Disk")
-    num_cpus = Param.Int(1, "Number of CPUs")
     sim_console = Param.SimConsole(Parent.any, "The Simulator Console")
     system = Param.System(Parent.any, "system object")

python/m5/objects/BaseCPU.py

@@ -10,6 +10,7 @@ class BaseCPU(SimObject):
         itb = Param.AlphaITB("Instruction TLB")
         mem = Param.FunctionalMemory("memory")
         system = Param.System(Parent.any, "system object")
+        cpu_id = Param.Int(-1, "CPU identifier")
     else:
         workload = VectorParam.Process("processes to run")
 

sim/system.cc

@@ -46,7 +46,7 @@ int System::numSystemsRunning = 0;
 
 System::System(Params *p)
     : SimObject(p->name), memctrl(p->memctrl), physmem(p->physmem),
-      init_param(p->init_param), params(p)
+      init_param(p->init_param), numcpus(0), params(p)
 {
     // add self to global system list
     systemList.push_back(this);
@@ -204,13 +204,26 @@ System::breakpoint()
 }
 
 int
-System::registerExecContext(ExecContext *xc)
+System::registerExecContext(ExecContext *xc, int id)
 {
-    int xcIndex = execContexts.size();
+    if (id == -1) {
-    execContexts.push_back(xc);
+        for (id = 0; id < execContexts.size(); id++) {
+            if (!execContexts[id])
+                break;
+        }
+    }
+
+    if (execContexts.size() <= id)
+        execContexts.resize(id + 1);
+
+    if (execContexts[id])
+        panic("Cannot have two CPUs with the same id (%d)\n", id);
+
+    execContexts[id] = xc;
+    numcpus++;
 
     RemoteGDB *rgdb = new RemoteGDB(this, xc);
-    GDBListener *gdbl = new GDBListener(rgdb, 7000 + xcIndex);
+    GDBListener *gdbl = new GDBListener(rgdb, 7000 + id);
     gdbl->listen();
     /**
      * Uncommenting this line waits for a remote debugger to connect
@@ -218,13 +231,13 @@ System::registerExecContext(ExecContext *xc)
      */
     //gdbl->accept();
 
-    if (remoteGDB.size() <= xcIndex) {
+    if (remoteGDB.size() <= id) {
-        remoteGDB.resize(xcIndex+1);
+        remoteGDB.resize(id + 1);
     }
 
-    remoteGDB[xcIndex] = rgdb;
+    remoteGDB[id] = rgdb;
 
-    return xcIndex;
+    return id;
 }
 
 void
@@ -238,15 +251,15 @@ System::startup()
 }
 
 void
-System::replaceExecContext(ExecContext *xc, int xcIndex)
+System::replaceExecContext(ExecContext *xc, int id)
 {
-    if (xcIndex >= execContexts.size()) {
+    if (id >= execContexts.size()) {
-        panic("replaceExecContext: bad xcIndex, %d >= %d\n",
+        panic("replaceExecContext: bad id, %d >= %d\n",
-              xcIndex, execContexts.size());
+              id, execContexts.size());
     }
 
-    execContexts[xcIndex] = xc;
+    execContexts[id] = xc;
-    remoteGDB[xcIndex]->replaceExecContext(xc);
+    remoteGDB[id]->replaceExecContext(xc);
 }
 
 void

sim/system.hh

@@ -58,6 +58,15 @@ class System : public SimObject
     uint64_t init_param;
 
     std::vector<ExecContext *> execContexts;
+    int numcpus;
+
+    int getNumCPUs()
+    {
+        if (numcpus != execContexts.size())
+            panic("cpu array not fully populated!");
+
+        return numcpus;
+    }
 
     /** kernel Symbol table */
     SymbolTable *kernelSymtab;
@@ -150,7 +159,7 @@ class System : public SimObject
      */
     Addr getKernelEntry() const { return kernelEntry; }
 
-    int registerExecContext(ExecContext *xc);
+    int registerExecContext(ExecContext *xc, int xcIndex);
     void replaceExecContext(ExecContext *xc, int xcIndex);
 
     void regStats();