cpu: Move the branch predictor out of the BaseCPU
The branch predictor is guarded by having either the in-order or out-of-order CPU as one of the available CPU models and therefore should not be used in the BaseCPU. This patch moves the parameter to the relevant CPU classes.
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3 changed files with 6 additions and 5 deletions
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@ -51,7 +51,6 @@ from Bus import CoherentBus
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from InstTracer import InstTracer
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from ExeTracer import ExeTracer
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from MemObject import MemObject
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from BranchPredictor import BranchPredictor
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from ClockDomain import *
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default_tracer = ExeTracer()
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@ -210,8 +209,6 @@ class BaseCPU(MemObject):
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dcache_port = MasterPort("Data Port")
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_cached_ports = ['icache_port', 'dcache_port']
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branchPred = Param.BranchPredictor(NULL, "Branch Predictor")
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if buildEnv['TARGET_ISA'] in ['x86', 'arm']:
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_cached_ports += ["itb.walker.port", "dtb.walker.port"]
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@ -68,4 +68,6 @@ class InOrderCPU(BaseCPU):
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div32Latency = Param.Cycles(1, "Latency for 32-bit Divide Operations")
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div32RepeatRate = Param.Cycles(1, "Repeat Rate for 32-bit Divide Operations")
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branchPred = BranchPredictor(numThreads = Parent.numThreads)
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branchPred = Param.BranchPredictor(BranchPredictor(numThreads =
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Parent.numThreads),
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"Branch Predictor")
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@ -125,7 +125,9 @@ class DerivO3CPU(BaseCPU):
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smtROBThreshold = Param.Int(100, "SMT ROB Threshold Sharing Parameter")
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smtCommitPolicy = Param.String('RoundRobin', "SMT Commit Policy")
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branchPred = BranchPredictor(numThreads = Parent.numThreads)
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branchPred = Param.BranchPredictor(BranchPredictor(numThreads =
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Parent.numThreads),
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"Branch Predictor")
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needsTSO = Param.Bool(buildEnv['TARGET_ISA'] == 'x86',
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"Enable TSO Memory model")
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