diff --git a/src/mem/CommMonitor.py b/src/mem/CommMonitor.py index 4e8cfe270..ba871357d 100644 --- a/src/mem/CommMonitor.py +++ b/src/mem/CommMonitor.py @@ -53,6 +53,13 @@ class CommMonitor(MemObject): master = MasterPort("Master port") slave = SlavePort("Slave port") + # Boolean to enable or disable the trace. Writes to an a file named based on + # SimObject hierarchy. + trace_enable = Param.Bool(False, "Enable trace capture") + + # Boolean to compress the trace or not. + trace_compress = Param.Bool(True, "Enable trace compression") + # packet trace output file, disabled by default trace_file = Param.String("", "Packet trace output file") diff --git a/src/mem/comm_monitor.cc b/src/mem/comm_monitor.cc index 70b8a6451..3bfaad289 100644 --- a/src/mem/comm_monitor.cc +++ b/src/mem/comm_monitor.cc @@ -58,11 +58,28 @@ CommMonitor::CommMonitor(Params* params) traceStream(NULL), system(params->system) { - // If we are using a trace file, then open the file, - if (params->trace_file != "") { - // If the trace file is not specified as an absolute path, - // append the current simulation output directory - std::string filename = simout.resolve(params->trace_file); + // If we are using a trace file, then open the file + if (params->trace_enable) { + std::string filename; + if (params->trace_file != "") { + // If the trace file is not specified as an absolute path, + // append the current simulation output directory + filename = simout.resolve(params->trace_file); + + std::string suffix = ".gz"; + // If trace_compress has been set, check the suffix. Append + // accordingly. + if (params->trace_compress && + filename.compare(filename.size() - suffix.size(), suffix.size(), + suffix) != 0) + filename = filename + suffix; + } else { + // Generate a filename from the name of the SimObject. Append .trc + // and .gz if we want compression enabled. + filename = simout.resolve(name() + ".trc" + + (params->trace_compress ? ".gz" : "")); + } + traceStream = new ProtoOutputStream(filename); // Create a protobuf message for the header and write it to diff --git a/tests/configs/tgen-simple-mem.py b/tests/configs/tgen-simple-mem.py index 5e241a25a..7fdeb9c12 100644 --- a/tests/configs/tgen-simple-mem.py +++ b/tests/configs/tgen-simple-mem.py @@ -55,7 +55,8 @@ system = System(cpu = cpu, physmem = SimpleMemory(), VoltageDomain())) # add a communication monitor, and also trace all the packets -system.monitor = CommMonitor(trace_file = "monitor.ptrc.gz") +system.monitor = CommMonitor(trace_file = "monitor.ptrc.gz", + trace_enable = True) # connect the traffic generator to the bus via a communication monitor system.cpu.port = system.monitor.slave