From 8d220c5c1024bc80c4f1365bc4ef542480acaac5 Mon Sep 17 00:00:00 2001 From: Kevin Lim Date: Wed, 2 Aug 2006 12:04:18 -0400 Subject: [PATCH 02/20] Updates for registers and stuff. arch/alpha/ev5.cc: Update for copying IPRs. arch/alpha/isa_traits.hh: Allow for misc register file to serialize. Also add some register copying code. cpu/cpu_exec_context.cc: Use ISA's function to copy registers. --HG-- extra : convert_revision : 09fa3b2b1b229cbf3a34f69354953da2607c2a8f --- arch/alpha/ev5.cc | 6 ++++-- arch/alpha/isa_traits.hh | 19 ++++++++++++++++++- cpu/cpu_exec_context.cc | 2 +- 3 files changed, 23 insertions(+), 4 deletions(-) diff --git a/arch/alpha/ev5.cc b/arch/alpha/ev5.cc index f113a2767..907bea92c 100644 --- a/arch/alpha/ev5.cc +++ b/arch/alpha/ev5.cc @@ -547,14 +547,16 @@ AlphaISA::MiscRegFile::setIpr(int idx, uint64_t val, ExecContext *xc) return NoFault; } + void -AlphaISA::MiscRegFile::copyIprs(ExecContext *xc) +AlphaISA::copyIprs(ExecContext *src, ExecContext *dest) { for (int i = IPR_Base_DepTag; i < NumInternalProcRegs; ++i) { - ipr[i] = xc->readMiscReg(i); + dest->setMiscReg(i, src->readMiscReg(i)); } } + /** * Check for special simulator handling of specific PAL calls. * If return value is false, actual PAL call will be suppressed. diff --git a/arch/alpha/isa_traits.hh b/arch/alpha/isa_traits.hh index 878193881..515ec933b 100644 --- a/arch/alpha/isa_traits.hh +++ b/arch/alpha/isa_traits.hh @@ -212,7 +212,16 @@ extern const int reg_redir[NumIntRegs]; Fault setRegWithEffect(int misc_reg, const MiscReg &val, ExecContext *xc); - void copyMiscRegs(ExecContext *xc); + void serialize(std::ostream &os); + + void unserialize(Checkpoint *cp, const std::string §ion); + + void clear() + { + fpcr = uniq = 0; + lock_flag = 0; + lock_addr = 0; + } #if FULL_SYSTEM protected: @@ -361,6 +370,14 @@ extern const int reg_redir[NumIntRegs]; } } #endif + + void copyRegs(ExecContext *src, ExecContext *dest); + + void copyMiscRegs(ExecContext *src, ExecContext *dest); + +#if FULL_SYSTEM + void copyIprs(ExecContext *src, ExecContext *dest); +#endif }; static inline AlphaISA::ExtMachInst diff --git a/cpu/cpu_exec_context.cc b/cpu/cpu_exec_context.cc index e30295ef8..e28c34f88 100644 --- a/cpu/cpu_exec_context.cc +++ b/cpu/cpu_exec_context.cc @@ -306,7 +306,7 @@ CPUExecContext::copyArchRegs(ExecContext *xc) } // Copy misc. registers - regs.miscRegs.copyMiscRegs(xc); + TheISA::copyMiscRegs(xc, proxy); // Lastly copy PC/NPC setPC(xc->readPC()); From cbfbb7bc56630ddefb95625a6da87b3c1da9599d Mon Sep 17 00:00:00 2001 From: Kevin Lim Date: Wed, 2 Aug 2006 12:05:34 -0400 Subject: [PATCH 03/20] Updates to bring CPU portion of m5 up-to-date with newmem. --HG-- extra : convert_revision : 00e6eefb24e6ffd9c7c5d8165db26fbf6199fdc4 --- base/timebuf.hh | 5 + cpu/base_dyn_inst.cc | 35 +---- cpu/base_dyn_inst.hh | 205 +++++++++++++---------------- cpu/o3/alpha_cpu_builder.cc | 33 ++--- cpu/o3/alpha_cpu_impl.hh | 2 +- cpu/o3/alpha_params.hh | 14 +- cpu/o3/commit.hh | 13 -- cpu/o3/commit_impl.hh | 62 +++------ cpu/o3/cpu.cc | 66 ++++++++-- cpu/o3/cpu.hh | 6 + cpu/o3/decode_impl.hh | 9 +- cpu/o3/fetch.hh | 6 + cpu/o3/fetch_impl.hh | 19 ++- cpu/o3/iew.hh | 107 ++++++++++----- cpu/o3/iew_impl.hh | 157 +++++++++++----------- cpu/o3/inst_queue.hh | 2 - cpu/o3/inst_queue_impl.hh | 23 +--- cpu/o3/lsq.hh | 3 + cpu/o3/lsq_impl.hh | 10 ++ cpu/o3/lsq_unit.hh | 53 +++++--- cpu/o3/lsq_unit_impl.hh | 47 ++++++- cpu/o3/mem_dep_unit.cc | 2 + cpu/o3/mem_dep_unit_impl.hh | 14 ++ cpu/o3/regfile.hh | 16 ++- cpu/o3/rename_impl.hh | 4 +- cpu/o3/rob.hh | 2 +- cpu/o3/rob_impl.hh | 14 +- cpu/ozone/cpu.hh | 45 ++++--- cpu/ozone/cpu_impl.hh | 53 ++++---- cpu/ozone/inorder_back_end_impl.hh | 2 +- cpu/ozone/inst_queue_impl.hh | 8 +- cpu/ozone/lw_back_end.hh | 78 +++++------ cpu/ozone/lw_back_end_impl.hh | 138 +++++++++---------- cpu/ozone/lw_lsq.hh | 2 +- cpu/ozone/thread_state.hh | 2 - cpu/thread_state.hh | 1 + python/m5/objects/AlphaFullCPU.py | 13 +- 37 files changed, 691 insertions(+), 580 deletions(-) diff --git a/base/timebuf.hh b/base/timebuf.hh index f6b5b2781..db34528d8 100644 --- a/base/timebuf.hh +++ b/base/timebuf.hh @@ -212,6 +212,11 @@ class TimeBuffer { return wire(this, 0); } + + int getSize() + { + return size; + } }; #endif // __BASE_TIMEBUF_HH__ diff --git a/cpu/base_dyn_inst.cc b/cpu/base_dyn_inst.cc index 64a995689..1a52279cc 100644 --- a/cpu/base_dyn_inst.cc +++ b/cpu/base_dyn_inst.cc @@ -100,32 +100,15 @@ BaseDynInst::initVars() readyRegs = 0; - completed = false; - resultReady = false; - canIssue = false; - issued = false; - executed = false; - canCommit = false; - committed = false; - squashed = false; - squashedInIQ = false; - squashedInLSQ = false; - squashedInROB = false; + instResult.integer = 0; + + status.reset(); + eaCalcDone = false; memOpDone = false; + lqIdx = -1; sqIdx = -1; - reachedCommit = false; - - blockingInst = false; - recoverInst = false; - - iqEntry = false; - robEntry = false; - - serializeBefore = false; - serializeAfter = false; - serializeHandled = false; // Eventually make this a parameter. threadNumber = 0; @@ -395,7 +378,7 @@ void BaseDynInst::markSrcRegReady() { if (++readyRegs == numSrcRegs()) { - canIssue = true; + status.set(CanIssue); } } @@ -403,13 +386,9 @@ template void BaseDynInst::markSrcRegReady(RegIndex src_idx) { - ++readyRegs; - _readySrcRegIdx[src_idx] = true; - if (readyRegs == numSrcRegs()) { - canIssue = true; - } + markSrcRegReady(); } template diff --git a/cpu/base_dyn_inst.hh b/cpu/base_dyn_inst.hh index 388ea4a8d..01f6be185 100644 --- a/cpu/base_dyn_inst.hh +++ b/cpu/base_dyn_inst.hh @@ -127,56 +127,34 @@ class BaseDynInst : public FastAlloc, public RefCounted /** The sequence number of the instruction. */ InstSeqNum seqNum; - /** Is the instruction in the IQ */ - bool iqEntry; + enum Status { + IqEntry, /// Instruction is in the IQ + RobEntry, /// Instruction is in the ROB + LsqEntry, /// Instruction is in the LSQ + Completed, /// Instruction has completed + ResultReady, /// Instruction has its result + CanIssue, /// Instruction can issue and execute + Issued, /// Instruction has issued + Executed, /// Instruction has executed + CanCommit, /// Instruction can commit + AtCommit, /// Instruction has reached commit + Committed, /// Instruction has committed + Squashed, /// Instruction is squashed + SquashedInIQ, /// Instruction is squashed in the IQ + SquashedInLSQ, /// Instruction is squashed in the LSQ + SquashedInROB, /// Instruction is squashed in the ROB + RecoverInst, /// Is a recover instruction + BlockingInst, /// Is a blocking instruction + ThreadsyncWait, /// Is a thread synchronization instruction + SerializeBefore, /// Needs to serialize on + /// instructions ahead of it + SerializeAfter, /// Needs to serialize instructions behind it + SerializeHandled, /// Serialization has been handled + NumStatus + }; - /** Is the instruction in the ROB */ - bool robEntry; - - /** Is the instruction in the LSQ */ - bool lsqEntry; - - /** Is the instruction completed. */ - bool completed; - - /** Is the instruction's result ready. */ - bool resultReady; - - /** Can this instruction issue. */ - bool canIssue; - - /** Has this instruction issued. */ - bool issued; - - /** Has this instruction executed (or made it through execute) yet. */ - bool executed; - - /** Can this instruction commit. */ - bool canCommit; - - /** Is this instruction committed. */ - bool committed; - - /** Is this instruction squashed. */ - bool squashed; - - /** Is this instruction squashed in the instruction queue. */ - bool squashedInIQ; - - /** Is this instruction squashed in the instruction queue. */ - bool squashedInLSQ; - - /** Is this instruction squashed in the instruction queue. */ - bool squashedInROB; - - /** Is this a recover instruction. */ - bool recoverInst; - - /** Is this a thread blocking instruction. */ - bool blockingInst; /* this inst has called thread_block() */ - - /** Is this a thread syncrhonization instruction. */ - bool threadsyncWait; + /** The status of this BaseDynInst. Several bits can be set. */ + std::bitset status; /** The thread this instruction is from. */ short threadNumber; @@ -351,9 +329,9 @@ class BaseDynInst : public FastAlloc, public RefCounted bool isThreadSync() const { return staticInst->isThreadSync(); } bool isSerializing() const { return staticInst->isSerializing(); } bool isSerializeBefore() const - { return staticInst->isSerializeBefore() || serializeBefore; } + { return staticInst->isSerializeBefore() || status[SerializeBefore]; } bool isSerializeAfter() const - { return staticInst->isSerializeAfter() || serializeAfter; } + { return staticInst->isSerializeAfter() || status[SerializeAfter]; } bool isMemBarrier() const { return staticInst->isMemBarrier(); } bool isWriteBarrier() const { return staticInst->isWriteBarrier(); } bool isNonSpeculative() const { return staticInst->isNonSpeculative(); } @@ -362,41 +340,32 @@ class BaseDynInst : public FastAlloc, public RefCounted bool isUnverifiable() const { return staticInst->isUnverifiable(); } /** Temporarily sets this instruction as a serialize before instruction. */ - void setSerializeBefore() { serializeBefore = true; } + void setSerializeBefore() { status.set(SerializeBefore); } /** Clears the serializeBefore part of this instruction. */ - void clearSerializeBefore() { serializeBefore = false; } + void clearSerializeBefore() { status.reset(SerializeBefore); } /** Checks if this serializeBefore is only temporarily set. */ - bool isTempSerializeBefore() { return serializeBefore; } - - /** Tracks if instruction has been externally set as serializeBefore. */ - bool serializeBefore; + bool isTempSerializeBefore() { return status[SerializeBefore]; } /** Temporarily sets this instruction as a serialize after instruction. */ - void setSerializeAfter() { serializeAfter = true; } + void setSerializeAfter() { status.set(SerializeAfter); } /** Clears the serializeAfter part of this instruction.*/ - void clearSerializeAfter() { serializeAfter = false; } + void clearSerializeAfter() { status.reset(SerializeAfter); } /** Checks if this serializeAfter is only temporarily set. */ - bool isTempSerializeAfter() { return serializeAfter; } + bool isTempSerializeAfter() { return status[SerializeAfter]; } - /** Tracks if instruction has been externally set as serializeAfter. */ - bool serializeAfter; + /** Sets the serialization part of this instruction as handled. */ + void setSerializeHandled() { status.set(SerializeHandled); } /** Checks if the serialization part of this instruction has been * handled. This does not apply to the temporary serializing * state; it only applies to this instruction's own permanent * serializing state. */ - bool isSerializeHandled() { return serializeHandled; } - - /** Sets the serialization part of this instruction as handled. */ - void setSerializeHandled() { serializeHandled = true; } - - /** Whether or not the serialization of this instruction has been handled. */ - bool serializeHandled; + bool isSerializeHandled() { return status[SerializeHandled]; } /** Returns the opclass of this instruction. */ OpClass opClass() const { return staticInst->opClass(); } @@ -463,106 +432,112 @@ class BaseDynInst : public FastAlloc, public RefCounted } /** Sets this instruction as completed. */ - void setCompleted() { completed = true; } + void setCompleted() { status.set(Completed); } /** Returns whether or not this instruction is completed. */ - bool isCompleted() const { return completed; } + bool isCompleted() const { return status[Completed]; } - void setResultReady() { resultReady = true; } + /** Marks the result as ready. */ + void setResultReady() { status.set(ResultReady); } - bool isResultReady() const { return resultReady; } + /** Returns whether or not the result is ready. */ + bool isResultReady() const { return status[ResultReady]; } /** Sets this instruction as ready to issue. */ - void setCanIssue() { canIssue = true; } + void setCanIssue() { status.set(CanIssue); } /** Returns whether or not this instruction is ready to issue. */ - bool readyToIssue() const { return canIssue; } + bool readyToIssue() const { return status[CanIssue]; } /** Sets this instruction as issued from the IQ. */ - void setIssued() { issued = true; } + void setIssued() { status.set(Issued); } /** Returns whether or not this instruction has issued. */ - bool isIssued() const { return issued; } + bool isIssued() const { return status[Issued]; } /** Sets this instruction as executed. */ - void setExecuted() { executed = true; } + void setExecuted() { status.set(Executed); } /** Returns whether or not this instruction has executed. */ - bool isExecuted() const { return executed; } + bool isExecuted() const { return status[Executed]; } /** Sets this instruction as ready to commit. */ - void setCanCommit() { canCommit = true; } + void setCanCommit() { status.set(CanCommit); } /** Clears this instruction as being ready to commit. */ - void clearCanCommit() { canCommit = false; } + void clearCanCommit() { status.reset(CanCommit); } /** Returns whether or not this instruction is ready to commit. */ - bool readyToCommit() const { return canCommit; } + bool readyToCommit() const { return status[CanCommit]; } + + void setAtCommit() { status.set(AtCommit); } + + bool isAtCommit() { return status[AtCommit]; } /** Sets this instruction as committed. */ - void setCommitted() { committed = true; } + void setCommitted() { status.set(Committed); } /** Returns whether or not this instruction is committed. */ - bool isCommitted() const { return committed; } + bool isCommitted() const { return status[Committed]; } /** Sets this instruction as squashed. */ - void setSquashed() { squashed = true; } + void setSquashed() { status.set(Squashed); } /** Returns whether or not this instruction is squashed. */ - bool isSquashed() const { return squashed; } + bool isSquashed() const { return status[Squashed]; } //Instruction Queue Entry //----------------------- /** Sets this instruction as a entry the IQ. */ - void setInIQ() { iqEntry = true; } + void setInIQ() { status.set(IqEntry); } /** Sets this instruction as a entry the IQ. */ - void removeInIQ() { iqEntry = false; } - - /** Sets this instruction as squashed in the IQ. */ - void setSquashedInIQ() { squashedInIQ = true; squashed = true;} - - /** Returns whether or not this instruction is squashed in the IQ. */ - bool isSquashedInIQ() const { return squashedInIQ; } + void clearInIQ() { status.reset(IqEntry); } /** Returns whether or not this instruction has issued. */ - bool isInIQ() const { return iqEntry; } + bool isInIQ() const { return status[IqEntry]; } + + /** Sets this instruction as squashed in the IQ. */ + void setSquashedInIQ() { status.set(SquashedInIQ); status.set(Squashed);} + + /** Returns whether or not this instruction is squashed in the IQ. */ + bool isSquashedInIQ() const { return status[SquashedInIQ]; } //Load / Store Queue Functions //----------------------- /** Sets this instruction as a entry the LSQ. */ - void setInLSQ() { lsqEntry = true; } + void setInLSQ() { status.set(LsqEntry); } /** Sets this instruction as a entry the LSQ. */ - void removeInLSQ() { lsqEntry = false; } - - /** Sets this instruction as squashed in the LSQ. */ - void setSquashedInLSQ() { squashedInLSQ = true;} - - /** Returns whether or not this instruction is squashed in the LSQ. */ - bool isSquashedInLSQ() const { return squashedInLSQ; } + void removeInLSQ() { status.reset(LsqEntry); } /** Returns whether or not this instruction is in the LSQ. */ - bool isInLSQ() const { return lsqEntry; } + bool isInLSQ() const { return status[LsqEntry]; } + + /** Sets this instruction as squashed in the LSQ. */ + void setSquashedInLSQ() { status.set(SquashedInLSQ);} + + /** Returns whether or not this instruction is squashed in the LSQ. */ + bool isSquashedInLSQ() const { return status[SquashedInLSQ]; } //Reorder Buffer Functions //----------------------- /** Sets this instruction as a entry the ROB. */ - void setInROB() { robEntry = true; } + void setInROB() { status.set(RobEntry); } /** Sets this instruction as a entry the ROB. */ - void removeInROB() { robEntry = false; } - - /** Sets this instruction as squashed in the ROB. */ - void setSquashedInROB() { squashedInROB = true; } - - /** Returns whether or not this instruction is squashed in the ROB. */ - bool isSquashedInROB() const { return squashedInROB; } + void clearInROB() { status.reset(RobEntry); } /** Returns whether or not this instruction is in the ROB. */ - bool isInROB() const { return robEntry; } + bool isInROB() const { return status[RobEntry]; } + + /** Sets this instruction as squashed in the ROB. */ + void setSquashedInROB() { status.set(SquashedInROB); } + + /** Returns whether or not this instruction is squashed in the ROB. */ + bool isSquashedInROB() const { return status[SquashedInROB]; } /** Read the PC of this instruction. */ const Addr readPC() const { return PC; } @@ -619,8 +594,6 @@ class BaseDynInst : public FastAlloc, public RefCounted /** Store queue index. */ int16_t sqIdx; - bool reachedCommit; - /** Iterator pointing to this BaseDynInst in the list of all insts. */ ListIt instListIt; @@ -636,7 +609,7 @@ template inline Fault BaseDynInst::read(Addr addr, T &data, unsigned flags) { - if (executed) { + if (status[Executed]) { fault = cpu->read(req, data, lqIdx); return fault; } diff --git a/cpu/o3/alpha_cpu_builder.cc b/cpu/o3/alpha_cpu_builder.cc index 08d42cd46..c563fbef3 100644 --- a/cpu/o3/alpha_cpu_builder.cc +++ b/cpu/o3/alpha_cpu_builder.cc @@ -94,12 +94,10 @@ Param renameWidth; Param commitToIEWDelay; Param renameToIEWDelay; Param issueToExecuteDelay; +Param dispatchWidth; Param issueWidth; -Param executeWidth; -Param executeIntWidth; -Param executeFloatWidth; -Param executeBranchWidth; -Param executeMemoryWidth; +Param wbWidth; +Param wbDepth; SimObjectParam fuPool; Param iewToCommitDelay; @@ -109,6 +107,9 @@ Param squashWidth; Param trapLatency; Param fetchTrapLatency; +Param backComSize; +Param forwardComSize; + Param predType; Param localPredictorSize; Param localCtrBits; @@ -219,12 +220,10 @@ BEGIN_INIT_SIM_OBJECT_PARAMS(DerivAlphaFullCPU) "Issue/Execute/Writeback delay"), INIT_PARAM(issueToExecuteDelay, "Issue to execute delay (internal" "to the IEW stage)"), + INIT_PARAM(dispatchWidth, "Dispatch width"), INIT_PARAM(issueWidth, "Issue width"), - INIT_PARAM(executeWidth, "Execute width"), - INIT_PARAM(executeIntWidth, "Integer execute width"), - INIT_PARAM(executeFloatWidth, "Floating point execute width"), - INIT_PARAM(executeBranchWidth, "Branch execute width"), - INIT_PARAM(executeMemoryWidth, "Memory execute width"), + INIT_PARAM(wbWidth, "Writeback width"), + INIT_PARAM(wbDepth, "Writeback depth (number of cycles it can buffer)"), INIT_PARAM_DFLT(fuPool, "Functional unit pool", NULL), INIT_PARAM(iewToCommitDelay, "Issue/Execute/Writeback to commit " @@ -235,6 +234,9 @@ BEGIN_INIT_SIM_OBJECT_PARAMS(DerivAlphaFullCPU) INIT_PARAM_DFLT(trapLatency, "Number of cycles before the trap is handled", 6), INIT_PARAM_DFLT(fetchTrapLatency, "Number of cycles before the fetch trap is handled", 12), + INIT_PARAM(backComSize, "Time buffer size for backwards communication"), + INIT_PARAM(forwardComSize, "Time buffer size for forward communication"), + INIT_PARAM(predType, "Type of branch predictor ('local', 'tournament')"), INIT_PARAM(localPredictorSize, "Size of local predictor"), INIT_PARAM(localCtrBits, "Bits per counter"), @@ -353,12 +355,10 @@ CREATE_SIM_OBJECT(DerivAlphaFullCPU) params->commitToIEWDelay = commitToIEWDelay; params->renameToIEWDelay = renameToIEWDelay; params->issueToExecuteDelay = issueToExecuteDelay; + params->dispatchWidth = dispatchWidth; params->issueWidth = issueWidth; - params->executeWidth = executeWidth; - params->executeIntWidth = executeIntWidth; - params->executeFloatWidth = executeFloatWidth; - params->executeBranchWidth = executeBranchWidth; - params->executeMemoryWidth = executeMemoryWidth; + params->wbWidth = wbWidth; + params->wbDepth = wbDepth; params->fuPool = fuPool; params->iewToCommitDelay = iewToCommitDelay; @@ -368,6 +368,9 @@ CREATE_SIM_OBJECT(DerivAlphaFullCPU) params->trapLatency = trapLatency; params->fetchTrapLatency = fetchTrapLatency; + params->backComSize = backComSize; + params->forwardComSize = forwardComSize; + params->predType = predType; params->localPredictorSize = localPredictorSize; params->localCtrBits = localCtrBits; diff --git a/cpu/o3/alpha_cpu_impl.hh b/cpu/o3/alpha_cpu_impl.hh index f39fdf6b6..1bf0652cd 100644 --- a/cpu/o3/alpha_cpu_impl.hh +++ b/cpu/o3/alpha_cpu_impl.hh @@ -383,7 +383,7 @@ AlphaFullCPU::AlphaXC::copyArchRegs(ExecContext *xc) } // Copy the misc regs. - cpu->regFile.miscRegs[tid].copyMiscRegs(xc); + TheISA::copyMiscRegs(xc, this); // Then finally set the PC and the next PC. cpu->setPC(xc->readPC(), tid); diff --git a/cpu/o3/alpha_params.hh b/cpu/o3/alpha_params.hh index f0836a9fd..4ab130d02 100644 --- a/cpu/o3/alpha_params.hh +++ b/cpu/o3/alpha_params.hh @@ -106,12 +106,10 @@ class AlphaSimpleParams : public BaseFullCPU::Params unsigned commitToIEWDelay; unsigned renameToIEWDelay; unsigned issueToExecuteDelay; + unsigned dispatchWidth; unsigned issueWidth; - unsigned executeWidth; - unsigned executeIntWidth; - unsigned executeFloatWidth; - unsigned executeBranchWidth; - unsigned executeMemoryWidth; + unsigned wbWidth; + unsigned wbDepth; FUPool *fuPool; // @@ -124,6 +122,12 @@ class AlphaSimpleParams : public BaseFullCPU::Params Tick trapLatency; Tick fetchTrapLatency; + // + // Timebuffer sizes + // + unsigned backComSize; + unsigned forwardComSize; + // // Branch predictor (BP, BTB, RAS) // diff --git a/cpu/o3/commit.hh b/cpu/o3/commit.hh index d93822394..b153effc4 100644 --- a/cpu/o3/commit.hh +++ b/cpu/o3/commit.hh @@ -160,10 +160,6 @@ class DefaultCommit /** Sets the pointer to the queue coming from IEW. */ void setIEWQueue(TimeBuffer *iq_ptr); - void setFetchStage(Fetch *fetch_stage); - - Fetch *fetchStage; - /** Sets the pointer to the IEW stage. */ void setIEWStage(IEW *iew_stage); @@ -367,11 +363,6 @@ class DefaultCommit */ unsigned renameWidth; - /** IEW width, in instructions. Used so ROB knows how many - * instructions to get from the IEW instruction queue. - */ - unsigned iewWidth; - /** Commit width, in instructions. */ unsigned commitWidth; @@ -392,10 +383,6 @@ class DefaultCommit */ Tick trapLatency; - Tick fetchTrapLatency; - - Tick fetchFaultTick; - /** The commit PC of each thread. Refers to the instruction that * is currently being processed/committed. */ diff --git a/cpu/o3/commit_impl.hh b/cpu/o3/commit_impl.hh index 798f30294..364e685c2 100644 --- a/cpu/o3/commit_impl.hh +++ b/cpu/o3/commit_impl.hh @@ -71,12 +71,10 @@ DefaultCommit::DefaultCommit(Params *params) renameToROBDelay(params->renameToROBDelay), fetchToCommitDelay(params->commitToFetchDelay), renameWidth(params->renameWidth), - iewWidth(params->executeWidth), commitWidth(params->commitWidth), numThreads(params->numberOfThreads), switchedOut(false), - trapLatency(params->trapLatency), - fetchTrapLatency(params->fetchTrapLatency) + trapLatency(params->trapLatency) { _status = Active; _nextStatus = Inactive; @@ -114,10 +112,8 @@ DefaultCommit::DefaultCommit(Params *params) changedROBNumEntries[i] = false; trapSquash[i] = false; xcSquash[i] = false; + PC[i] = nextPC[i] = 0; } - - fetchFaultTick = 0; - fetchTrapWait = 0; } template @@ -240,7 +236,6 @@ DefaultCommit::setCPU(FullCPU *cpu_ptr) cpu->activateStage(FullCPU::CommitIdx); trapLatency = cpu->cycles(trapLatency); - fetchTrapLatency = cpu->cycles(fetchTrapLatency); } template @@ -297,13 +292,6 @@ DefaultCommit::setIEWQueue(TimeBuffer *iq_ptr) fromIEW = iewQueue->getWire(-iewToCommitDelay); } -template -void -DefaultCommit::setFetchStage(Fetch *fetch_stage) -{ - fetchStage = fetch_stage; -} - template void DefaultCommit::setIEWStage(IEW *iew_stage) @@ -431,7 +419,7 @@ DefaultCommit::setNextStatus() } } - assert(squashes == squashCounter); + squashCounter = squashes; // If commit is currently squashing, then it will have activity for the // next cycle. Set its next status as active. @@ -536,8 +524,6 @@ DefaultCommit::squashFromTrap(unsigned tid) commitStatus[tid] = ROBSquashing; cpu->activityThisCycle(); - - ++squashCounter; } template @@ -555,8 +541,6 @@ DefaultCommit::squashFromXC(unsigned tid) cpu->activityThisCycle(); xcSquash[tid] = false; - - ++squashCounter; } template @@ -571,6 +555,9 @@ DefaultCommit::tick() return; } + if ((*activeThreads).size() <=0) + return; + list::iterator threads = (*activeThreads).begin(); // Check if any of the threads are done squashing. Change the @@ -582,10 +569,12 @@ DefaultCommit::tick() if (rob->isDoneSquashing(tid)) { commitStatus[tid] = Running; - --squashCounter; } else { DPRINTF(Commit,"[tid:%u]: Still Squashing, cannot commit any" - "insts this cycle.\n", tid); + " insts this cycle.\n", tid); + rob->doSquash(tid); + toIEW->commitInfo[tid].robSquashing = true; + wroteToTimeBuffer = true; } } } @@ -691,29 +680,7 @@ DefaultCommit::commit() while (threads != (*activeThreads).end()) { unsigned tid = *threads++; -/* - if (fromFetch->fetchFault && commitStatus[0] != TrapPending) { - // Record the fault. Wait until it's empty in the ROB. - // Then handle the trap. Ignore it if there's already a - // trap pending as fetch will be redirected. - fetchFault = fromFetch->fetchFault; - fetchFaultTick = curTick + fetchTrapLatency; - commitStatus[0] = FetchTrapPending; - DPRINTF(Commit, "Fault from fetch recorded. Will trap if the " - "ROB empties without squashing the fault.\n"); - fetchTrapWait = 0; - } - // Fetch may tell commit to clear the trap if it's been squashed. - if (fromFetch->clearFetchFault) { - DPRINTF(Commit, "Received clear fetch fault signal\n"); - fetchTrapWait = 0; - if (commitStatus[0] == FetchTrapPending) { - DPRINTF(Commit, "Clearing fault from fetch\n"); - commitStatus[0] = Running; - } - } -*/ // Not sure which one takes priority. I think if we have // both, that's a bad sign. if (trapSquash[tid] == true) { @@ -741,8 +708,6 @@ DefaultCommit::commit() commitStatus[tid] = ROBSquashing; - ++squashCounter; - // If we want to include the squashing instruction in the squash, // then use one older sequence number. InstSeqNum squashed_inst = fromIEW->squashedSeqNum[tid]; @@ -944,7 +909,7 @@ DefaultCommit::commitHead(DynInstPtr &head_inst, unsigned inst_num) // and committed this instruction. thread[tid]->funcExeInst--; - head_inst->reachedCommit = true; + head_inst->setAtCommit(); if (head_inst->isNonSpeculative() || head_inst->isStoreConditional() || @@ -1060,7 +1025,7 @@ DefaultCommit::commitHead(DynInstPtr &head_inst, unsigned inst_num) // Generate trap squash event. generateTrapEvent(tid); - +// warn("%lli fault (%d) handled @ PC %08p", curTick, inst_fault->name(), head_inst->readPC()); return false; #else // !FULL_SYSTEM panic("fault (%d) detected @ PC %08p", inst_fault, @@ -1083,6 +1048,9 @@ DefaultCommit::commitHead(DynInstPtr &head_inst, unsigned inst_num) head_inst->renamedDestRegIdx(i)); } + if (head_inst->isCopy()) + panic("Should not commit any copy instructions!"); + // Finally clear the head ROB entry. rob->retireHead(tid); diff --git a/cpu/o3/cpu.cc b/cpu/o3/cpu.cc index 8d72bdc41..f1571e61b 100644 --- a/cpu/o3/cpu.cc +++ b/cpu/o3/cpu.cc @@ -108,12 +108,14 @@ FullO3CPU::FullO3CPU(Params *params) // For now just have these time buffers be pretty big. // @todo: Make these time buffer sizes parameters or derived // from latencies - timeBuffer(5, 5), - fetchQueue(5, 5), - decodeQueue(5, 5), - renameQueue(5, 5), - iewQueue(5, 5), - activityRec(NumStages, 10, params->activity), + timeBuffer(params->backComSize, params->forwardComSize), + fetchQueue(params->backComSize, params->forwardComSize), + decodeQueue(params->backComSize, params->forwardComSize), + renameQueue(params->backComSize, params->forwardComSize), + iewQueue(params->backComSize, params->forwardComSize), + activityRec(NumStages, + params->backComSize + params->forwardComSize, + params->activity), globalSeqNum(1), @@ -180,7 +182,6 @@ FullO3CPU::FullO3CPU(Params *params) commit.setIEWQueue(&iewQueue); commit.setRenameQueue(&renameQueue); - commit.setFetchStage(&fetch); commit.setIEWStage(&iew); rename.setIEWStage(&iew); rename.setCommitStage(&commit); @@ -709,7 +710,7 @@ void FullO3CPU::takeOverFrom(BaseCPU *oldCPU) { // Flush out any old data from the time buffers. - for (int i = 0; i < 10; ++i) { + for (int i = 0; i < timeBuffer.getSize(); ++i) { timeBuffer.advance(); fetchQueue.advance(); decodeQueue.advance(); @@ -758,6 +759,46 @@ FullO3CPU::takeOverFrom(BaseCPU *oldCPU) tickEvent.schedule(curTick); } +/* +template +void +FullO3CPU::serialize(std::ostream &os) +{ + BaseCPU::serialize(os); + nameOut(os, csprintf("%s.tickEvent", name())); + tickEvent.serialize(os); + + // Use SimpleThread's ability to checkpoint to make it easier to + // write out the registers. Also make this static so it doesn't + // get instantiated multiple times (causes a panic in statistics). + static SimpleThread temp; + + for (int i = 0; i < thread.size(); i++) { + nameOut(os, csprintf("%s.xc.%i", name(), i)); + temp.copyXC(thread[i]->getXC()); + temp.serialize(os); + } +} + +template +void +FullO3CPU::unserialize(Checkpoint *cp, const std::string §ion) +{ + BaseCPU::unserialize(cp, section); + tickEvent.unserialize(cp, csprintf("%s.tickEvent", section)); + + // Use SimpleThread's ability to checkpoint to make it easier to + // read in the registers. Also make this static so it doesn't + // get instantiated multiple times (causes a panic in statistics). + static SimpleThread temp; + + for (int i = 0; i < thread.size(); i++) { + temp.copyXC(thread[i]->getXC()); + temp.unserialize(cp, csprintf("%s.xc.%i", section, i)); + thread[i]->getXC()->copyArchRegs(temp.getXC()); + } +} +*/ template uint64_t FullO3CPU::readIntReg(int reg_idx) @@ -866,7 +907,8 @@ template void FullO3CPU::setArchFloatRegSingle(int reg_idx, float val, unsigned tid) { - PhysRegIndex phys_reg = commitRenameMap[tid].lookup(reg_idx); + int idx = reg_idx + TheISA::FP_Base_DepTag; + PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx); regFile.setFloatRegSingle(phys_reg, val); } @@ -875,7 +917,8 @@ template void FullO3CPU::setArchFloatRegDouble(int reg_idx, double val, unsigned tid) { - PhysRegIndex phys_reg = commitRenameMap[tid].lookup(reg_idx); + int idx = reg_idx + TheISA::FP_Base_DepTag; + PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx); regFile.setFloatRegDouble(phys_reg, val); } @@ -884,7 +927,8 @@ template void FullO3CPU::setArchFloatRegInt(int reg_idx, uint64_t val, unsigned tid) { - PhysRegIndex phys_reg = commitRenameMap[tid].lookup(reg_idx); + int idx = reg_idx + TheISA::FP_Base_DepTag; + PhysRegIndex phys_reg = commitRenameMap[tid].lookup(idx); regFile.setFloatRegInt(phys_reg, val); } diff --git a/cpu/o3/cpu.hh b/cpu/o3/cpu.hh index f4b19bfb3..ef5c9ae53 100644 --- a/cpu/o3/cpu.hh +++ b/cpu/o3/cpu.hh @@ -63,6 +63,12 @@ class BaseFullCPU : public BaseCPU void regStats(); + /** Sets this CPU's ID. */ + void setCpuId(int id) { cpu_id = id; } + + /** Reads this CPU's ID. */ + int readCpuId() { return cpu_id; } + protected: int cpu_id; }; diff --git a/cpu/o3/decode_impl.hh b/cpu/o3/decode_impl.hh index 0b686375e..e1af4d423 100644 --- a/cpu/o3/decode_impl.hh +++ b/cpu/o3/decode_impl.hh @@ -278,7 +278,7 @@ DefaultDecode::squash(DynInstPtr &inst, unsigned tid) toFetch->decodeInfo[tid].doneSeqNum = inst->seqNum; toFetch->decodeInfo[tid].predIncorrect = true; toFetch->decodeInfo[tid].squash = true; - toFetch->decodeInfo[tid].nextPC = inst->readNextPC(); + toFetch->decodeInfo[tid].nextPC = inst->branchTarget(); toFetch->decodeInfo[tid].branchTaken = inst->readNextPC() != (inst->readPC() + sizeof(TheISA::MachInst)); @@ -294,7 +294,7 @@ DefaultDecode::squash(DynInstPtr &inst, unsigned tid) for (int i=0; isize; i++) { if (fromFetch->insts[i]->threadNumber == tid && fromFetch->insts[i]->seqNum > inst->seqNum) { - fromFetch->insts[i]->squashed = true; + fromFetch->insts[i]->setSquashed(); } } @@ -343,7 +343,7 @@ DefaultDecode::squash(unsigned tid) for (int i=0; isize; i++) { if (fromFetch->insts[i]->threadNumber == tid) { - fromFetch->insts[i]->squashed = true; + fromFetch->insts[i]->setSquashed(); squash_count++; } } @@ -721,9 +721,8 @@ DefaultDecode::decodeInsts(unsigned tid) // Go ahead and compute any PC-relative branches. if (inst->isDirectCtrl() && inst->isUncondCtrl()) { ++decodeBranchResolved; - inst->setNextPC(inst->branchTarget()); - if (inst->mispredicted()) { + if (inst->branchTarget() != inst->readPredTarg()) { ++decodeBranchMispred; // Might want to set some sort of boolean and just do diff --git a/cpu/o3/fetch.hh b/cpu/o3/fetch.hh index 92a87ab54..0bde56ce9 100644 --- a/cpu/o3/fetch.hh +++ b/cpu/o3/fetch.hh @@ -358,6 +358,12 @@ class DefaultFetch /** The cache line being fetched. */ uint8_t *cacheData[Impl::MaxThreads]; + /** The PC of the cacheline that has been loaded. */ + Addr cacheDataPC[Impl::MaxThreads]; + + /** Whether or not the cache data is valid. */ + bool cacheDataValid[Impl::MaxThreads]; + /** Size of instructions. */ int instSize; diff --git a/cpu/o3/fetch_impl.hh b/cpu/o3/fetch_impl.hh index a309bd49a..cc09c4a41 100644 --- a/cpu/o3/fetch_impl.hh +++ b/cpu/o3/fetch_impl.hh @@ -138,6 +138,8 @@ DefaultFetch::DefaultFetch(Params *params) // Create space to store a cache line. cacheData[tid] = new uint8_t[cacheBlkSize]; + cacheDataPC[tid] = 0; + cacheDataValid[tid] = false; stalls[tid].decode = 0; stalls[tid].rename = 0; @@ -334,6 +336,7 @@ DefaultFetch::processCacheCompletion(MemReqPtr &req) // Wake up the CPU (if it went to sleep and was waiting on this completion // event). cpu->wakeCPU(); + cacheDataValid[tid] = true; DPRINTF(Activity, "[tid:%u] Activating fetch due to cache completion\n", tid); @@ -466,7 +469,7 @@ DefaultFetch::fetchCacheLine(Addr fetch_PC, Fault &ret_fault, unsigned tid unsigned flags = 0; #endif // FULL_SYSTEM - if (interruptPending && flags == 0 || switchedOut) { + if (interruptPending && flags == 0) { // Hold off fetch from getting new instructions while an interrupt // is pending. return false; @@ -475,6 +478,11 @@ DefaultFetch::fetchCacheLine(Addr fetch_PC, Fault &ret_fault, unsigned tid // Align the fetch PC so it's at the start of a cache block. fetch_PC = icacheBlockAlignPC(fetch_PC); + // If we've already got the block, no need to try to fetch it again. + if (cacheDataValid[tid] && fetch_PC == cacheDataPC[tid]) { + return true; + } + // Setup the memReq to do a read of the first instruction's address. // Set the appropriate read size and flags as well. memReq[tid] = new MemReq(); @@ -525,6 +533,9 @@ DefaultFetch::fetchCacheLine(Addr fetch_PC, Fault &ret_fault, unsigned tid MemAccessResult result = icacheInterface->access(memReq[tid]); + cacheDataPC[tid] = fetch_PC; + cacheDataValid[tid] = false; + fetchedCacheLines++; // If the cache missed, then schedule an event to wake @@ -1002,8 +1013,8 @@ DefaultFetch::fetch(bool &status_change) fetch_PC = next_PC; if (instruction->isQuiesce()) { - warn("%lli: Quiesce instruction encountered, halting fetch!", - curTick); +// warn("%lli: Quiesce instruction encountered, halting fetch!", +// curTick); fetchStatus[tid] = QuiescePending; ++numInst; status_change = true; @@ -1067,7 +1078,7 @@ DefaultFetch::fetch(bool &status_change) fetchStatus[tid] = TrapPending; status_change = true; - warn("%lli fault (%d) detected @ PC %08p", curTick, fault, PC[tid]); +// warn("%lli fault (%d) detected @ PC %08p", curTick, fault, PC[tid]); #else // !FULL_SYSTEM fatal("fault (%d) detected @ PC %08p", fault, PC[tid]); #endif // FULL_SYSTEM diff --git a/cpu/o3/iew.hh b/cpu/o3/iew.hh index eda6a6bc0..d21c573fe 100644 --- a/cpu/o3/iew.hh +++ b/cpu/o3/iew.hh @@ -224,6 +224,47 @@ class DefaultIEW /** Returns if the LSQ has any stores to writeback. */ bool hasStoresToWB() { return ldstQueue.hasStoresToWB(); } + void incrWb(InstSeqNum &sn) + { + if (++wbOutstanding == wbMax) + ableToIssue = false; + DPRINTF(IEW, "wbOutstanding: %i\n", wbOutstanding); + assert(wbOutstanding <= wbMax); +#ifdef DEBUG + wbList.insert(sn); +#endif + } + + void decrWb(InstSeqNum &sn) + { + if (wbOutstanding-- == wbMax) + ableToIssue = true; + DPRINTF(IEW, "wbOutstanding: %i\n", wbOutstanding); + assert(wbOutstanding >= 0); +#ifdef DEBUG + assert(wbList.find(sn) != wbList.end()); + wbList.erase(sn); +#endif + } + +#ifdef DEBUG + std::set wbList; + + void dumpWb() + { + std::set::iterator wb_it = wbList.begin(); + while (wb_it != wbList.end()) { + cprintf("[sn:%lli]\n", + (*wb_it)); + wb_it++; + } + } +#endif + + bool canIssue() { return ableToIssue; } + + bool ableToIssue; + private: /** Sends commit proper information for a squash due to a branch * mispredict. @@ -281,6 +322,9 @@ class DefaultIEW /** Processes inputs and changes state accordingly. */ void checkSignalsAndUpdate(unsigned tid); + /** Removes instructions from rename from a thread's instruction list. */ + void emptyRenameInsts(unsigned tid); + /** Sorts instructions coming from rename into lists separated by thread. */ void sortInsts(); @@ -401,20 +445,12 @@ class DefaultIEW */ unsigned issueToExecuteDelay; - /** Width of issue's read path, in instructions. The read path is both - * the skid buffer and the rename instruction queue. - * Note to self: is this really different than issueWidth? - */ - unsigned issueReadWidth; + /** Width of dispatch, in instructions. */ + unsigned dispatchWidth; /** Width of issue, in instructions. */ unsigned issueWidth; - /** Width of execute, in instructions. Might make more sense to break - * down into FP vs int. - */ - unsigned executeWidth; - /** Index into queue of instructions being written back. */ unsigned wbNumInst; @@ -425,6 +461,17 @@ class DefaultIEW */ unsigned wbCycle; + /** Number of instructions in flight that will writeback. */ + int wbOutstanding; + + /** Writeback width. */ + unsigned wbWidth; + + /** Writeback width * writeback depth, where writeback depth is + * the number of cycles of writing back instructions that can be + * buffered. */ + unsigned wbMax; + /** Number of active threads. */ unsigned numThreads; @@ -459,14 +506,6 @@ class DefaultIEW Stats::Scalar<> iewIQFullEvents; /** Stat for number of times the LSQ becomes full. */ Stats::Scalar<> iewLSQFullEvents; - /** Stat for total number of executed instructions. */ - Stats::Scalar<> iewExecutedInsts; - /** Stat for total number of executed load instructions. */ - Stats::Vector<> iewExecLoadInsts; - /** Stat for total number of executed store instructions. */ -// Stats::Scalar<> iewExecStoreInsts; - /** Stat for total number of squashed instructions skipped at execute. */ - Stats::Scalar<> iewExecSquashedInsts; /** Stat for total number of memory ordering violation events. */ Stats::Scalar<> memOrderViolationEvents; /** Stat for total number of incorrect predicted taken branches. */ @@ -476,28 +515,27 @@ class DefaultIEW /** Stat for total number of mispredicted branches detected at execute. */ Stats::Formula branchMispredicts; + /** Stat for total number of executed instructions. */ + Stats::Scalar<> iewExecutedInsts; + /** Stat for total number of executed load instructions. */ + Stats::Vector<> iewExecLoadInsts; + /** Stat for total number of executed store instructions. */ +// Stats::Scalar<> iewExecStoreInsts; + /** Stat for total number of squashed instructions skipped at execute. */ + Stats::Scalar<> iewExecSquashedInsts; /** Number of executed software prefetches. */ - Stats::Vector<> exeSwp; + Stats::Vector<> iewExecutedSwp; /** Number of executed nops. */ - Stats::Vector<> exeNop; + Stats::Vector<> iewExecutedNop; /** Number of executed meomory references. */ - Stats::Vector<> exeRefs; + Stats::Vector<> iewExecutedRefs; /** Number of executed branches. */ - Stats::Vector<> exeBranches; - -// Stats::Vector<> issued_ops; -/* - Stats::Vector<> stat_fu_busy; - Stats::Vector2d<> stat_fuBusy; - Stats::Vector<> dist_unissued; - Stats::Vector2d<> stat_issued_inst_type; -*/ - /** Number of instructions issued per cycle. */ - Stats::Formula issueRate; + Stats::Vector<> iewExecutedBranches; /** Number of executed store instructions. */ Stats::Formula iewExecStoreInsts; -// Stats::Formula issue_op_rate; -// Stats::Formula fu_busy_rate; + /** Number of instructions executed per cycle. */ + Stats::Formula iewExecRate; + /** Number of instructions sent to commit. */ Stats::Vector<> iewInstsToCommit; /** Number of instructions that writeback. */ @@ -510,7 +548,6 @@ class DefaultIEW * to resource contention. */ Stats::Vector<> wbPenalized; - /** Number of instructions per cycle written back. */ Stats::Formula wbRate; /** Average number of woken instructions per writeback. */ diff --git a/cpu/o3/iew_impl.hh b/cpu/o3/iew_impl.hh index 3ed20cb75..102be4f8d 100644 --- a/cpu/o3/iew_impl.hh +++ b/cpu/o3/iew_impl.hh @@ -56,9 +56,11 @@ DefaultIEW::LdWritebackEvent::process() //iewStage->ldstQueue.removeMSHR(inst->threadNumber,inst->seqNum); if (iewStage->isSwitchedOut()) { + iewStage->decrWb(inst->seqNum); inst = NULL; return; } else if (inst->isSquashed()) { + iewStage->decrWb(inst->seqNum); iewStage->wakeCPU(); inst = NULL; return; @@ -93,16 +95,17 @@ DefaultIEW::LdWritebackEvent::description() template DefaultIEW::DefaultIEW(Params *params) : // @todo: Make this into a parameter. - issueToExecQueue(5, 5), + issueToExecQueue(params->backComSize, params->forwardComSize), instQueue(params), ldstQueue(params), fuPool(params->fuPool), commitToIEWDelay(params->commitToIEWDelay), renameToIEWDelay(params->renameToIEWDelay), issueToExecuteDelay(params->issueToExecuteDelay), - issueReadWidth(params->issueWidth), + dispatchWidth(params->dispatchWidth), issueWidth(params->issueWidth), - executeWidth(params->executeWidth), + wbOutstanding(0), + wbWidth(params->wbWidth), numThreads(params->numberOfThreads), switchedOut(false) { @@ -125,8 +128,12 @@ DefaultIEW::DefaultIEW(Params *params) fetchRedirect[i] = false; } + wbMax = wbWidth * params->wbDepth; + updateLSQNextCycle = false; + ableToIssue = true; + skidBufferMax = (3 * (renameToIEWDelay * params->renameWidth)) + issueWidth; } @@ -144,6 +151,7 @@ DefaultIEW::regStats() using namespace Stats; instQueue.regStats(); + ldstQueue.regStats(); iewIdleCycles .name(name() + ".iewIdleCycles") @@ -189,20 +197,6 @@ DefaultIEW::regStats() .name(name() + ".iewLSQFullEvents") .desc("Number of times the LSQ has become full, causing a stall"); - iewExecutedInsts - .name(name() + ".iewExecutedInsts") - .desc("Number of executed instructions"); - - iewExecLoadInsts - .init(cpu->number_of_threads) - .name(name() + ".iewExecLoadInsts") - .desc("Number of load instructions executed") - .flags(total); - - iewExecSquashedInsts - .name(name() + ".iewExecSquashedInsts") - .desc("Number of squashed instructions skipped in execute"); - memOrderViolationEvents .name(name() + ".memOrderViolationEvents") .desc("Number of memory order violations"); @@ -221,47 +215,49 @@ DefaultIEW::regStats() branchMispredicts = predictedTakenIncorrect + predictedNotTakenIncorrect; - exeSwp + iewExecutedInsts + .name(name() + ".iewExecutedInsts") + .desc("Number of executed instructions"); + + iewExecLoadInsts + .init(cpu->number_of_threads) + .name(name() + ".iewExecLoadInsts") + .desc("Number of load instructions executed") + .flags(total); + + iewExecSquashedInsts + .name(name() + ".iewExecSquashedInsts") + .desc("Number of squashed instructions skipped in execute"); + + iewExecutedSwp .init(cpu->number_of_threads) .name(name() + ".EXEC:swp") .desc("number of swp insts executed") - .flags(total) - ; + .flags(total); - exeNop + iewExecutedNop .init(cpu->number_of_threads) .name(name() + ".EXEC:nop") .desc("number of nop insts executed") - .flags(total) - ; + .flags(total); - exeRefs + iewExecutedRefs .init(cpu->number_of_threads) .name(name() + ".EXEC:refs") .desc("number of memory reference insts executed") - .flags(total) - ; + .flags(total); - exeBranches + iewExecutedBranches .init(cpu->number_of_threads) .name(name() + ".EXEC:branches") .desc("Number of branches executed") - .flags(total) - ; - - issueRate - .name(name() + ".EXEC:rate") - .desc("Inst execution rate") - .flags(total) - ; - issueRate = iewExecutedInsts / cpu->numCycles; + .flags(total); iewExecStoreInsts .name(name() + ".EXEC:stores") .desc("Number of stores executed") - .flags(total) - ; - iewExecStoreInsts = exeRefs - iewExecLoadInsts; + .flags(total); + iewExecStoreInsts = iewExecutedRefs - iewExecLoadInsts; /* for (int i=0; i::regStats() .init(cpu->number_of_threads) .name(name() + ".WB:sent") .desc("cumulative count of insts sent to commit") - .flags(total) - ; + .flags(total); writebackCount .init(cpu->number_of_threads) .name(name() + ".WB:count") .desc("cumulative count of insts written-back") - .flags(total) - ; + .flags(total); producerInst .init(cpu->number_of_threads) .name(name() + ".WB:producers") .desc("num instructions producing a value") - .flags(total) - ; + .flags(total); consumerInst .init(cpu->number_of_threads) .name(name() + ".WB:consumers") .desc("num instructions consuming a value") - .flags(total) - ; + .flags(total); wbPenalized .init(cpu->number_of_threads) .name(name() + ".WB:penalized") .desc("number of instrctions required to write to 'other' IQ") - .flags(total) - ; + .flags(total); wbPenalizedRate .name(name() + ".WB:penalized_rate") .desc ("fraction of instructions written-back that wrote to 'other' IQ") - .flags(total) - ; + .flags(total); wbPenalizedRate = wbPenalized / writebackCount; wbFanout .name(name() + ".WB:fanout") .desc("average fanout of values written-back") - .flags(total) - ; + .flags(total); wbFanout = producerInst / consumerInst; wbRate .name(name() + ".WB:rate") .desc("insts written-back per cycle") - .flags(total) - ; + .flags(total); wbRate = writebackCount / cpu->numCycles; } @@ -481,8 +469,7 @@ DefaultIEW::takeOverFrom() updateLSQNextCycle = false; - // @todo: Fix hardcoded number - for (int i = 0; i < 6; ++i) { + for (int i = 0; i < issueToExecQueue.getSize(); ++i) { issueToExecQueue.advance(); } } @@ -515,16 +502,7 @@ DefaultIEW::squash(unsigned tid) skidBuffer[tid].pop(); } - while (!insts[tid].empty()) { - if (insts[tid].front()->isLoad() || - insts[tid].front()->isStore() ) { - toRename->iewInfo[tid].dispatchedToLSQ++; - } - - toRename->iewInfo[tid].dispatched++; - - insts[tid].pop(); - } + emptyRenameInsts(tid); } template @@ -650,14 +628,16 @@ DefaultIEW::instToCommit(DynInstPtr &inst) // free slot. while ((*iewQueue)[wbCycle].insts[wbNumInst]) { ++wbNumInst; - if (wbNumInst == issueWidth) { + if (wbNumInst == wbWidth) { ++wbCycle; wbNumInst = 0; } - assert(wbCycle < 5); + assert((wbCycle * wbWidth + wbNumInst) <= wbMax); } + DPRINTF(IEW, "Current wb cycle: %i, width: %i, numInst: %i\nwbActual:%i\n", + wbCycle, wbWidth, wbNumInst, wbCycle * wbWidth + wbNumInst); // Add finished instruction to queue to commit. (*iewQueue)[wbCycle].insts[wbNumInst] = inst; (*iewQueue)[wbCycle].size++; @@ -670,7 +650,7 @@ DefaultIEW::validInstsFromRename() unsigned inst_count = 0; for (int i=0; isize; i++) { - if (!fromRename->insts[i]->squashed) + if (!fromRename->insts[i]->isSquashed()) inst_count++; } @@ -858,10 +838,12 @@ DefaultIEW::checkSignalsAndUpdate(unsigned tid) } if (fromCommit->commitInfo[tid].robSquashing) { - DPRINTF(IEW, "[tid:%i]: ROB is still squashing.\n"); + DPRINTF(IEW, "[tid:%i]: ROB is still squashing.\n", tid); dispatchStatus[tid] = Squashing; + emptyRenameInsts(tid); + wroteToTimeBuffer = true; return; } @@ -910,6 +892,22 @@ DefaultIEW::sortInsts() } } +template +void +DefaultIEW::emptyRenameInsts(unsigned tid) +{ + while (!insts[tid].empty()) { + if (insts[tid].front()->isLoad() || + insts[tid].front()->isStore() ) { + toRename->iewInfo[tid].dispatchedToLSQ++; + } + + toRename->iewInfo[tid].dispatched++; + + insts[tid].pop(); + } +} + template void DefaultIEW::wakeCPU() @@ -1010,7 +1008,7 @@ DefaultIEW::dispatchInsts(unsigned tid) // Loop through the instructions, putting them in the instruction // queue. for ( ; dis_num_inst < insts_to_add && - dis_num_inst < issueReadWidth; + dis_num_inst < dispatchWidth; ++dis_num_inst) { inst = insts_to_dispatch.front(); @@ -1149,7 +1147,7 @@ DefaultIEW::dispatchInsts(unsigned tid) instQueue.recordProducer(inst); - exeNop[tid]++; + iewExecutedNop[tid]++; add_to_iq = false; } else if (inst->isExecuted()) { @@ -1263,6 +1261,7 @@ DefaultIEW::executeInsts() ++iewExecSquashedInsts; + decrWb(inst->seqNum); continue; } @@ -1399,8 +1398,8 @@ DefaultIEW::writebackInsts() DynInstPtr inst = toCommit->insts[inst_num]; int tid = inst->threadNumber; - DPRINTF(IEW, "Sending instructions to commit, PC %#x.\n", - inst->readPC()); + DPRINTF(IEW, "Sending instructions to commit, [sn:%lli] PC %#x.\n", + inst->seqNum, inst->readPC()); iewInstsToCommit[tid]++; @@ -1425,6 +1424,8 @@ DefaultIEW::writebackInsts() } writebackCount[tid]++; } + + decrWb(inst->seqNum); } } @@ -1561,7 +1562,7 @@ DefaultIEW::updateExeInstStats(DynInstPtr &inst) // #ifdef TARGET_ALPHA if (inst->isDataPrefetch()) - exeSwp[thread_number]++; + iewExecutedSwp[thread_number]++; else iewExecutedInsts++; #else @@ -1572,13 +1573,13 @@ DefaultIEW::updateExeInstStats(DynInstPtr &inst) // Control operations // if (inst->isControl()) - exeBranches[thread_number]++; + iewExecutedBranches[thread_number]++; // // Memory operations // if (inst->isMemRef()) { - exeRefs[thread_number]++; + iewExecutedRefs[thread_number]++; if (inst->isLoad()) { iewExecLoadInsts[thread_number]++; diff --git a/cpu/o3/inst_queue.hh b/cpu/o3/inst_queue.hh index 4802cbaf4..80cd71f0d 100644 --- a/cpu/o3/inst_queue.hh +++ b/cpu/o3/inst_queue.hh @@ -490,8 +490,6 @@ class InstructionQueue /** Number of instructions issued per cycle. */ Stats::Formula issueRate; -// Stats::Formula issue_stores; -// Stats::Formula issue_op_rate; /** Number of times the FU was busy. */ Stats::Vector<> fuBusy; /** Number of times the FU was busy per instruction issued. */ diff --git a/cpu/o3/inst_queue_impl.hh b/cpu/o3/inst_queue_impl.hh index d677a259c..72cb0d708 100644 --- a/cpu/o3/inst_queue_impl.hh +++ b/cpu/o3/inst_queue_impl.hh @@ -288,22 +288,7 @@ InstructionQueue::regStats() .flags(total) ; issueRate = iqInstsIssued / cpu->numCycles; -/* - issue_stores - .name(name() + ".ISSUE:stores") - .desc("Number of stores issued") - .flags(total) - ; - issue_stores = exe_refs - exe_loads; -*/ -/* - issue_op_rate - .name(name() + ".ISSUE:op_rate") - .desc("Operation issue rate") - .flags(total) - ; - issue_op_rate = issued_ops / numCycles; -*/ + statFuBusy .init(Num_OpClasses) .name(name() + ".ISSUE:fu_full") @@ -700,6 +685,7 @@ InstructionQueue::scheduleReadyInsts() int total_issued = 0; while (total_issued < totalWidth && + iewStage->canIssue() && order_it != order_end_it) { OpClass op_class = (*order_it).queueType; @@ -790,13 +776,14 @@ InstructionQueue::scheduleReadyInsts() // complete. ++freeEntries; count[tid]--; - issuing_inst->removeInIQ(); + issuing_inst->clearInIQ(); } else { memDepUnit[tid].issue(issuing_inst); } listOrder.erase(order_it++); statIssuedInstType[tid][op_class]++; + iewStage->incrWb(issuing_inst->seqNum); } else { statFuBusy[op_class]++; fuBusy[tid]++; @@ -1096,7 +1083,7 @@ InstructionQueue::doSquash(unsigned tid) // inst will flow through the rest of the pipeline. squashed_inst->setIssued(); squashed_inst->setCanCommit(); - squashed_inst->removeInIQ(); + squashed_inst->clearInIQ(); //Update Thread IQ Count count[squashed_inst->threadNumber]--; diff --git a/cpu/o3/lsq.hh b/cpu/o3/lsq.hh index b321d4590..c67225bc0 100644 --- a/cpu/o3/lsq.hh +++ b/cpu/o3/lsq.hh @@ -62,6 +62,9 @@ class LSQ { /** Returns the name of the LSQ. */ std::string name() const; + /** Registers the statistics for each LSQ Unit. */ + void regStats(); + /** Sets the pointer to the list of active threads. */ void setActiveThreads(std::list *at_ptr); /** Sets the CPU pointer. */ diff --git a/cpu/o3/lsq_impl.hh b/cpu/o3/lsq_impl.hh index a6ad27522..a8a55af1a 100644 --- a/cpu/o3/lsq_impl.hh +++ b/cpu/o3/lsq_impl.hh @@ -104,6 +104,16 @@ LSQ::name() const return iewStage->name() + ".lsq"; } +template +void +LSQ::regStats() +{ + //Initialize LSQs + for (int tid=0; tid < numThreads; tid++) { + thread[tid].regStats(); + } +} + template void LSQ::setActiveThreads(list *at_ptr) diff --git a/cpu/o3/lsq_unit.hh b/cpu/o3/lsq_unit.hh index a6afff743..fe174a97d 100644 --- a/cpu/o3/lsq_unit.hh +++ b/cpu/o3/lsq_unit.hh @@ -101,6 +101,9 @@ class LSQUnit { /** Returns the name of the LSQ unit. */ std::string name() const; + /** Registers statistics. */ + void regStats(); + /** Sets the CPU pointer. */ void setCPU(FullCPU *cpu_ptr) { cpu = cpu_ptr; } @@ -153,9 +156,6 @@ class LSQUnit { /** Writes back stores. */ void writebackStores(); - // @todo: Include stats in the LSQ unit. - //void regStats(); - /** Clears all the entries in the LQ. */ void clearLQ(); @@ -369,25 +369,34 @@ class LSQUnit { // Will also need how many read/write ports the Dcache has. Or keep track // of that in stage that is one level up, and only call executeLoad/Store // the appropriate number of times. -/* - // total number of loads forwaded from LSQ stores - Stats::Vector<> lsq_forw_loads; + /** Total number of loads forwaded from LSQ stores. */ + Stats::Scalar<> lsqForwLoads; - // total number of loads ignored due to invalid addresses - Stats::Vector<> inv_addr_loads; + /** Total number of loads ignored due to invalid addresses. */ + Stats::Scalar<> invAddrLoads; - // total number of software prefetches ignored due to invalid addresses - Stats::Vector<> inv_addr_swpfs; + /** Total number of squashed loads. */ + Stats::Scalar<> lsqSquashedLoads; - // total non-speculative bogus addresses seen (debug var) - Counter sim_invalid_addrs; - Stats::Vector<> fu_busy; //cumulative fu busy + /** Total number of responses from the memory system that are + * ignored due to the instruction already being squashed. */ + Stats::Scalar<> lsqIgnoredResponses; - // ready loads blocked due to memory disambiguation - Stats::Vector<> lsq_blocked_loads; + /** Total number of squashed stores. */ + Stats::Scalar<> lsqSquashedStores; + + /** Total number of software prefetches ignored due to invalid addresses. */ + Stats::Scalar<> invAddrSwpfs; + + /** Ready loads blocked due to partial store-forwarding. */ + Stats::Scalar<> lsqBlockedLoads; + + /** Number of loads that were rescheduled. */ + Stats::Scalar<> lsqRescheduledLoads; + + /** Number of times the LSQ is blocked due to the cache. */ + Stats::Scalar<> lsqCacheBlocked; - Stats::Scalar<> lsqInversion; -*/ public: /** Executes the load at the given index. */ template @@ -441,8 +450,9 @@ LSQUnit::read(MemReqPtr &req, T &data, int load_idx) // at the head of the LSQ and are ready to commit (at the head of the ROB // too). if (req->flags & UNCACHEABLE && - (load_idx != loadHead || !loadQueue[load_idx]->reachedCommit)) { + (load_idx != loadHead || !loadQueue[load_idx]->isAtCommit())) { iewStage->rescheduleMemInst(loadQueue[load_idx]); + ++lsqRescheduledLoads; return TheISA::genMachineCheckFault(); } @@ -552,6 +562,8 @@ LSQUnit::read(MemReqPtr &req, T &data, int load_idx) // Tell IQ/mem dep unit that this instruction will need to be // rescheduled eventually iewStage->rescheduleMemInst(loadQueue[load_idx]); + iewStage->decrWb(loadQueue[load_idx]->seqNum); + ++lsqRescheduledLoads; // Do not generate a writeback event as this instruction is not // complete. @@ -559,6 +571,7 @@ LSQUnit::read(MemReqPtr &req, T &data, int load_idx) "Store idx %i to load addr %#x\n", store_idx, req->vaddr); + ++lsqBlockedLoads; return NoFault; } } @@ -579,6 +592,10 @@ LSQUnit::read(MemReqPtr &req, T &data, int load_idx) // if we have a cache, do cache access too if (fault == NoFault && dcacheInterface) { if (dcacheInterface->isBlocked()) { + ++lsqCacheBlocked; + + iewStage->decrWb(inst->seqNum); + // There's an older load that's already going to squash. if (isLoadBlocked && blockedLoadSeqNum < inst->seqNum) return NoFault; diff --git a/cpu/o3/lsq_unit_impl.hh b/cpu/o3/lsq_unit_impl.hh index 4ee8bb234..5cc3078f8 100644 --- a/cpu/o3/lsq_unit_impl.hh +++ b/cpu/o3/lsq_unit_impl.hh @@ -124,6 +124,47 @@ LSQUnit::name() const } } +template +void +LSQUnit::regStats() +{ + lsqForwLoads + .name(name() + ".forwLoads") + .desc("Number of loads that had data forwarded from stores"); + + invAddrLoads + .name(name() + ".invAddrLoads") + .desc("Number of loads ignored due to an invalid address"); + + lsqSquashedLoads + .name(name() + ".squashedLoads") + .desc("Number of loads squashed"); + + lsqIgnoredResponses + .name(name() + ".ignoredResponses") + .desc("Number of memory responses ignored because the instruction is squashed"); + + lsqSquashedStores + .name(name() + ".squashedStores") + .desc("Number of stores squashed"); + + invAddrSwpfs + .name(name() + ".invAddrSwpfs") + .desc("Number of software prefetches ignored due to an invalid address"); + + lsqBlockedLoads + .name(name() + ".blockedLoads") + .desc("Number of blocked loads due to partial load-store forwarding"); + + lsqRescheduledLoads + .name(name() + ".rescheduledLoads") + .desc("Number of loads that were rescheduled"); + + lsqCacheBlocked + .name(name() + ".cacheBlocked") + .desc("Number of times an access to memory failed due to the cache being blocked"); +} + template void LSQUnit::clearLQ() @@ -548,6 +589,7 @@ LSQUnit::writebackStores() if (dcacheInterface && dcacheInterface->isBlocked()) { DPRINTF(LSQUnit, "Unable to write back any more stores, cache" " is blocked!\n"); + ++lsqCacheBlocked; break; } @@ -705,7 +747,7 @@ LSQUnit::squash(const InstSeqNum &squashed_num) } // Clear the smart pointer to make sure it is decremented. - loadQueue[load_idx]->squashed = true; + loadQueue[load_idx]->setSquashed(); loadQueue[load_idx] = NULL; --loads; @@ -748,7 +790,7 @@ LSQUnit::squash(const InstSeqNum &squashed_num) } // Clear the smart pointer to make sure it is decremented. - storeQueue[store_idx].inst->squashed = true; + storeQueue[store_idx].inst->setSquashed(); storeQueue[store_idx].inst = NULL; storeQueue[store_idx].canWB = 0; @@ -765,6 +807,7 @@ LSQUnit::squash(const InstSeqNum &squashed_num) storeTail = store_idx; decrStIdx(store_idx); + ++lsqSquashedStores; } } diff --git a/cpu/o3/mem_dep_unit.cc b/cpu/o3/mem_dep_unit.cc index ccdd1a515..b0f91d44f 100644 --- a/cpu/o3/mem_dep_unit.cc +++ b/cpu/o3/mem_dep_unit.cc @@ -35,6 +35,7 @@ // AlphaSimpleImpl. template class MemDepUnit; +#ifdef DEBUG template <> int MemDepUnit::MemDepEntry::memdep_count = 0; @@ -44,3 +45,4 @@ MemDepUnit::MemDepEntry::memdep_insert = 0; template <> int MemDepUnit::MemDepEntry::memdep_erase = 0; +#endif diff --git a/cpu/o3/mem_dep_unit_impl.hh b/cpu/o3/mem_dep_unit_impl.hh index 595e9293f..bfe694bd8 100644 --- a/cpu/o3/mem_dep_unit_impl.hh +++ b/cpu/o3/mem_dep_unit_impl.hh @@ -59,7 +59,9 @@ MemDepUnit::~MemDepUnit() } } +#ifdef DEBUG assert(MemDepEntry::memdep_count == 0); +#endif } template @@ -141,7 +143,9 @@ MemDepUnit::insert(DynInstPtr &inst) // Add the MemDepEntry to the hash. memDepHash.insert( std::pair(inst->seqNum, inst_entry)); +#ifdef DEBUG MemDepEntry::memdep_insert++; +#endif instList[tid].push_back(inst); @@ -227,7 +231,9 @@ MemDepUnit::insertNonSpec(DynInstPtr &inst) // Insert the MemDepEntry into the hash. memDepHash.insert( std::pair(inst->seqNum, inst_entry)); +#ifdef DEBUG MemDepEntry::memdep_insert++; +#endif // Add the instruction to the list. instList[tid].push_back(inst); @@ -275,7 +281,9 @@ MemDepUnit::insertBarrier(DynInstPtr &barr_inst) // Add the MemDepEntry to the hash. memDepHash.insert( std::pair(barr_sn, inst_entry)); +#ifdef DEBUG MemDepEntry::memdep_insert++; +#endif // Add the instruction to the instruction list. instList[tid].push_back(barr_inst); @@ -375,7 +383,9 @@ MemDepUnit::completed(DynInstPtr &inst) (*hash_it).second = NULL; memDepHash.erase(hash_it); +#ifdef DEBUG MemDepEntry::memdep_erase++; +#endif } template @@ -470,7 +480,9 @@ MemDepUnit::squash(const InstSeqNum &squashed_num, (*hash_it).second = NULL; memDepHash.erase(hash_it); +#ifdef DEBUG MemDepEntry::memdep_erase++; +#endif instList[tid].erase(squash_it--); } @@ -551,5 +563,7 @@ MemDepUnit::dumpLists() cprintf("Memory dependence hash size: %i\n", memDepHash.size()); +#ifdef DEBUG cprintf("Memory dependence entries: %i\n", MemDepEntry::memdep_count); +#endif } diff --git a/cpu/o3/regfile.hh b/cpu/o3/regfile.hh index ed1238d36..76c43d3a1 100644 --- a/cpu/o3/regfile.hh +++ b/cpu/o3/regfile.hh @@ -223,10 +223,10 @@ class PhysRegFile public: /** (signed) integer register file. */ - std::vector intRegFile; + IntReg *intRegFile; /** Floating point register file. */ - std::vector floatRegFile; + FloatReg *floatRegFile; /** Miscellaneous register file. */ MiscRegFile miscRegs[Impl::MaxThreads]; @@ -256,11 +256,15 @@ PhysRegFile::PhysRegFile(unsigned _numPhysicalIntRegs, : numPhysicalIntRegs(_numPhysicalIntRegs), numPhysicalFloatRegs(_numPhysicalFloatRegs) { - intRegFile.resize(numPhysicalIntRegs); - floatRegFile.resize(numPhysicalFloatRegs); + intRegFile = new IntReg[numPhysicalIntRegs]; + floatRegFile = new FloatReg[numPhysicalFloatRegs]; - //memset(intRegFile, 0, sizeof(*intRegFile)); - //memset(floatRegFile, 0, sizeof(*floatRegFile)); + for (int i = 0; i < Impl::MaxThreads; ++i) { + miscRegs[i].clear(); + } + + memset(intRegFile, 0, sizeof(*intRegFile)); + memset(floatRegFile, 0, sizeof(*floatRegFile)); } #endif diff --git a/cpu/o3/rename_impl.hh b/cpu/o3/rename_impl.hh index 829c99584..93f5b3504 100644 --- a/cpu/o3/rename_impl.hh +++ b/cpu/o3/rename_impl.hh @@ -348,7 +348,7 @@ DefaultRename::squash(unsigned tid) for (int i=0; isize; i++) { if (fromDecode->insts[i]->threadNumber == tid) { - fromDecode->insts[i]->squashed = true; + fromDecode->insts[i]->setSquashed(); wroteToTimeBuffer = true; squashCount++; } @@ -1029,7 +1029,7 @@ DefaultRename::validInsts() unsigned inst_count = 0; for (int i=0; isize; i++) { - if (!fromDecode->insts[i]->squashed) + if (!fromDecode->insts[i]->isSquashed()) inst_count++; } diff --git a/cpu/o3/rob.hh b/cpu/o3/rob.hh index bdbdde32f..2043e0b34 100644 --- a/cpu/o3/rob.hh +++ b/cpu/o3/rob.hh @@ -305,7 +305,7 @@ class ROB private: /** The sequence number of the squashed instruction. */ - InstSeqNum squashedSeqNum; + InstSeqNum squashedSeqNum[Impl::MaxThreads]; /** Is the ROB done squashing. */ bool doneSquashing[Impl::MaxThreads]; diff --git a/cpu/o3/rob_impl.hh b/cpu/o3/rob_impl.hh index 25e0c80fd..62c4d9cf7 100644 --- a/cpu/o3/rob_impl.hh +++ b/cpu/o3/rob_impl.hh @@ -38,10 +38,10 @@ ROB::ROB(unsigned _numEntries, unsigned _squashWidth, : numEntries(_numEntries), squashWidth(_squashWidth), numInstsInROB(0), - squashedSeqNum(0), numThreads(_numThreads) { for (int tid=0; tid < numThreads; tid++) { + squashedSeqNum[tid] = 0; doneSquashing[tid] = true; threadEntries[tid] = 0; } @@ -274,7 +274,7 @@ ROB::retireHead(unsigned tid) --numInstsInROB; --threadEntries[tid]; - head_inst->removeInROB(); + head_inst->clearInROB(); head_inst->setCommitted(); instList[tid].erase(head_it); @@ -349,11 +349,11 @@ void ROB::doSquash(unsigned tid) { DPRINTF(ROB, "[tid:%u]: Squashing instructions until [sn:%i].\n", - tid, squashedSeqNum); + tid, squashedSeqNum[tid]); assert(squashIt[tid] != instList[tid].end()); - if ((*squashIt[tid])->seqNum < squashedSeqNum) { + if ((*squashIt[tid])->seqNum < squashedSeqNum[tid]) { DPRINTF(ROB, "[tid:%u]: Done squashing instructions.\n", tid); @@ -368,7 +368,7 @@ ROB::doSquash(unsigned tid) for (int numSquashed = 0; numSquashed < squashWidth && squashIt[tid] != instList[tid].end() && - (*squashIt[tid])->seqNum > squashedSeqNum; + (*squashIt[tid])->seqNum > squashedSeqNum[tid]; ++numSquashed) { DPRINTF(ROB, "[tid:%u]: Squashing instruction PC %#x, seq num %i.\n", @@ -405,7 +405,7 @@ ROB::doSquash(unsigned tid) // Check if ROB is done squashing. - if ((*squashIt[tid])->seqNum <= squashedSeqNum) { + if ((*squashIt[tid])->seqNum <= squashedSeqNum[tid]) { DPRINTF(ROB, "[tid:%u]: Done squashing instructions.\n", tid); @@ -517,7 +517,7 @@ ROB::squash(InstSeqNum squash_num,unsigned tid) doneSquashing[tid] = false; - squashedSeqNum = squash_num; + squashedSeqNum[tid] = squash_num; if (!instList[tid].empty()) { InstIt tail_thread = instList[tid].end(); diff --git a/cpu/ozone/cpu.hh b/cpu/ozone/cpu.hh index 5af2b02b2..c272528b1 100644 --- a/cpu/ozone/cpu.hh +++ b/cpu/ozone/cpu.hh @@ -1,5 +1,5 @@ /* - * Copyright (c) 2005 The Regents of The University of Michigan + * Copyright (c) 2006 The Regents of The University of Michigan * All rights reserved. * * Redistribution and use in source and binary forms, with or without @@ -79,13 +79,13 @@ template class Checker; /** - * Declaration of Out-of-Order CPU class. Basically it is a SimpleCPU with - * simple out-of-order capabilities added to it. It is still a 1 CPI machine - * (?), but is capable of handling cache misses. Basically it models having - * a ROB/IQ by only allowing a certain amount of instructions to execute while - * the cache miss is outstanding. + * Light weight out of order CPU model that approximates an out of + * order CPU. It is separated into a front end and a back end, with + * the template parameter Impl describing the classes used for each. + * The goal is to be able to specify through the Impl the class to use + * for the front end and back end, with different classes used to + * model different levels of detail. */ - template class OzoneCPU : public BaseCPU { @@ -98,6 +98,11 @@ class OzoneCPU : public BaseCPU typedef TheISA::MiscReg MiscReg; public: + /** + * The ExecContext for this CPU, which is used to provide the + * CPU's interface to any external objects. Internally most of + * the CPU state is stored within the OzoneThreadState class. + */ class OzoneXC : public ExecContext { public: OzoneCPU *cpu; @@ -235,14 +240,19 @@ class OzoneCPU : public BaseCPU #endif }; - // execution context proxy + // ExecContext for OzoneCPU OzoneXC ozoneXC; + + // ExecContext pointer that will be given to any external objects. ExecContext *xcProxy; + + // ExecContext pointer to the CheckerCPU's ExecContext. ExecContext *checkerXC; typedef OzoneThreadState ImplState; private: + // Committed thread state for the OzoneCPU. OzoneThreadState thread; public: @@ -280,12 +290,6 @@ class OzoneCPU : public BaseCPU tickEvent.squash(); } - private: - Trace::InstRecord *traceData; - - template - void trace_data(T data); - public: enum Status { Running, @@ -361,6 +365,7 @@ class OzoneCPU : public BaseCPU FrontEnd *frontEnd; BackEnd *backEnd; + private: Status status() const { return _status; } void setStatus(Status new_status) { _status = new_status; } @@ -392,12 +397,11 @@ class OzoneCPU : public BaseCPU // number of idle cycles Stats::Average<> notIdleFraction; Stats::Formula idleFraction; - public: + public: virtual void serialize(std::ostream &os); virtual void unserialize(Checkpoint *cp, const std::string §ion); - #if FULL_SYSTEM bool validInstAddr(Addr addr) { return true; } bool validDataAddr(Addr addr) { return true; } @@ -585,12 +589,9 @@ class OzoneCPU : public BaseCPU Fault copy(Addr dest); - InstSeqNum globalSeqNum; - public: void squashFromXC(); - // @todo: This can be a useful debug function. Implement it. void dumpInsts() { frontEnd->dumpInsts(); } #if FULL_SYSTEM @@ -608,7 +609,6 @@ class OzoneCPU : public BaseCPU ExecContext *xcBase() { return xcProxy; } - bool decoupledFrontEnd; struct CommStruct { InstSeqNum doneSeqNum; InstSeqNum nonSpecSeqNum; @@ -617,8 +617,13 @@ class OzoneCPU : public BaseCPU bool stall; }; + + InstSeqNum globalSeqNum; + TimeBuffer comm; + bool decoupledFrontEnd; + bool lockFlag; Stats::Scalar<> quiesceCycles; diff --git a/cpu/ozone/cpu_impl.hh b/cpu/ozone/cpu_impl.hh index 5675da3a8..4f41f220a 100644 --- a/cpu/ozone/cpu_impl.hh +++ b/cpu/ozone/cpu_impl.hh @@ -26,9 +26,6 @@ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ -//#include -//#include - #include "arch/isa_traits.hh" // For MachInst #include "base/trace.hh" #include "config/full_system.hh" @@ -39,7 +36,6 @@ #include "cpu/ozone/cpu.hh" #include "cpu/quiesce_event.hh" #include "cpu/static_inst.hh" -//#include "mem/base_mem.hh" #include "mem/mem_interface.hh" #include "sim/sim_object.hh" #include "sim/stats.hh" @@ -50,7 +46,6 @@ #include "arch/alpha/tlb.hh" #include "arch/vtophys.hh" #include "base/callback.hh" -//#include "base/remote_gdb.hh" #include "cpu/profile.hh" #include "kern/kernel_stats.hh" #include "mem/functional/memory_control.hh" @@ -66,15 +61,6 @@ using namespace TheISA; -template -template -void -OzoneCPU::trace_data(T data) { - if (traceData) { - traceData->setData(data); - } -} - template OzoneCPU::TickEvent::TickEvent(OzoneCPU *c, int w) : Event(&mainEventQueue, CPU_Tick_Pri), cpu(c), width(w) @@ -104,7 +90,7 @@ OzoneCPU::OzoneCPU(Params *p) : BaseCPU(p), thread(this, 0, p->workload[0], 0), tickEvent(this, p->width), mem(p->workload[0]->getMemory()), #endif - comm(5, 5) + comm(5, 5), decoupledFrontEnd(p->decoupledFrontEnd) { frontEnd = new FrontEnd(p); backEnd = new BackEnd(p); @@ -112,6 +98,9 @@ OzoneCPU::OzoneCPU(Params *p) _status = Idle; if (p->checker) { + // If checker is being used, get the checker from the params + // pointer, make the Checker's ExecContext, and setup the + // xcProxy to point to it. BaseCPU *temp_checker = p->checker; checker = dynamic_cast *>(temp_checker); checker->setMemory(mem); @@ -122,11 +111,17 @@ OzoneCPU::OzoneCPU(Params *p) thread.xcProxy = checkerXC; xcProxy = checkerXC; } else { + // If checker is not being used, then the xcProxy points + // directly to the CPU's ExecContext. checker = NULL; thread.xcProxy = &ozoneXC; xcProxy = &ozoneXC; } + // Add xcProxy to CPU list of ExecContexts. + execContexts.push_back(xcProxy); + + // Give the OzoneXC pointers to the CPU and the thread state. ozoneXC.cpu = this; ozoneXC.thread = &thread; @@ -134,7 +129,7 @@ OzoneCPU::OzoneCPU(Params *p) thread.setStatus(ExecContext::Suspended); #if FULL_SYSTEM - /***** All thread state stuff *****/ + // Setup thread state stuff. thread.cpu = this; thread.tid = 0; thread.mem = p->mem; @@ -171,8 +166,7 @@ OzoneCPU::OzoneCPU(Params *p) numInst = 0; startNumInst = 0; - execContexts.push_back(xcProxy); - + // Give pointers to the front and back end to all things they may need. frontEnd->setCPU(this); backEnd->setCPU(this); @@ -188,12 +182,13 @@ OzoneCPU::OzoneCPU(Params *p) frontEnd->setBackEnd(backEnd); backEnd->setFrontEnd(frontEnd); - decoupledFrontEnd = p->decoupledFrontEnd; - globalSeqNum = 1; checkInterrupts = false; + lockFlag = 0; + + // Setup rename table, initializing all values to ready. for (int i = 0; i < TheISA::TotalNumRegs; ++i) { thread.renameTable[i] = new DynInst(this); thread.renameTable[i]->setResultReady(); @@ -206,8 +201,6 @@ OzoneCPU::OzoneCPU(Params *p) // pTable = p->pTable; #endif - lockFlag = 0; - DPRINTF(OzoneCPU, "OzoneCPU: Created Ozone cpu object.\n"); } @@ -231,14 +224,20 @@ template void OzoneCPU::signalSwitched() { + // Only complete the switchout when both the front end and back + // end have signalled they are ready to switch. if (++switchCount == 2) { backEnd->doSwitchOut(); frontEnd->doSwitchOut(); + if (checker) checker->switchOut(sampler); + _status = SwitchedOut; + if (tickEvent.scheduled()) tickEvent.squash(); + sampler->signalSwitched(); } assert(switchCount <= 2); @@ -793,6 +792,7 @@ OzoneCPU::OzoneXC::takeOverFrom(ExecContext *old_context) thread->quiesceEvent->xc = this; } + // Copy kernel stats pointer from old context. thread->kernelStats = old_context->getKernelStats(); // storeCondFailures = 0; cpu->lockFlag = false; @@ -814,7 +814,11 @@ OzoneCPU::OzoneXC::regStats(const std::string &name) template void OzoneCPU::OzoneXC::serialize(std::ostream &os) -{ } +{ + // Once serialization is added, serialize the quiesce event and + // kernel stats. Will need to make sure there aren't multiple + // things that serialize them. +} template void @@ -867,7 +871,6 @@ OzoneCPU::OzoneXC::getThreadNum() return thread->tid; } -// Also somewhat obnoxious. Really only used for the TLB fault. template TheISA::MachInst OzoneCPU::OzoneXC::getInst() @@ -901,7 +904,7 @@ OzoneCPU::OzoneXC::copyArchRegs(ExecContext *xc) // Need to copy the XC values into the current rename table, // copy the misc regs. - thread->regs.miscRegs.copyMiscRegs(xc); + TheISA::copyMiscRegs(xc, this); } template diff --git a/cpu/ozone/inorder_back_end_impl.hh b/cpu/ozone/inorder_back_end_impl.hh index 5a378ec76..cc92ec92f 100644 --- a/cpu/ozone/inorder_back_end_impl.hh +++ b/cpu/ozone/inorder_back_end_impl.hh @@ -257,7 +257,7 @@ InorderBackEnd::executeInsts() } inst->setExecuted(); - inst->setCompleted(); + inst->setResultReady(); inst->setCanCommit(); instList.pop_front(); diff --git a/cpu/ozone/inst_queue_impl.hh b/cpu/ozone/inst_queue_impl.hh index 0523c68d6..1b9fcdc84 100644 --- a/cpu/ozone/inst_queue_impl.hh +++ b/cpu/ozone/inst_queue_impl.hh @@ -848,13 +848,13 @@ template void InstQueue::addReadyMemInst(DynInstPtr &ready_inst) { - OpClass op_class = ready_inst->opClass(); +// OpClass op_class = ready_inst->opClass(); readyInsts.push(ready_inst); DPRINTF(IQ, "Instruction is ready to issue, putting it onto " "the ready list, PC %#x opclass:%i [sn:%lli].\n", - ready_inst->readPC(), op_class, ready_inst->seqNum); + ready_inst->readPC(), ready_inst->opClass(), ready_inst->seqNum); } /* template @@ -1175,11 +1175,11 @@ InstQueue::addIfReady(DynInstPtr &inst) return; } - OpClass op_class = inst->opClass(); +// OpClass op_class = inst->opClass(); DPRINTF(IQ, "Instruction is ready to issue, putting it onto " "the ready list, PC %#x opclass:%i [sn:%lli].\n", - inst->readPC(), op_class, inst->seqNum); + inst->readPC(), inst->opClass(), inst->seqNum); readyInsts.push(inst); } diff --git a/cpu/ozone/lw_back_end.hh b/cpu/ozone/lw_back_end.hh index 1c03ffb73..19f2b2b61 100644 --- a/cpu/ozone/lw_back_end.hh +++ b/cpu/ozone/lw_back_end.hh @@ -369,37 +369,37 @@ class LWBackEnd /* Stats::Scalar<> dcacheStallCycles; Counter lastDcacheStall; */ - Stats::Vector<> rob_cap_events; - Stats::Vector<> rob_cap_inst_count; - Stats::Vector<> iq_cap_events; - Stats::Vector<> iq_cap_inst_count; + Stats::Vector<> robCapEvents; + Stats::Vector<> robCapInstCount; + Stats::Vector<> iqCapEvents; + Stats::Vector<> iqCapInstCount; // total number of instructions executed - Stats::Vector<> exe_inst; - Stats::Vector<> exe_swp; - Stats::Vector<> exe_nop; - Stats::Vector<> exe_refs; - Stats::Vector<> exe_loads; - Stats::Vector<> exe_branches; + Stats::Vector<> exeInst; + Stats::Vector<> exeSwp; + Stats::Vector<> exeNop; + Stats::Vector<> exeRefs; + Stats::Vector<> exeLoads; + Stats::Vector<> exeBranches; - Stats::Vector<> issued_ops; + Stats::Vector<> issuedOps; // total number of loads forwaded from LSQ stores - Stats::Vector<> lsq_forw_loads; + Stats::Vector<> lsqForwLoads; // total number of loads ignored due to invalid addresses - Stats::Vector<> inv_addr_loads; + Stats::Vector<> invAddrLoads; // total number of software prefetches ignored due to invalid addresses - Stats::Vector<> inv_addr_swpfs; + Stats::Vector<> invAddrSwpfs; // ready loads blocked due to memory disambiguation - Stats::Vector<> lsq_blocked_loads; + Stats::Vector<> lsqBlockedLoads; Stats::Scalar<> lsqInversion; - Stats::Vector<> n_issued_dist; - Stats::VectorDistribution<> issue_delay_dist; + Stats::Vector<> nIssuedDist; + Stats::VectorDistribution<> issueDelayDist; - Stats::VectorDistribution<> queue_res_dist; + Stats::VectorDistribution<> queueResDist; /* Stats::Vector<> stat_fu_busy; Stats::Vector2d<> stat_fuBusy; @@ -417,37 +417,37 @@ class LWBackEnd Stats::Formula commit_ipb; Stats::Formula lsq_inv_rate; */ - Stats::Vector<> writeback_count; - Stats::Vector<> producer_inst; - Stats::Vector<> consumer_inst; - Stats::Vector<> wb_penalized; + Stats::Vector<> writebackCount; + Stats::Vector<> producerInst; + Stats::Vector<> consumerInst; + Stats::Vector<> wbPenalized; - Stats::Formula wb_rate; - Stats::Formula wb_fanout; - Stats::Formula wb_penalized_rate; + Stats::Formula wbRate; + Stats::Formula wbFanout; + Stats::Formula wbPenalizedRate; // total number of instructions committed - Stats::Vector<> stat_com_inst; - Stats::Vector<> stat_com_swp; - Stats::Vector<> stat_com_refs; - Stats::Vector<> stat_com_loads; - Stats::Vector<> stat_com_membars; - Stats::Vector<> stat_com_branches; + Stats::Vector<> statComInst; + Stats::Vector<> statComSwp; + Stats::Vector<> statComRefs; + Stats::Vector<> statComLoads; + Stats::Vector<> statComMembars; + Stats::Vector<> statComBranches; - Stats::Distribution<> n_committed_dist; + Stats::Distribution<> nCommittedDist; - Stats::Scalar<> commit_eligible_samples; - Stats::Vector<> commit_eligible; + Stats::Scalar<> commitEligibleSamples; + Stats::Vector<> commitEligible; Stats::Vector<> squashedInsts; Stats::Vector<> ROBSquashedInsts; - Stats::Scalar<> ROB_fcount; - Stats::Formula ROB_full_rate; + Stats::Scalar<> ROBFcount; + Stats::Formula ROBFullRate; - Stats::Vector<> ROB_count; // cumulative ROB occupancy - Stats::Formula ROB_occ_rate; - Stats::VectorDistribution<> ROB_occ_dist; + Stats::Vector<> ROBCount; // cumulative ROB occupancy + Stats::Formula ROBOccRate; + Stats::VectorDistribution<> ROBOccDist; public: void dumpInsts(); diff --git a/cpu/ozone/lw_back_end_impl.hh b/cpu/ozone/lw_back_end_impl.hh index 41b4ea24b..18b2e8f47 100644 --- a/cpu/ozone/lw_back_end_impl.hh +++ b/cpu/ozone/lw_back_end_impl.hh @@ -251,78 +251,77 @@ void LWBackEnd::regStats() { using namespace Stats; - rob_cap_events + robCapEvents .init(cpu->number_of_threads) .name(name() + ".ROB:cap_events") .desc("number of cycles where ROB cap was active") .flags(total) ; - rob_cap_inst_count + robCapInstCount .init(cpu->number_of_threads) .name(name() + ".ROB:cap_inst") .desc("number of instructions held up by ROB cap") .flags(total) ; - iq_cap_events + iqCapEvents .init(cpu->number_of_threads) .name(name() +".IQ:cap_events" ) .desc("number of cycles where IQ cap was active") .flags(total) ; - iq_cap_inst_count + iqCapInstCount .init(cpu->number_of_threads) .name(name() + ".IQ:cap_inst") .desc("number of instructions held up by IQ cap") .flags(total) ; - - exe_inst + exeInst .init(cpu->number_of_threads) .name(name() + ".ISSUE:count") .desc("number of insts issued") .flags(total) ; - exe_swp + exeSwp .init(cpu->number_of_threads) .name(name() + ".ISSUE:swp") .desc("number of swp insts issued") .flags(total) ; - exe_nop + exeNop .init(cpu->number_of_threads) .name(name() + ".ISSUE:nop") .desc("number of nop insts issued") .flags(total) ; - exe_refs + exeRefs .init(cpu->number_of_threads) .name(name() + ".ISSUE:refs") .desc("number of memory reference insts issued") .flags(total) ; - exe_loads + exeLoads .init(cpu->number_of_threads) .name(name() + ".ISSUE:loads") .desc("number of load insts issued") .flags(total) ; - exe_branches + exeBranches .init(cpu->number_of_threads) .name(name() + ".ISSUE:branches") .desc("Number of branches issued") .flags(total) ; - issued_ops + issuedOps .init(cpu->number_of_threads) .name(name() + ".ISSUE:op_count") .desc("number of insts issued") @@ -339,28 +338,28 @@ LWBackEnd::regStats() // // Other stats // - lsq_forw_loads + lsqForwLoads .init(cpu->number_of_threads) .name(name() + ".LSQ:forw_loads") .desc("number of loads forwarded via LSQ") .flags(total) ; - inv_addr_loads + invAddrLoads .init(cpu->number_of_threads) .name(name() + ".ISSUE:addr_loads") .desc("number of invalid-address loads") .flags(total) ; - inv_addr_swpfs + invAddrSwpfs .init(cpu->number_of_threads) .name(name() + ".ISSUE:addr_swpfs") .desc("number of invalid-address SW prefetches") .flags(total) ; - lsq_blocked_loads + lsqBlockedLoads .init(cpu->number_of_threads) .name(name() + ".LSQ:blocked_loads") .desc("number of ready loads not issued due to memory disambiguation") @@ -372,51 +371,51 @@ LWBackEnd::regStats() .desc("Number of times LSQ instruction issued early") ; - n_issued_dist + nIssuedDist .init(issueWidth + 1) .name(name() + ".ISSUE:issued_per_cycle") .desc("Number of insts issued each cycle") .flags(total | pdf | dist) ; - issue_delay_dist + issueDelayDist .init(Num_OpClasses,0,99,2) .name(name() + ".ISSUE:") .desc("cycles from operands ready to issue") .flags(pdf | cdf) ; - queue_res_dist + queueResDist .init(Num_OpClasses, 0, 99, 2) .name(name() + ".IQ:residence:") .desc("cycles from dispatch to issue") .flags(total | pdf | cdf ) ; for (int i = 0; i < Num_OpClasses; ++i) { - queue_res_dist.subname(i, opClassStrings[i]); + queueResDist.subname(i, opClassStrings[i]); } - writeback_count + writebackCount .init(cpu->number_of_threads) .name(name() + ".WB:count") .desc("cumulative count of insts written-back") .flags(total) ; - producer_inst + producerInst .init(cpu->number_of_threads) .name(name() + ".WB:producers") .desc("num instructions producing a value") .flags(total) ; - consumer_inst + consumerInst .init(cpu->number_of_threads) .name(name() + ".WB:consumers") .desc("num instructions consuming a value") .flags(total) ; - wb_penalized + wbPenalized .init(cpu->number_of_threads) .name(name() + ".WB:penalized") .desc("number of instrctions required to write to 'other' IQ") @@ -424,71 +423,71 @@ LWBackEnd::regStats() ; - wb_penalized_rate + wbPenalizedRate .name(name() + ".WB:penalized_rate") .desc ("fraction of instructions written-back that wrote to 'other' IQ") .flags(total) ; - wb_penalized_rate = wb_penalized / writeback_count; + wbPenalizedRate = wbPenalized / writebackCount; - wb_fanout + wbFanout .name(name() + ".WB:fanout") .desc("average fanout of values written-back") .flags(total) ; - wb_fanout = producer_inst / consumer_inst; + wbFanout = producerInst / consumerInst; - wb_rate + wbRate .name(name() + ".WB:rate") .desc("insts written-back per cycle") .flags(total) ; - wb_rate = writeback_count / cpu->numCycles; + wbRate = writebackCount / cpu->numCycles; - stat_com_inst + statComInst .init(cpu->number_of_threads) .name(name() + ".COM:count") .desc("Number of instructions committed") .flags(total) ; - stat_com_swp + statComSwp .init(cpu->number_of_threads) .name(name() + ".COM:swp_count") .desc("Number of s/w prefetches committed") .flags(total) ; - stat_com_refs + statComRefs .init(cpu->number_of_threads) .name(name() + ".COM:refs") .desc("Number of memory references committed") .flags(total) ; - stat_com_loads + statComLoads .init(cpu->number_of_threads) .name(name() + ".COM:loads") .desc("Number of loads committed") .flags(total) ; - stat_com_membars + statComMembars .init(cpu->number_of_threads) .name(name() + ".COM:membars") .desc("Number of memory barriers committed") .flags(total) ; - stat_com_branches + statComBranches .init(cpu->number_of_threads) .name(name() + ".COM:branches") .desc("Number of branches committed") .flags(total) ; - n_committed_dist + nCommittedDist .init(0,commitWidth,1) .name(name() + ".COM:committed_per_cycle") .desc("Number of insts commited each cycle") @@ -508,14 +507,14 @@ LWBackEnd::regStats() // -> The standard deviation is computed only over cycles where // we reached the BW limit // - commit_eligible + commitEligible .init(cpu->number_of_threads) .name(name() + ".COM:bw_limited") .desc("number of insts not committed due to BW limits") .flags(total) ; - commit_eligible_samples + commitEligibleSamples .name(name() + ".COM:bw_lim_events") .desc("number cycles where commit BW limit reached") ; @@ -532,32 +531,32 @@ LWBackEnd::regStats() .desc("Number of instructions removed from inst list when they reached the head of the ROB") ; - ROB_fcount + ROBFcount .name(name() + ".ROB:full_count") .desc("number of cycles where ROB was full") ; - ROB_count + ROBCount .init(cpu->number_of_threads) .name(name() + ".ROB:occupancy") .desc(name() + ".ROB occupancy (cumulative)") .flags(total) ; - ROB_full_rate + ROBFullRate .name(name() + ".ROB:full_rate") .desc("ROB full per cycle") ; - ROB_full_rate = ROB_fcount / cpu->numCycles; + ROBFullRate = ROBFcount / cpu->numCycles; - ROB_occ_rate + ROBOccRate .name(name() + ".ROB:occ_rate") .desc("ROB occupancy rate") .flags(total) ; - ROB_occ_rate = ROB_count / cpu->numCycles; + ROBOccRate = ROBCount / cpu->numCycles; - ROB_occ_dist + ROBOccDist .init(cpu->number_of_threads,0,numROBEntries,2) .name(name() + ".ROB:occ_dist") .desc("ROB Occupancy per cycle") @@ -660,7 +659,7 @@ LWBackEnd::tick() return; } - ROB_count[0]+= numInsts; + ROBCount[0]+= numInsts; wbCycle = 0; @@ -980,8 +979,8 @@ LWBackEnd::executeInsts() } } - issued_ops[0]+= num_executed; - n_issued_dist[num_executed]++; + issuedOps[0]+= num_executed; + nIssuedDist[num_executed]++; } template @@ -1002,13 +1001,13 @@ LWBackEnd::instToCommit(DynInstPtr &inst) inst->setResultReady(); int dependents = wakeDependents(inst); if (dependents) { - producer_inst[0]++; - consumer_inst[0]+= dependents; + producerInst[0]++; + consumerInst[0]+= dependents; } } } - writeback_count[0]++; + writebackCount[0]++; } #if 0 template @@ -1076,7 +1075,7 @@ LWBackEnd::commitInst(int inst_num) thread->setPC(inst->readPC()); thread->setNextPC(inst->readNextPC()); - inst->reachedCommit = true; + inst->setAtCommit(); // If the instruction is not executed yet, then it is a non-speculative // or store inst. Signal backwards that it should be executed. @@ -1229,6 +1228,9 @@ LWBackEnd::commitInst(int inst_num) inst->traceData = NULL; } + if (inst->isCopy()) + panic("Should not commit any copy instructions!"); + inst->clearDependents(); frontEnd->addFreeRegs(freed_regs); @@ -1292,7 +1294,7 @@ LWBackEnd::commitInsts() break; } } - n_committed_dist.sample(inst_num); + nCommittedDist.sample(inst_num); } template @@ -1344,7 +1346,7 @@ LWBackEnd::squash(const InstSeqNum &sn) (*insts_it)->setCanCommit(); - (*insts_it)->removeInROB(); + (*insts_it)->clearInROB(); for (int i = 0; i < (*insts_it)->numDestRegs(); ++i) { DynInstPtr prev_dest = (*insts_it)->getPrevDestInst(i); @@ -1522,27 +1524,27 @@ LWBackEnd::updateExeInstStats(DynInstPtr &inst) // #ifdef TARGET_ALPHA if (inst->isDataPrefetch()) - exe_swp[thread_number]++; + exeSwp[thread_number]++; else - exe_inst[thread_number]++; + exeInst[thread_number]++; #else - exe_inst[thread_number]++; + exeInst[thread_number]++; #endif // // Control operations // if (inst->isControl()) - exe_branches[thread_number]++; + exeBranches[thread_number]++; // // Memory operations // if (inst->isMemRef()) { - exe_refs[thread_number]++; + exeRefs[thread_number]++; if (inst->isLoad()) - exe_loads[thread_number]++; + exeLoads[thread_number]++; } } @@ -1562,33 +1564,33 @@ LWBackEnd::updateComInstStats(DynInstPtr &inst) // #ifdef TARGET_ALPHA if (inst->isDataPrefetch()) { - stat_com_swp[tid]++; + statComSwp[tid]++; } else { - stat_com_inst[tid]++; + statComInst[tid]++; } #else - stat_com_inst[tid]++; + statComInst[tid]++; #endif // // Control Instructions // if (inst->isControl()) - stat_com_branches[tid]++; + statComBranches[tid]++; // // Memory references // if (inst->isMemRef()) { - stat_com_refs[tid]++; + statComRefs[tid]++; if (inst->isLoad()) { - stat_com_loads[tid]++; + statComLoads[tid]++; } } if (inst->isMemBarrier()) { - stat_com_membars[tid]++; + statComMembars[tid]++; } } diff --git a/cpu/ozone/lw_lsq.hh b/cpu/ozone/lw_lsq.hh index 6fe343b42..c0bf0b0fe 100644 --- a/cpu/ozone/lw_lsq.hh +++ b/cpu/ozone/lw_lsq.hh @@ -447,7 +447,7 @@ OzoneLWLSQ::read(MemReqPtr &req, T &data, int load_idx) // too). // @todo: Fix uncached accesses. if (req->flags & UNCACHEABLE && - (inst != loadQueue.back() || !inst->reachedCommit)) { + (inst != loadQueue.back() || !inst->isAtCommit())) { DPRINTF(OzoneLSQ, "[sn:%lli] Uncached load and not head of " "commit/LSQ!\n", inst->seqNum); diff --git a/cpu/ozone/thread_state.hh b/cpu/ozone/thread_state.hh index c86c3a720..f104dff23 100644 --- a/cpu/ozone/thread_state.hh +++ b/cpu/ozone/thread_state.hh @@ -182,8 +182,6 @@ struct OzoneThreadState : public ThreadState { void setNextPC(uint64_t val) { nextPC = val; } - bool misspeculating() { return false; } - void setInst(TheISA::MachInst _inst) { inst = _inst; } Counter readFuncExeInst() { return funcExeInst; } diff --git a/cpu/thread_state.hh b/cpu/thread_state.hh index e09cb12fd..12146bd11 100644 --- a/cpu/thread_state.hh +++ b/cpu/thread_state.hh @@ -60,6 +60,7 @@ struct ThreadState { : cpuId(_cpuId), tid(_tid), mem(_mem), process(_process), asid(_asid) #endif { + numInst = 0; funcExeInst = 0; storeCondFailures = 0; } diff --git a/python/m5/objects/AlphaFullCPU.py b/python/m5/objects/AlphaFullCPU.py index 043c3c08f..015e9d872 100644 --- a/python/m5/objects/AlphaFullCPU.py +++ b/python/m5/objects/AlphaFullCPU.py @@ -39,12 +39,10 @@ class DerivAlphaFullCPU(BaseCPU): "Issue/Execute/Writeback delay") issueToExecuteDelay = Param.Unsigned("Issue to execute delay (internal " "to the IEW stage)") - issueWidth = Param.Unsigned("Issue width") - executeWidth = Param.Unsigned("Execute width") - executeIntWidth = Param.Unsigned("Integer execute width") - executeFloatWidth = Param.Unsigned("Floating point execute width") - executeBranchWidth = Param.Unsigned("Branch execute width") - executeMemoryWidth = Param.Unsigned("Memory execute width") + dispatchWidth = Param.Unsigned(8, "Dispatch width") + issueWidth = Param.Unsigned(8, "Issue width") + wbWidth = Param.Unsigned(8, "Writeback width") + wbDepth = Param.Unsigned(1, "Writeback depth") fuPool = Param.FUPool(NULL, "Functional Unit pool") iewToCommitDelay = Param.Unsigned("Issue/Execute/Writeback to commit " @@ -55,6 +53,9 @@ class DerivAlphaFullCPU(BaseCPU): trapLatency = Param.Tick("Trap latency") fetchTrapLatency = Param.Tick("Fetch trap latency") + backComSize = Param.Unsigned(5, "Time buffer size for backwards communication") + forwardComSize = Param.Unsigned(5, "Time buffer size for forward communication") + predType = Param.String("Branch predictor type ('local', 'tournament')") localPredictorSize = Param.Unsigned("Size of local predictor") localCtrBits = Param.Unsigned("Bits per counter") From 5be592f870d1d59cffe9a5d1eebac66b225ff8ef Mon Sep 17 00:00:00 2001 From: Kevin Lim Date: Wed, 2 Aug 2006 12:06:59 -0400 Subject: [PATCH 04/20] Make checker handle not executing the same instruction as the main CPU a little better. Also add the option for the checker to update itself with the main CPU's state if it executes an instruction differently (so it will handle DMA timing errors properly). --HG-- extra : convert_revision : 760d11ec1a249bc75e2807d320866b5d08c2b6f2 --- cpu/checker/cpu.cc | 30 ++++++++++++++++++++++++++---- cpu/checker/cpu.hh | 23 +++++++++++++++++------ cpu/checker/cpu_builder.cc | 3 +++ 3 files changed, 46 insertions(+), 10 deletions(-) diff --git a/cpu/checker/cpu.cc b/cpu/checker/cpu.cc index 41ff6e769..f195c8842 100644 --- a/cpu/checker/cpu.cc +++ b/cpu/checker/cpu.cc @@ -78,6 +78,7 @@ CheckerCPU::CheckerCPU(Params *p) changedPC = willChangePC = changedNextPC = false; exitOnError = p->exitOnError; + updateOnError = p->updateOnError; #if FULL_SYSTEM itb = p->itb; dtb = p->dtb; @@ -350,7 +351,12 @@ CheckerCPU::translateDataReadReq(MemReqPtr &req) { cpuXC->translateDataReadReq(req); - if (req->vaddr != unverifiedReq->vaddr) { + if (!unverifiedReq) { + warn("%lli: Request virtual addresses do not match! Inst: N/A, " + "checker: %#x", + curTick, req->vaddr); + return; + } else if (req->vaddr != unverifiedReq->vaddr) { warn("%lli: Request virtual addresses do not match! Inst: %#x, " "checker: %#x", curTick, unverifiedReq->vaddr, req->vaddr); @@ -370,7 +376,12 @@ CheckerCPU::translateDataWriteReq(MemReqPtr &req) { cpuXC->translateDataWriteReq(req); - if (req->vaddr != unverifiedReq->vaddr) { + if (!unverifiedReq) { + warn("%lli: Request virtual addresses do not match! Inst: N/A, " + "checker: %#x", + curTick, req->vaddr); + return; + } else if (req->vaddr != unverifiedReq->vaddr) { warn("%lli: Request virtual addresses do not match! Inst: %#x, " "checker: %#x", curTick, unverifiedReq->vaddr, req->vaddr); @@ -443,6 +454,8 @@ Checker::tick(DynInstPtr &completed_inst) } } + unverifiedInst = inst; + // Try to check all instructions that are completed, ending if we // run out of instructions to check or if an instruction is not // yet completed. @@ -516,7 +529,7 @@ Checker::tick(DynInstPtr &completed_inst) cpuXC->setPC(cpuXC->readNextPC()); cpuXC->setNextPC(cpuXC->readNextPC() + sizeof(MachInst)); - return; + break; } else { // The instruction is carrying an ITB fault. Handle // the fault and see if our results match the CPU on @@ -554,7 +567,8 @@ Checker::tick(DynInstPtr &completed_inst) cpuXC->func_exe_inst++; - fault = curStaticInst->execute(this, NULL); + if (!inst->isUnverifiable()) + fault = curStaticInst->execute(this, NULL); // Checks to make sure instrution results are correct. validateExecution(inst); @@ -620,6 +634,7 @@ Checker::tick(DynInstPtr &completed_inst) break; } } + unverifiedInst = NULL; } template @@ -718,6 +733,13 @@ template void Checker::validateState() { + if (updateThisCycle) { + warn("%lli: Instruction PC %#x results didn't match up, copying all " + "registers from main CPU", unverifiedInst->readPC()); + // Heavy-weight copying of all registers + cpuXC->copyArchRegs(unverifiedInst->xcBase()); + updateThisCycle = false; + } } template diff --git a/cpu/checker/cpu.hh b/cpu/checker/cpu.hh index 9fcd1037f..f48d1135a 100644 --- a/cpu/checker/cpu.hh +++ b/cpu/checker/cpu.hh @@ -98,6 +98,7 @@ class CheckerCPU : public BaseCPU Process *process; #endif bool exitOnError; + bool updateOnError; }; public: @@ -294,11 +295,8 @@ class CheckerCPU : public BaseCPU void syscall() { } #endif - void handleError() - { - if (exitOnError) - panic("Checker found error!"); - } + virtual void handleError() = 0; + bool checkFlags(MemReqPtr &req); ExecContext *xcBase() { return xcProxy; } @@ -312,6 +310,7 @@ class CheckerCPU : public BaseCPU uint64_t newPC; bool changedNextPC; bool exitOnError; + bool updateOnError; InstSeqNum youngestSN; }; @@ -327,7 +326,7 @@ class Checker : public CheckerCPU { public: Checker(Params *p) - : CheckerCPU(p) + : CheckerCPU(p), updateThisCycle(false), unverifiedInst(NULL) { } void switchOut(Sampler *s); @@ -339,6 +338,18 @@ class Checker : public CheckerCPU void validateExecution(DynInstPtr &inst); void validateState(); + virtual void handleError() + { + if (exitOnError) + panic("Checker found error!"); + else if (updateOnError) + updateThisCycle = true; + } + + bool updateThisCycle; + + DynInstPtr unverifiedInst; + std::list instList; typedef typename std::list::iterator InstListIt; void dumpInsts(); diff --git a/cpu/checker/cpu_builder.cc b/cpu/checker/cpu_builder.cc index d80daef97..802944e47 100644 --- a/cpu/checker/cpu_builder.cc +++ b/cpu/checker/cpu_builder.cc @@ -75,6 +75,7 @@ BEGIN_DECLARE_SIM_OBJECT_PARAMS(OzoneChecker) Param defer_registration; Param exitOnError; + Param updateOnError; Param function_trace; Param function_trace_start; @@ -108,6 +109,7 @@ BEGIN_INIT_SIM_OBJECT_PARAMS(OzoneChecker) INIT_PARAM(defer_registration, "defer system registration (for sampling)"), INIT_PARAM(exitOnError, "exit on error"), + INIT_PARAM(updateOnError, "Update the checker with the main CPU's state on error"), INIT_PARAM(function_trace, "Enable function trace"), INIT_PARAM(function_trace_start, "Cycle to start function trace") @@ -124,6 +126,7 @@ CREATE_SIM_OBJECT(OzoneChecker) params->max_loads_any_thread = 0; params->max_loads_all_threads = 0; params->exitOnError = exitOnError; + params->updateOnError = updateOnError; params->deferRegistration = defer_registration; params->functionTrace = function_trace; params->functionTraceStart = function_trace_start; From 5ec58c4bdc2ffa8c650a784efc5a342a3ad36810 Mon Sep 17 00:00:00 2001 From: Kevin Lim Date: Wed, 2 Aug 2006 12:07:44 -0400 Subject: [PATCH 05/20] Fix up some ISA related stuff. arch/alpha/isa/decoder.isa: Marked a few more instructions as unverifiable. arch/alpha/isa/mem.isa: Warn instead of panic, otherwise this can cause the simulation to fail even if the instruction is never committed. --HG-- extra : convert_revision : 12befc6fedd1a6883d0517e649ad01b91fb561ae --- arch/alpha/isa/decoder.isa | 6 +++--- arch/alpha/isa/mem.isa | 4 ++-- 2 files changed, 5 insertions(+), 5 deletions(-) diff --git a/arch/alpha/isa/decoder.isa b/arch/alpha/isa/decoder.isa index b3744a43d..71b9131aa 100644 --- a/arch/alpha/isa/decoder.isa +++ b/arch/alpha/isa/decoder.isa @@ -694,7 +694,7 @@ decode OPCODE default Unknown::unknown() { }}, IsNonSpeculative); 0x83: callsys({{ xc->syscall(); - }}, IsNonSpeculative); + }}, IsNonSpeculative, IsSerializeAfter); // Read uniq reg into ABI return value register (r0) 0x9e: rduniq({{ R0 = Runiq; }}, IsIprAccess); // Write uniq reg with value from ABI arg register (r16) @@ -768,10 +768,10 @@ decode OPCODE default Unknown::unknown() { }}, IsNonSpeculative, IsQuiesce); 0x03: quiesceCycles({{ AlphaPseudo::quiesceCycles(xc->xcBase(), R16); - }}, IsNonSpeculative, IsQuiesce); + }}, IsNonSpeculative, IsQuiesce, IsUnverifiable); 0x04: quiesceTime({{ R0 = AlphaPseudo::quiesceTime(xc->xcBase()); - }}, IsNonSpeculative); + }}, IsNonSpeculative, IsUnverifiable); 0x10: ivlb({{ AlphaPseudo::ivlb(xc->xcBase()); }}, No_OpClass, IsNonSpeculative); diff --git a/arch/alpha/isa/mem.isa b/arch/alpha/isa/mem.isa index 3c8b4f755..5d29c18bc 100644 --- a/arch/alpha/isa/mem.isa +++ b/arch/alpha/isa/mem.isa @@ -500,7 +500,7 @@ def template MiscInitiateAcc {{ Fault %(class_name)s::initiateAcc(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const { - panic("Misc instruction does not support split access method!"); + warn("Misc instruction does not support split access method!"); return NoFault; } }}; @@ -511,7 +511,7 @@ def template MiscCompleteAcc {{ %(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const { - panic("Misc instruction does not support split access method!"); + warn("Misc instruction does not support split access method!"); return NoFault; } From 716ceb6c107751fded501f18466a4166b7809e64 Mon Sep 17 00:00:00 2001 From: Kevin Lim Date: Fri, 11 Aug 2006 17:42:59 -0400 Subject: [PATCH 06/20] Code update for CPU models. arch/alpha/isa_traits.hh: Add in clear functions. cpu/base.cc: cpu/base.hh: Add in CPU progress event. cpu/base_dyn_inst.hh: Mimic normal registers in terms of writing/reading floats. cpu/checker/cpu.cc: cpu/checker/cpu.hh: cpu/checker/cpu_builder.cc: cpu/checker/o3_cpu_builder.cc: Fix up stuff. cpu/cpu_exec_context.cc: cpu/cpu_exec_context.hh: cpu/o3/cpu.cc: cpu/o3/cpu.hh: Bring up to speed with newmem. cpu/o3/alpha_cpu_builder.cc: Allow for progress intervals. cpu/o3/tournament_pred.cc: Fix up predictor. cpu/o3/tournament_pred.hh: cpu/ozone/cpu.hh: cpu/ozone/cpu_impl.hh: cpu/simple/cpu.cc: Fixes. cpu/ozone/cpu_builder.cc: Allow progress interval. cpu/ozone/front_end_impl.hh: Comment out this message. cpu/ozone/lw_back_end_impl.hh: Remove this. python/m5/objects/BaseCPU.py: Add progress interval. python/m5/objects/Root.py: Allow for stat reset. sim/serialize.cc: sim/stat_control.cc: Add in stats reset. --HG-- extra : convert_revision : fdb5ac5542099173cc30c40ea93372a065534b5e --- arch/alpha/isa_traits.hh | 10 +++++++ cpu/base.cc | 26 +++++++++++++++- cpu/base.hh | 18 +++++++++++ cpu/base_dyn_inst.hh | 7 +++-- cpu/checker/cpu.cc | 13 +++++++- cpu/checker/cpu.hh | 2 +- cpu/checker/cpu_builder.cc | 4 +++ cpu/checker/o3_cpu_builder.cc | 7 +++++ cpu/cpu_exec_context.cc | 56 ++++++++++++++++++++++++++++++----- cpu/cpu_exec_context.hh | 7 +++++ cpu/o3/alpha_cpu_builder.cc | 3 ++ cpu/o3/cpu.cc | 17 ++++++----- cpu/o3/cpu.hh | 7 +++++ cpu/o3/tournament_pred.cc | 10 +++++-- cpu/o3/tournament_pred.hh | 3 ++ cpu/ozone/cpu.hh | 2 -- cpu/ozone/cpu_builder.cc | 3 ++ cpu/ozone/cpu_impl.hh | 28 ++++++++++++++---- cpu/ozone/front_end_impl.hh | 2 +- cpu/ozone/lw_back_end_impl.hh | 1 - cpu/simple/cpu.cc | 7 +++-- python/m5/objects/BaseCPU.py | 1 + python/m5/objects/Root.py | 2 ++ sim/serialize.cc | 36 ++++++++++++++++++++++ sim/stat_control.cc | 4 ++- 25 files changed, 241 insertions(+), 35 deletions(-) diff --git a/arch/alpha/isa_traits.hh b/arch/alpha/isa_traits.hh index 515ec933b..6f5cae9ef 100644 --- a/arch/alpha/isa_traits.hh +++ b/arch/alpha/isa_traits.hh @@ -168,6 +168,9 @@ namespace AlphaISA typedef union { uint64_t q[NumFloatRegs]; // integer qword view double d[NumFloatRegs]; // double-precision floating point view + + void clear() + { bzero(d, sizeof(d)); } } FloatRegFile; extern const Addr PageShift; @@ -266,6 +269,13 @@ extern const int reg_redir[NumIntRegs]; void serialize(std::ostream &os); void unserialize(Checkpoint *cp, const std::string §ion); + + void clear() + { + bzero(intRegFile, sizeof(intRegFile)); + floatRegFile.clear(); + miscRegs.clear(); + } }; static inline ExtMachInst makeExtMI(MachInst inst, const uint64_t &pc); diff --git a/cpu/base.cc b/cpu/base.cc index de03b9eab..36950a683 100644 --- a/cpu/base.cc +++ b/cpu/base.cc @@ -54,6 +54,26 @@ vector BaseCPU::cpuList; // been initialized int maxThreadsPerCPU = 1; +void +CPUProgressEvent::process() +{ +#ifndef NDEBUG + Counter temp = cpu->totalInstructions(); + double ipc = double(temp - lastNumInst) / (interval / cpu->cycles(1)); + DPRINTFN("%s progress event, instructions committed: %lli, IPC: %0.8d\n", + cpu->name(), temp - lastNumInst, ipc); + ipc = 0.0; + lastNumInst = temp; + schedule(curTick + interval); +#endif +} + +const char * +CPUProgressEvent::description() +{ + return "CPU Progress event"; +} + #if FULL_SYSTEM BaseCPU::BaseCPU(Params *p) : SimObject(p->name), clock(p->clock), checkInterrupts(true), @@ -150,7 +170,6 @@ BaseCPU::BaseCPU(Params *p) if (params->profile) profileEvent = new ProfileEvent(this, params->profile); #endif - } BaseCPU::Params::Params() @@ -185,6 +204,11 @@ BaseCPU::startup() if (!params->deferRegistration && profileEvent) profileEvent->schedule(curTick); #endif + + if (params->progress_interval) { + new CPUProgressEvent(&mainEventQueue, params->progress_interval, + this); + } } diff --git a/cpu/base.hh b/cpu/base.hh index dd776859d..4f1578f67 100644 --- a/cpu/base.hh +++ b/cpu/base.hh @@ -43,6 +43,23 @@ class CheckerCPU; class ExecContext; class System; +class CPUProgressEvent : public Event +{ + protected: + Tick interval; + Counter lastNumInst; + BaseCPU *cpu; + + public: + CPUProgressEvent(EventQueue *q, Tick ival, BaseCPU *_cpu) + : Event(q, Event::Stat_Event_Pri), interval(ival), lastNumInst(0), cpu(_cpu) + { schedule(curTick + interval); } + + void process(); + + virtual const char *description(); +}; + class BaseCPU : public SimObject { protected: @@ -125,6 +142,7 @@ class BaseCPU : public SimObject int cpu_id; Tick profile; #endif + Tick progress_interval; BaseCPU *checker; Params(); diff --git a/cpu/base_dyn_inst.hh b/cpu/base_dyn_inst.hh index 01f6be185..6333a1fb1 100644 --- a/cpu/base_dyn_inst.hh +++ b/cpu/base_dyn_inst.hh @@ -200,7 +200,7 @@ class BaseDynInst : public FastAlloc, public RefCounted union Result { uint64_t integer; - float fp; +// float fp; double dbl; }; @@ -394,7 +394,7 @@ class BaseDynInst : public FastAlloc, public RefCounted uint64_t readIntResult() { return instResult.integer; } /** Returns the result of a floating point instruction. */ - float readFloatResult() { return instResult.fp; } + float readFloatResult() { return (float)instResult.dbl; } /** Returns the result of a floating point (double) instruction. */ double readDoubleResult() { return instResult.dbl; } @@ -406,7 +406,8 @@ class BaseDynInst : public FastAlloc, public RefCounted void setFloatRegSingle(const StaticInst *si, int idx, float val) { - instResult.fp = val; +// instResult.fp = val; + instResult.dbl = (double)val; } void setFloatRegDouble(const StaticInst *si, int idx, double val) diff --git a/cpu/checker/cpu.cc b/cpu/checker/cpu.cc index f195c8842..071559b7c 100644 --- a/cpu/checker/cpu.cc +++ b/cpu/checker/cpu.cc @@ -735,9 +735,20 @@ Checker::validateState() { if (updateThisCycle) { warn("%lli: Instruction PC %#x results didn't match up, copying all " - "registers from main CPU", unverifiedInst->readPC()); + "registers from main CPU", curTick, unverifiedInst->readPC()); // Heavy-weight copying of all registers cpuXC->copyArchRegs(unverifiedInst->xcBase()); + // Also advance the PC. Hopefully no PC-based events happened. +#if THE_ISA != MIPS_ISA + // go to the next instruction + cpuXC->setPC(cpuXC->readNextPC()); + cpuXC->setNextPC(cpuXC->readNextPC() + sizeof(MachInst)); +#else + // go to the next instruction + cpuXC->setPC(cpuXC->readNextPC()); + cpuXC->setNextPC(cpuXC->readNextNPC()); + cpuXC->setNextNPC(cpuXC->readNextNPC() + sizeof(MachInst)); +#endif updateThisCycle = false; } } diff --git a/cpu/checker/cpu.hh b/cpu/checker/cpu.hh index f48d1135a..3000cee92 100644 --- a/cpu/checker/cpu.hh +++ b/cpu/checker/cpu.hh @@ -151,7 +151,7 @@ class CheckerCPU : public BaseCPU virtual Counter totalInstructions() const { - return numInst - startNumInst; + return 0; } // number of simulated loads diff --git a/cpu/checker/cpu_builder.cc b/cpu/checker/cpu_builder.cc index 802944e47..d1b5434c3 100644 --- a/cpu/checker/cpu_builder.cc +++ b/cpu/checker/cpu_builder.cc @@ -58,6 +58,7 @@ BEGIN_DECLARE_SIM_OBJECT_PARAMS(OzoneChecker) Param max_insts_all_threads; Param max_loads_any_thread; Param max_loads_all_threads; + Param progress_interval; #if FULL_SYSTEM SimObjectParam itb; @@ -91,6 +92,7 @@ BEGIN_INIT_SIM_OBJECT_PARAMS(OzoneChecker) "terminate when any thread reaches this load count"), INIT_PARAM(max_loads_all_threads, "terminate when all threads have reached this load count"), + INIT_PARAM_DFLT(progress_interval, "CPU Progress Interval", 0), #if FULL_SYSTEM INIT_PARAM(itb, "Instruction TLB"), @@ -138,6 +140,8 @@ CREATE_SIM_OBJECT(OzoneChecker) temp = max_insts_all_threads; temp = max_loads_any_thread; temp = max_loads_all_threads; + Tick temp2 = progress_interval; + temp2++; BaseMem *cache = icache; cache = dcache; diff --git a/cpu/checker/o3_cpu_builder.cc b/cpu/checker/o3_cpu_builder.cc index 410f91352..496cca779 100644 --- a/cpu/checker/o3_cpu_builder.cc +++ b/cpu/checker/o3_cpu_builder.cc @@ -58,6 +58,7 @@ BEGIN_DECLARE_SIM_OBJECT_PARAMS(O3Checker) Param max_insts_all_threads; Param max_loads_any_thread; Param max_loads_all_threads; + Param progress_interval; #if FULL_SYSTEM SimObjectParam itb; @@ -75,6 +76,7 @@ BEGIN_DECLARE_SIM_OBJECT_PARAMS(O3Checker) Param defer_registration; Param exitOnError; + Param updateOnError; Param function_trace; Param function_trace_start; @@ -90,6 +92,7 @@ BEGIN_INIT_SIM_OBJECT_PARAMS(O3Checker) "terminate when any thread reaches this load count"), INIT_PARAM(max_loads_all_threads, "terminate when all threads have reached this load count"), + INIT_PARAM_DFLT(progress_interval, "CPU Progress Interval", 0), #if FULL_SYSTEM INIT_PARAM(itb, "Instruction TLB"), @@ -108,6 +111,7 @@ BEGIN_INIT_SIM_OBJECT_PARAMS(O3Checker) INIT_PARAM(defer_registration, "defer system registration (for sampling)"), INIT_PARAM(exitOnError, "exit on error"), + INIT_PARAM(updateOnError, "Update the checker with the main CPU's state on error"), INIT_PARAM(function_trace, "Enable function trace"), INIT_PARAM(function_trace_start, "Cycle to start function trace") @@ -124,6 +128,7 @@ CREATE_SIM_OBJECT(O3Checker) params->max_loads_any_thread = 0; params->max_loads_all_threads = 0; params->exitOnError = exitOnError; + params->updateOnError = updateOnError; params->deferRegistration = defer_registration; params->functionTrace = function_trace; params->functionTraceStart = function_trace_start; @@ -135,6 +140,8 @@ CREATE_SIM_OBJECT(O3Checker) temp = max_insts_all_threads; temp = max_loads_any_thread; temp = max_loads_all_threads; + Tick temp2 = progress_interval; + temp2++; BaseMem *cache = icache; cache = dcache; diff --git a/cpu/cpu_exec_context.cc b/cpu/cpu_exec_context.cc index e28c34f88..0dcf149fd 100644 --- a/cpu/cpu_exec_context.cc +++ b/cpu/cpu_exec_context.cc @@ -118,6 +118,20 @@ CPUExecContext::CPUExecContext(RegFile *regFile) #endif +CPUExecContext::CPUExecContext() +#if !FULL_SYSTEM + : cpu(NULL), thread_num(-1), process(NULL), mem(NULL), asid(-1), + func_exe_inst(0), storeCondFailures(0) +#else + : cpu(NULL), thread_num(-1), cpu_id(-1), lastActivate(0), lastSuspend(0), + mem(NULL), itb(NULL), dtb(NULL), system(NULL), memctrl(NULL), + physmem(NULL), profile(NULL), func_exe_inst(0), storeCondFailures(0) +#endif +{ + regs.clear(); + proxy = new ProxyExecContext(this); +} + CPUExecContext::~CPUExecContext() { delete proxy; @@ -158,13 +172,8 @@ CPUExecContext::takeOverFrom(ExecContext *oldContext) assert(process == oldContext->getProcessPtr()); #endif - // copy over functional state - _status = oldContext->status(); - copyArchRegs(oldContext); - cpu_id = oldContext->readCpuId(); -#if !FULL_SYSTEM - func_exe_inst = oldContext->readFuncExeInst(); -#else + copyState(oldContext); +#if FULL_SYSTEM EndQuiesceEvent *quiesce = oldContext->getQuiesceEvent(); if (quiesce) { // Point the quiesce event's XC at this XC so that it wakes up @@ -181,6 +190,36 @@ CPUExecContext::takeOverFrom(ExecContext *oldContext) oldContext->setStatus(ExecContext::Unallocated); } +void +CPUExecContext::copyXC(ExecContext *context) +{ + copyState(context); + +#if FULL_SYSTEM + EndQuiesceEvent *quiesce = context->getQuiesceEvent(); + if (quiesce) { + quiesceEvent = quiesce; + } + Kernel::Statistics *stats = context->getKernelStats(); + if (stats) { + kernelStats = stats; + } +#endif +} + +void +CPUExecContext::copyState(ExecContext *oldContext) +{ + // copy over functional state + _status = oldContext->status(); + copyArchRegs(oldContext); + cpu_id = oldContext->readCpuId(); +#if !FULL_SYSTEM + func_exe_inst = oldContext->readFuncExeInst(); +#endif + inst = oldContext->getInst(); +} + void CPUExecContext::serialize(ostream &os) { @@ -294,6 +333,8 @@ CPUExecContext::regStats(const string &name) void CPUExecContext::copyArchRegs(ExecContext *xc) { + TheISA::copyRegs(xc, proxy); +/* // First loop through the integer registers. for (int i = 0; i < AlphaISA::NumIntRegs; ++i) { setIntReg(i, xc->readIntReg(i)); @@ -311,5 +352,6 @@ CPUExecContext::copyArchRegs(ExecContext *xc) // Lastly copy PC/NPC setPC(xc->readPC()); setNextPC(xc->readNextPC()); +*/ } diff --git a/cpu/cpu_exec_context.hh b/cpu/cpu_exec_context.hh index 061fe450a..619d07d3a 100644 --- a/cpu/cpu_exec_context.hh +++ b/cpu/cpu_exec_context.hh @@ -203,12 +203,19 @@ class CPUExecContext // else. CPUExecContext(RegFile *regFile); #endif + + CPUExecContext(); + virtual ~CPUExecContext(); virtual void takeOverFrom(ExecContext *oldContext); void regStats(const std::string &name); + void copyXC(ExecContext *context); + + void copyState(ExecContext *oldContext); + void serialize(std::ostream &os); void unserialize(Checkpoint *cp, const std::string §ion); diff --git a/cpu/o3/alpha_cpu_builder.cc b/cpu/o3/alpha_cpu_builder.cc index c563fbef3..fa0e892aa 100644 --- a/cpu/o3/alpha_cpu_builder.cc +++ b/cpu/o3/alpha_cpu_builder.cc @@ -68,6 +68,7 @@ Param max_insts_any_thread; Param max_insts_all_threads; Param max_loads_any_thread; Param max_loads_all_threads; +Param progress_interval; SimObjectParam icache; SimObjectParam dcache; @@ -189,6 +190,7 @@ BEGIN_INIT_SIM_OBJECT_PARAMS(DerivAlphaFullCPU) "Terminate when all threads have reached this load" "count", 0), + INIT_PARAM_DFLT(progress_interval, "Progress interval", 0), INIT_PARAM_DFLT(icache, "L1 instruction cache", NULL), INIT_PARAM_DFLT(dcache, "L1 data cache", NULL), @@ -327,6 +329,7 @@ CREATE_SIM_OBJECT(DerivAlphaFullCPU) params->max_insts_all_threads = max_insts_all_threads; params->max_loads_any_thread = max_loads_any_thread; params->max_loads_all_threads = max_loads_all_threads; + params->progress_interval = progress_interval; // // Caches diff --git a/cpu/o3/cpu.cc b/cpu/o3/cpu.cc index f1571e61b..0025d4144 100644 --- a/cpu/o3/cpu.cc +++ b/cpu/o3/cpu.cc @@ -29,6 +29,7 @@ #include "config/full_system.hh" #if FULL_SYSTEM +#include "cpu/quiesce_event.hh" #include "sim/system.hh" #else #include "sim/process.hh" @@ -598,6 +599,9 @@ FullO3CPU::activateContext(int tid, int delay) // Be sure to signal that there's some activity so the CPU doesn't // deschedule itself. activityRec.activity(); + if (thread[tid]->quiesceEvent && thread[tid]->quiesceEvent->scheduled()) + thread[tid]->quiesceEvent->deschedule(); + fetch.wakeFromQuiesce(); _status = Running; @@ -759,7 +763,6 @@ FullO3CPU::takeOverFrom(BaseCPU *oldCPU) tickEvent.schedule(curTick); } -/* template void FullO3CPU::serialize(std::ostream &os) @@ -771,11 +774,11 @@ FullO3CPU::serialize(std::ostream &os) // Use SimpleThread's ability to checkpoint to make it easier to // write out the registers. Also make this static so it doesn't // get instantiated multiple times (causes a panic in statistics). - static SimpleThread temp; + static CPUExecContext temp; for (int i = 0; i < thread.size(); i++) { nameOut(os, csprintf("%s.xc.%i", name(), i)); - temp.copyXC(thread[i]->getXC()); + temp.copyXC(thread[i]->getXCProxy()); temp.serialize(os); } } @@ -790,15 +793,15 @@ FullO3CPU::unserialize(Checkpoint *cp, const std::string §ion) // Use SimpleThread's ability to checkpoint to make it easier to // read in the registers. Also make this static so it doesn't // get instantiated multiple times (causes a panic in statistics). - static SimpleThread temp; + static CPUExecContext temp; for (int i = 0; i < thread.size(); i++) { - temp.copyXC(thread[i]->getXC()); + temp.copyXC(thread[i]->getXCProxy()); temp.unserialize(cp, csprintf("%s.xc.%i", section, i)); - thread[i]->getXC()->copyArchRegs(temp.getXC()); + thread[i]->getXCProxy()->copyArchRegs(temp.getProxy()); } } -*/ + template uint64_t FullO3CPU::readIntReg(int reg_idx) diff --git a/cpu/o3/cpu.hh b/cpu/o3/cpu.hh index ef5c9ae53..4d4adca5a 100644 --- a/cpu/o3/cpu.hh +++ b/cpu/o3/cpu.hh @@ -198,6 +198,13 @@ class FullO3CPU : public BaseFullCPU /** Update The Order In Which We Process Threads. */ void updateThreadPriority(); + /** Serialize state. */ + virtual void serialize(std::ostream &os); + + /** Unserialize from a checkpoint. */ + virtual void unserialize(Checkpoint *cp, const std::string §ion); + + public: /** Executes a syscall on this cycle. * --------------------------------------- * Note: this is a virtual function. CPU-Specific diff --git a/cpu/o3/tournament_pred.cc b/cpu/o3/tournament_pred.cc index f8c95abd8..8b1af6c7c 100644 --- a/cpu/o3/tournament_pred.cc +++ b/cpu/o3/tournament_pred.cc @@ -60,6 +60,8 @@ TournamentBP::TournamentBP(unsigned _localPredictorSize, for (int i = 0; i < localPredictorSize; ++i) localCtrs[i].setBits(localCtrBits); + localPredictorMask = floorPow2(localPredictorSize) - 1; + if (!isPowerOf2(localHistoryTableSize)) { fatal("Invalid local history table size!\n"); } @@ -156,7 +158,7 @@ TournamentBP::lookup(Addr &branch_addr, void * &bp_history) //Lookup in the local predictor to get its branch prediction local_history_idx = calcLocHistIdx(branch_addr); local_predictor_idx = localHistoryTable[local_history_idx] - & localHistoryMask; + & localPredictorMask; local_prediction = localCtrs[local_predictor_idx].read() > threshold; //Lookup in the global predictor to get its branch prediction @@ -174,7 +176,8 @@ TournamentBP::lookup(Addr &branch_addr, void * &bp_history) bp_history = (void *)history; assert(globalHistory < globalPredictorSize && - local_history_idx < localPredictorSize); + local_history_idx < localHistoryTableSize && + local_predictor_idx < localPredictorSize); // Commented code is for doing speculative update of counters and // all histories. @@ -232,7 +235,7 @@ TournamentBP::update(Addr &branch_addr, bool taken, void *bp_history) // Get the local predictor's current prediction local_history_idx = calcLocHistIdx(branch_addr); local_predictor_hist = localHistoryTable[local_history_idx]; - local_predictor_idx = local_predictor_hist & localHistoryMask; + local_predictor_idx = local_predictor_hist & localPredictorMask; // Update the choice predictor to tell it which one was correct if // there was a prediction. @@ -254,6 +257,7 @@ TournamentBP::update(Addr &branch_addr, bool taken, void *bp_history) } assert(globalHistory < globalPredictorSize && + local_history_idx < localHistoryTableSize && local_predictor_idx < localPredictorSize); // Update the counters and local history with the proper diff --git a/cpu/o3/tournament_pred.hh b/cpu/o3/tournament_pred.hh index 6d77999cc..dc0cc55dc 100644 --- a/cpu/o3/tournament_pred.hh +++ b/cpu/o3/tournament_pred.hh @@ -158,6 +158,9 @@ class TournamentBP /** Size of the local predictor. */ unsigned localPredictorSize; + /** Mask to get the proper index bits into the predictor. */ + unsigned localPredictorMask; + /** Number of bits of the local predictor's counters. */ unsigned localCtrBits; diff --git a/cpu/ozone/cpu.hh b/cpu/ozone/cpu.hh index c272528b1..345e526ef 100644 --- a/cpu/ozone/cpu.hh +++ b/cpu/ozone/cpu.hh @@ -300,8 +300,6 @@ class OzoneCPU : public BaseCPU Status _status; public: - bool checkInterrupts; - void post_interrupt(int int_num, int index); void zero_fill_64(Addr addr) { diff --git a/cpu/ozone/cpu_builder.cc b/cpu/ozone/cpu_builder.cc index 1ab7a4c29..9df5962c8 100644 --- a/cpu/ozone/cpu_builder.cc +++ b/cpu/ozone/cpu_builder.cc @@ -84,6 +84,7 @@ Param max_insts_any_thread; Param max_insts_all_threads; Param max_loads_any_thread; Param max_loads_all_threads; +Param progress_interval; SimObjectParam icache; SimObjectParam dcache; @@ -212,6 +213,7 @@ BEGIN_INIT_SIM_OBJECT_PARAMS(DerivOzoneCPU) "Terminate when all threads have reached this load" "count", 0), + INIT_PARAM_DFLT(progress_interval, "Progress interval", 0), INIT_PARAM_DFLT(icache, "L1 instruction cache", NULL), INIT_PARAM_DFLT(dcache, "L1 data cache", NULL), @@ -355,6 +357,7 @@ CREATE_SIM_OBJECT(DerivOzoneCPU) params->max_insts_all_threads = max_insts_all_threads; params->max_loads_any_thread = max_loads_any_thread; params->max_loads_all_threads = max_loads_all_threads; + params->progress_interval = progress_interval; // // Caches diff --git a/cpu/ozone/cpu_impl.hh b/cpu/ozone/cpu_impl.hh index 4f41f220a..050bdb9a3 100644 --- a/cpu/ozone/cpu_impl.hh +++ b/cpu/ozone/cpu_impl.hh @@ -249,6 +249,9 @@ OzoneCPU::takeOverFrom(BaseCPU *oldCPU) { BaseCPU::takeOverFrom(oldCPU); + thread.trapPending = false; + thread.inSyscall = false; + backEnd->takeOverFrom(); frontEnd->takeOverFrom(); assert(!tickEvent.scheduled()); @@ -288,6 +291,8 @@ OzoneCPU::activateContext(int thread_num, int delay) scheduleTickEvent(delay); _status = Running; thread._status = ExecContext::Active; + if (thread.quiesceEvent && thread.quiesceEvent->scheduled()) + thread.quiesceEvent->deschedule(); frontEnd->wakeFromQuiesce(); } @@ -395,11 +400,17 @@ void OzoneCPU::serialize(std::ostream &os) { BaseCPU::serialize(os); - SERIALIZE_ENUM(_status); - nameOut(os, csprintf("%s.xc", name())); - ozoneXC.serialize(os); nameOut(os, csprintf("%s.tickEvent", name())); tickEvent.serialize(os); + + // Use SimpleThread's ability to checkpoint to make it easier to + // write out the registers. Also make this static so it doesn't + // get instantiated multiple times (causes a panic in statistics). + static CPUExecContext temp; + + nameOut(os, csprintf("%s.xc.0", name())); + temp.copyXC(thread.getXCProxy()); + temp.serialize(os); } template @@ -407,9 +418,16 @@ void OzoneCPU::unserialize(Checkpoint *cp, const std::string §ion) { BaseCPU::unserialize(cp, section); - UNSERIALIZE_ENUM(_status); - ozoneXC.unserialize(cp, csprintf("%s.xc", section)); tickEvent.unserialize(cp, csprintf("%s.tickEvent", section)); + + // Use SimpleThread's ability to checkpoint to make it easier to + // read in the registers. Also make this static so it doesn't + // get instantiated multiple times (causes a panic in statistics). + static CPUExecContext temp; + + temp.copyXC(thread.getXCProxy()); + temp.unserialize(cp, csprintf("%s.xc.0", section)); + thread.getXCProxy()->copyArchRegs(temp.getProxy()); } template diff --git a/cpu/ozone/front_end_impl.hh b/cpu/ozone/front_end_impl.hh index ffbcf3340..ca9948b7d 100644 --- a/cpu/ozone/front_end_impl.hh +++ b/cpu/ozone/front_end_impl.hh @@ -353,7 +353,7 @@ FrontEnd::tick() #if FULL_SYSTEM if (inst->isQuiesce()) { - warn("%lli: Quiesce instruction encountered, halting fetch!", curTick); +// warn("%lli: Quiesce instruction encountered, halting fetch!", curTick); status = QuiescePending; break; } diff --git a/cpu/ozone/lw_back_end_impl.hh b/cpu/ozone/lw_back_end_impl.hh index 18b2e8f47..9e1cd28cf 100644 --- a/cpu/ozone/lw_back_end_impl.hh +++ b/cpu/ozone/lw_back_end_impl.hh @@ -1499,7 +1499,6 @@ template void LWBackEnd::takeOverFrom(ExecContext *old_xc) { - switchedOut = false; xcSquash = false; trapSquash = false; diff --git a/cpu/simple/cpu.cc b/cpu/simple/cpu.cc index c03945ffa..0a4b3c3e4 100644 --- a/cpu/simple/cpu.cc +++ b/cpu/simple/cpu.cc @@ -304,7 +304,7 @@ SimpleCPU::serialize(ostream &os) BaseCPU::serialize(os); SERIALIZE_ENUM(_status); SERIALIZE_SCALAR(inst); - nameOut(os, csprintf("%s.xc", name())); + nameOut(os, csprintf("%s.xc.0", name())); cpuXC->serialize(os); nameOut(os, csprintf("%s.tickEvent", name())); tickEvent.serialize(os); @@ -318,7 +318,7 @@ SimpleCPU::unserialize(Checkpoint *cp, const string §ion) BaseCPU::unserialize(cp, section); UNSERIALIZE_ENUM(_status); UNSERIALIZE_SCALAR(inst); - cpuXC->unserialize(cp, csprintf("%s.xc", section)); + cpuXC->unserialize(cp, csprintf("%s.xc.0", section)); tickEvent.unserialize(cp, csprintf("%s.tickEvent", section)); cacheCompletionEvent .unserialize(cp, csprintf("%s.cacheCompletionEvent", section)); @@ -863,6 +863,7 @@ BEGIN_DECLARE_SIM_OBJECT_PARAMS(SimpleCPU) Param max_insts_all_threads; Param max_loads_any_thread; Param max_loads_all_threads; + Param progress_interval; #if FULL_SYSTEM SimObjectParam itb; @@ -896,6 +897,7 @@ BEGIN_INIT_SIM_OBJECT_PARAMS(SimpleCPU) "terminate when any thread reaches this load count"), INIT_PARAM(max_loads_all_threads, "terminate when all threads have reached this load count"), + INIT_PARAM_DFLT(progress_interval, "CPU Progress interval", 0), #if FULL_SYSTEM INIT_PARAM(itb, "Instruction TLB"), @@ -936,6 +938,7 @@ CREATE_SIM_OBJECT(SimpleCPU) params->dcache_interface = (dcache) ? dcache->getInterface() : NULL; params->width = width; + params->progress_interval = progress_interval; #if FULL_SYSTEM params->itb = itb; params->dtb = dtb; diff --git a/python/m5/objects/BaseCPU.py b/python/m5/objects/BaseCPU.py index a90203729..29fb6ebce 100644 --- a/python/m5/objects/BaseCPU.py +++ b/python/m5/objects/BaseCPU.py @@ -22,6 +22,7 @@ class BaseCPU(SimObject): "terminate when all threads have reached this load count") max_loads_any_thread = Param.Counter(0, "terminate when any thread reaches this load count") + progress_interval = Param.Tick(0, "interval to print out the progress message") defer_registration = Param.Bool(False, "defer registration with system (for sampling)") diff --git a/python/m5/objects/Root.py b/python/m5/objects/Root.py index 23b13fc67..0973d6ae5 100644 --- a/python/m5/objects/Root.py +++ b/python/m5/objects/Root.py @@ -1,6 +1,7 @@ from m5 import * from HierParams import HierParams from Serialize import Serialize +from Serialize import Statreset from Statistics import Statistics from Trace import Trace from ExeTrace import ExecutionTrace @@ -23,3 +24,4 @@ class Root(SimObject): trace = Trace() exetrace = ExecutionTrace() serialize = Serialize() + statsreset = Statreset() diff --git a/sim/serialize.cc b/sim/serialize.cc index c4ef124bb..1827a617e 100644 --- a/sim/serialize.cc +++ b/sim/serialize.cc @@ -49,6 +49,9 @@ #include "sim/sim_exit.hh" #include "sim/sim_object.hh" +// For stat reset hack +#include "sim/stat_control.hh" + using namespace std; int Serializable::ckptMaxCount = 0; @@ -482,3 +485,36 @@ Checkpoint::sectionExists(const std::string §ion) { return db->sectionExists(section); } + +/** Hacked stat reset event */ + +class StatresetParamContext : public ParamContext +{ + public: + StatresetParamContext(const string §ion); + ~StatresetParamContext(); + void startup(); +}; + +StatresetParamContext statParams("statsreset"); + +Param reset_cycle(&statParams, "reset_cycle", + "Cycle to reset stats on", 0); + +StatresetParamContext::StatresetParamContext(const string §ion) + : ParamContext(section) +{ } + +StatresetParamContext::~StatresetParamContext() +{ +} + +void +StatresetParamContext::startup() +{ + if (reset_cycle > 0) { + Stats::SetupEvent(Stats::Reset, curTick + reset_cycle, 0); + cprintf("Stats reset event scheduled for %lli\n", + curTick + reset_cycle); + } +} diff --git a/sim/stat_control.cc b/sim/stat_control.cc index 85c405b7f..e4394cfa3 100644 --- a/sim/stat_control.cc +++ b/sim/stat_control.cc @@ -183,8 +183,10 @@ StatEvent::process() if (flags & Stats::Dump) DumpNow(); - if (flags & Stats::Reset) + if (flags & Stats::Reset) { + cprintf("Resetting stats!\n"); reset(); + } if (repeat) schedule(curTick + repeat); From de321175f2300cb40e02e5f6ef2692c0ac3b8ae9 Mon Sep 17 00:00:00 2001 From: Kevin Lim Date: Fri, 11 Aug 2006 17:48:41 -0400 Subject: [PATCH 07/20] Add in a bunch more stuff. configs/boot/micro_memlat.rcS: Update these scripts so they work (not sure why they broke) configs/boot/micro_tlblat.rcS: Update this script to use a different test. --HG-- extra : convert_revision : 6e8692540a9fac6ae8f2d9975c70d4135354b849 --- configs/boot/bonnie.rcS | 13 + configs/boot/halt.sh | 1 + configs/boot/ls.rcS | 18 ++ configs/boot/micro_memlat.rcS | 2 +- configs/boot/micro_tlblat.rcS | 2 +- configs/boot/micro_tlblat2.rcS | 3 + configs/boot/micro_tlblat3.rcS | 3 + util/batch/batch.py | 249 +++++++++++++++ util/batch/job.py | 246 +++++++++++++++ util/batch/jobfile.py | 539 +++++++++++++++++++++++++++++++++ util/batch/send.py | 306 +++++++++++++++++++ 11 files changed, 1380 insertions(+), 2 deletions(-) create mode 100644 configs/boot/bonnie.rcS create mode 100644 configs/boot/halt.sh create mode 100644 configs/boot/ls.rcS create mode 100644 configs/boot/micro_tlblat2.rcS create mode 100644 configs/boot/micro_tlblat3.rcS create mode 100644 util/batch/batch.py create mode 100755 util/batch/job.py create mode 100644 util/batch/jobfile.py create mode 100755 util/batch/send.py diff --git a/configs/boot/bonnie.rcS b/configs/boot/bonnie.rcS new file mode 100644 index 000000000..65b2fd6c9 --- /dev/null +++ b/configs/boot/bonnie.rcS @@ -0,0 +1,13 @@ +#!/bin/sh +# +# /etc/init.d/rcS +# + +echo -n "Mounting empty disk..." +mkdir /tmp-space +/bin/mount /dev/hdb1 /tmp-space +chmod a+rwx /tmp-space +echo "done." + +/bin/bonnie++ -u 99 -s 700 -r 0 -n 0 -f -F -d /tmp-space +m5 exit diff --git a/configs/boot/halt.sh b/configs/boot/halt.sh new file mode 100644 index 000000000..b1332ebab --- /dev/null +++ b/configs/boot/halt.sh @@ -0,0 +1 @@ +m5 exit diff --git a/configs/boot/ls.rcS b/configs/boot/ls.rcS new file mode 100644 index 000000000..4cfe38d2b --- /dev/null +++ b/configs/boot/ls.rcS @@ -0,0 +1,18 @@ +ls +ls +ls +ls +cd bin +ls +ls +ls +ls +ls +ls +ls +ls +cd ../benchmarks +ls +ls +ls +ls diff --git a/configs/boot/micro_memlat.rcS b/configs/boot/micro_memlat.rcS index 50ee8efb3..86ec01132 100644 --- a/configs/boot/micro_memlat.rcS +++ b/configs/boot/micro_memlat.rcS @@ -1,3 +1,3 @@ -/benchmarks/micros/lmbench/bin/alphaev6-linux-gnu/lat_mem_rd 512 64 +/benchmarks/micros/lmbench/bin/alphaev6-linux-gnu/lat_mem_rd 450 64 m5 exit diff --git a/configs/boot/micro_tlblat.rcS b/configs/boot/micro_tlblat.rcS index ab05fd9ff..6f713e580 100644 --- a/configs/boot/micro_tlblat.rcS +++ b/configs/boot/micro_tlblat.rcS @@ -1,3 +1,3 @@ -/benchmarks/micros/lmbench/bin/alphaev6-linux-gnu/lat_mem_rd_2MB 2 8192 +/benchmarks/micros/lmbench/bin/alphaev6-linux-gnu/lat_tlb m5 exit diff --git a/configs/boot/micro_tlblat2.rcS b/configs/boot/micro_tlblat2.rcS new file mode 100644 index 000000000..ab05fd9ff --- /dev/null +++ b/configs/boot/micro_tlblat2.rcS @@ -0,0 +1,3 @@ +/benchmarks/micros/lmbench/bin/alphaev6-linux-gnu/lat_mem_rd_2MB 2 8192 +m5 exit + diff --git a/configs/boot/micro_tlblat3.rcS b/configs/boot/micro_tlblat3.rcS new file mode 100644 index 000000000..fd5fd53c1 --- /dev/null +++ b/configs/boot/micro_tlblat3.rcS @@ -0,0 +1,3 @@ +/benchmarks/micros/lmbench/bin/alphaev6-linux-gnu/lat_mem_rd_2MB 20 8192 +m5 exit + diff --git a/util/batch/batch.py b/util/batch/batch.py new file mode 100644 index 000000000..91d354e97 --- /dev/null +++ b/util/batch/batch.py @@ -0,0 +1,249 @@ +# Copyright (c) 2006 The Regents of The University of Michigan +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer; +# redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution; +# neither the name of the copyright holders nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Kevin Lim + +import os, popen2, re, sys + +class MyPOpen(object): + def __init__(self, cmd, input = None, output = None, bufsize = -1): + self.status = -1 + + if input is None: + p2c_read, p2c_write = os.pipe() + self.tochild = os.fdopen(p2c_write, 'w', bufsize) + else: + p2c_write = None + if isinstance(input, file): + p2c_read = input.fileno() + elif isinstance(input, str): + input = file(input, 'r') + p2c_read = input.fileno() + elif isinstance(input, int): + p2c_read = input + else: + raise AttributeError + + if output is None: + c2p_read, c2p_write = os.pipe() + self.fromchild = os.fdopen(c2p_read, 'r', bufsize) + else: + c2p_read = None + if isinstance(output, file): + c2p_write = output.fileno() + elif isinstance(output, str): + output = file(output, 'w') + c2p_write = output.fileno() + elif isinstance(output, int): + c2p_write = output + else: + raise AttributeError + + self.pid = os.fork() + if self.pid == 0: + os.dup2(p2c_read, sys.stdin.fileno()) + os.dup2(c2p_write, sys.stdout.fileno()) + os.dup2(c2p_write, sys.stderr.fileno()) + try: + os.execvp(cmd[0], cmd) + finally: + os._exit(1) + + os.close(p2c_read) + os.close(c2p_write) + + def poll(self): + if self.status < 0: + pid, status = os.waitpid(self.pid, os.WNOHANG) + if pid == self.pid: + self.status = status + return self.status + + def wait(self): + if self.status < 0: + pid, status = os.waitpid(self.pid, 0) + if pid == self.pid: + self.status = status + return self.status + + +class oarsub: + def __init__(self): + self.walltime = None + self.queue = None + self.properties = None + + # OAR 2.0 parameters only! + self.name = None + self.afterok = None + self.notify = None + self.stderr = None + self.stdout = None + + + self.oarhost = None + self.oarsub = 'oarsub' + + self.jobid = re.compile('IdJob = (\S+)') + #self.outfile = open("jobnames.dat", "a+") + + def build(self, script, args = []): + self.cmd = [ self.oarsub ] + + print "args:", args + print "script:", script + if self.properties: + self.cmd.append('-p"%s"' % self.properties ) + + if self.queue: + self.cmd.append('-q "%s"' % self.queue) + + if self.walltime: + self.cmd.append('-l walltime=%s' % self.walltime) + + if script[0] != "/": + self.script = os.getcwd() + else: + self.script = script + + self.cmd.extend(args) + self.cmd.append(self.script) + #cmd = [ 'ssh', '-x', self.oarhost, '"cd %s; %s"' % (os.getcwd(), self.command) ] + self.command = ' '.join(self.cmd) + + print "command: [%s]" % self.command + + def do(self): + oar = MyPOpen(self.cmd) + self.result = oar.fromchild.read() + ec = oar.wait() + + if ec != 0 and self.oarhost: + pstdin, pstdout = os.popen4(self.command) + self.result = pstdout.read() + + jobid = self.jobid.match(self.result) + if jobid == None: + print "Couldn't get jobid from [%s]" % self.result + sys.exit(1) + else: + #self.outfile.write("%d %s\n" %(int(jobid.group(1)), self.name)); + #self.outfile.flush() + self.result = jobid.group(1) + + return 0 + +class qsub: + def __init__(self): + self.afterok = None + self.hold = False + self.join = False + self.keep_stdout = False + self.keep_stderr = False + self.node_type = None + self.mail_abort = False + self.mail_begin = False + self.mail_end = False + self.name = None + self.stdout = None + self.priority = None + self.queue = None + self.pbshost = None + self.qsub = 'qsub' + self.env = {} + + def build(self, script, args = []): + self.cmd = [ self.qsub ] + + if self.env: + arg = '-v' + arg += ','.join([ '%s=%s' % i for i in self.env.iteritems() ]) + self.cmd.append(arg) + + if self.hold: + self.cmd.append('-h') + + if self.stdout: + self.cmd.append('-olocalhost:' + self.stdout) + + if self.keep_stdout and self.keep_stderr: + self.cmd.append('-koe') + elif self.keep_stdout: + self.cmd.append('-ko') + elif self.keep_stderr: + self.cmd.append('-ke') + else: + self.cmd.append('-kn') + + if self.join: + self.cmd.append('-joe') + + if self.node_type: + self.cmd.append('-lnodes=' + self.node_type) + + if self.mail_abort or self.mail_begin or self.mail_end: + flags = '' + if self.mail_abort: + flags.append('a') + if self.mail_begin: + flags.append('b') + if self.mail_end: + flags.append('e') + if len(flags): + self.cmd.append('-m ' + flags) + else: + self.cmd.append('-mn') + + if self.name: + self.cmd.append("-N%s" % self.name) + + if self.priority: + self.cmd.append('-p' + self.priority) + + if self.queue: + self.cmd.append('-q' + self.queue) + + if self.afterok: + self.cmd.append('-Wdepend=afterok:%s' % self.afterok) + + self.cmd.extend(args) + self.script = script + self.command = ' '.join(self.cmd + [ self.script ]) + + def do(self): + pbs = MyPOpen(self.cmd + [ self.script ]) + self.result = pbs.fromchild.read() + ec = pbs.wait() + + if ec != 0 and self.pbshost: + cmd = ' '.join(self.cmd + [ '-' ]) + cmd = [ 'ssh', '-x', self.pbshost, cmd ] + self.command = ' '.join(cmd) + ssh = MyPOpen(cmd, input = self.script) + self.result = ssh.fromchild.read() + ec = ssh.wait() + + return ec diff --git a/util/batch/job.py b/util/batch/job.py new file mode 100755 index 000000000..9d7ecca8c --- /dev/null +++ b/util/batch/job.py @@ -0,0 +1,246 @@ +#!/usr/bin/env python +# Copyright (c) 2006 The Regents of The University of Michigan +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer; +# redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution; +# neither the name of the copyright holders nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Kevin Lim + +import os, os.path, shutil, signal, socket, sys +from os import environ as env +from os.path import join as joinpath, expanduser + +def date(): + import time + return time.strftime('%a %b %e %H:%M:%S %Z %Y', time.localtime()) + +def cleandir(dir): + for root, dirs, files in os.walk(dir, False): + for name in files: + os.remove(joinpath(root, name)) + for name in dirs: + os.rmdir(joinpath(root, name)) + +class rsync: + def __init__(self): + self.sudo = False + self.rsync = 'rsync' + self.compress = False + self.archive = True + self.delete = False + self.options = '' + + def do(self, src, dst): + args = [] + if self.sudo: + args.append('sudo') + + args.append(self.rsync) + if (self.archive): + args.append('-a') + if (self.compress): + args.append('-z') + if (self.delete): + args.append('--delete') + if len(self.options): + args.append(self.options) + args.append(src) + args.append(dst) + + return os.spawnvp(os.P_WAIT, args[0], args) + +class JobDir(object): + def __init__(self, dir): + self.dir = dir + + def file(self, filename): + return joinpath(self.dir, filename) + + def create(self): + if os.path.exists(self.dir): + if not os.path.isdir(self.dir): + sys.exit('%s is not a directory. Cannot build job' % self.dir) + else: + os.mkdir(self.dir) + + def exists(self): + return os.path.isdir(self.dir) + + def clean(self): + cleandir(self.dir) + + def hasfile(self, filename): + return os.path.isfile(self.file(filename)) + + def echofile(self, filename, string): + filename = self.file(filename) + try: + f = file(filename, 'w') + print >>f, string + f.flush() + f.close() + except IOError,e: + sys.exit(e) + + def rmfile(self, filename): + filename = self.file(filename) + if os.path.isfile(filename): + os.unlink(filename) + + def readval(self, filename): + filename = self.file(filename) + f = file(filename, 'r') + value = f.readline().strip() + f.close() + return value + + def setstatus(self, string): + filename = self.file('.status') + try: + f = file(filename, 'a') + print >>f, string + f.flush() + f.close() + except IOError,e: + sys.exit(e) + + def getstatus(self): + filename = self.file('.status') + try: + f = file(filename, 'r') + except IOError, e: + return 'none' + + # fast forward to the end + for line in f: pass + + # the first word on the last line is the status + return line.split(' ')[0] + + def __str__(self): + return self.dir + +if __name__ == '__main__': + import platform + binaries = { 'i686' : 'm5.i386', + 'x86_64' : 'm5.amd64' } + binary = binaries[platform.machine()] + + cwd = os.getcwd() + rootdir = env.setdefault('ROOTDIR', os.path.dirname(cwd)) + oar_jobid = int(env['OAR_JOBID']) + oar_jobname = os.path.basename(cwd) + #pbs_jobname = env['PBS_JOBNAME'] + basedir = joinpath(rootdir, 'Base') + jobname = env.setdefault('JOBNAME', oar_jobname) + jobfile = env.setdefault('JOBFILE', joinpath(rootdir, 'Test.py')) + outdir = env.setdefault('OUTPUT_DIR', cwd) + env['POOLJOB'] = 'True' + + if os.path.isdir("/work"): + workbase = "/work" + else: + workbase = "/tmp/" + + workdir = joinpath(workbase, '%s.%s' % (env['USER'], oar_jobid)) + host = socket.gethostname() + + os.umask(0022) + + jobdir = JobDir(outdir) + + started = date() + jobdir.echofile('.running', started) + jobdir.rmfile('.queued') + jobdir.echofile('.host', host) + + jobdir.setstatus('running on %s on %s' % (host, started)) + + if os.path.isdir(workdir): + cleandir(workdir) + else: + os.mkdir(workdir) + + if False and os.path.isdir('/z/dist'): + sync = rsync() + sync.delete = True + sync.sudo = True + sync.do('poolfs::dist/m5/', '/z/dist/m5/') + + try: + os.chdir(workdir) + except OSError,e: + sys.exit(e) + + os.symlink(jobdir.file('output'), 'status.out') + + args = [ joinpath(basedir, binary), joinpath(basedir, 'run.py') ] + if not len(args): + sys.exit("no arguments") + + print 'starting job... %s' % started + print ' '.join(args) + print + sys.stdout.flush() + + childpid = os.fork() + if not childpid: + # Execute command + sys.stdin.close() + fd = os.open(jobdir.file("output"), + os.O_WRONLY | os.O_CREAT | os.O_TRUNC) + os.dup2(fd, sys.stdout.fileno()) + os.dup2(fd, sys.stderr.fileno()) + os.execvp(args[0], args) + + def handler(signum, frame): + if childpid != 0: + os.kill(childpid, signum) + + signal.signal(signal.SIGHUP, handler) + signal.signal(signal.SIGINT, handler) + signal.signal(signal.SIGQUIT, handler) + signal.signal(signal.SIGTERM, handler) + signal.signal(signal.SIGCONT, handler) + signal.signal(signal.SIGUSR1, handler) + signal.signal(signal.SIGUSR2, handler) + + done = 0 + while not done: + try: + thepid,ec = os.waitpid(childpid, 0) + if ec: + print 'Exit code ', ec + status = 'failure' + else: + status = 'success' + done = 1 + except OSError: + pass + + complete = date() + print '\njob complete... %s' % complete + jobdir.echofile('.%s' % status, complete) + jobdir.rmfile('.running') + jobdir.setstatus('%s on %s' % (status, complete)) diff --git a/util/batch/jobfile.py b/util/batch/jobfile.py new file mode 100644 index 000000000..b78d7f3e1 --- /dev/null +++ b/util/batch/jobfile.py @@ -0,0 +1,539 @@ +# Copyright (c) 2006 The Regents of The University of Michigan +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer; +# redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution; +# neither the name of the copyright holders nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Kevin Lim + +import sys + +class ternary(object): + def __new__(cls, *args): + if len(args) > 1: + raise TypeError, \ + '%s() takes at most 1 argument (%d given)' % \ + (cls.__name__, len(args)) + + if args: + if not isinstance(args[0], (bool, ternary)): + raise TypeError, \ + '%s() argument must be True, False, or Any' % \ + cls.__name__ + return args[0] + return super(ternary, cls).__new__(cls) + + def __bool__(self): + return True + + def __neg__(self): + return self + + def __eq__(self, other): + return True + + def __ne__(self, other): + return False + + def __str__(self): + return 'Any' + + def __repr__(self): + return 'Any' + +Any = ternary() + +class Flags(dict): + def __init__(self, *args, **kwargs): + super(Flags, self).__init__() + self.update(*args, **kwargs) + + def __getattr__(self, attr): + return self[attr] + + def __setattr__(self, attr, value): + self[attr] = value + + def __setitem__(self, item, value): + return super(Flags, self).__setitem__(item, ternary(value)) + + def __getitem__(self, item): + if item not in self: + return False + return super(Flags, self).__getitem__(item) + + def update(self, *args, **kwargs): + for arg in args: + if isinstance(arg, Flags): + super(Flags, self).update(arg) + elif isinstance(arg, dict): + for key,val in kwargs.iteritems(): + self[key] = val + else: + raise AttributeError, \ + 'flags not of type %s or %s, but %s' % \ + (Flags, dict, type(arg)) + + for key,val in kwargs.iteritems(): + self[key] = val + + def match(self, *args, **kwargs): + match = Flags(*args, **kwargs) + + for key,value in match.iteritems(): + if self[key] != value: + return False + + return True + +def crossproduct(items): + if not isinstance(items, (list, tuple)): + raise AttributeError, 'crossproduct works only on sequences' + + if not items: + yield None + return + + current = items[0] + remainder = items[1:] + + if not hasattr(current, '__iter__'): + current = [ current ] + + for item in current: + for rem in crossproduct(remainder): + data = [ item ] + if rem: + data += rem + yield data + +def flatten(items): + if not isinstance(items, (list, tuple)): + yield items + return + + for item in items: + for flat in flatten(item): + yield flat + +class Data(object): + def __init__(self, name, desc, **kwargs): + self.name = name + self.desc = desc + self.system = None + self.flags = Flags() + self.env = {} + for k,v in kwargs.iteritems(): + setattr(self, k, v) + + def update(self, obj): + if not isinstance(obj, Data): + raise AttributeError, "can only update from Data object" + + self.env.update(obj.env) + self.flags.update(obj.flags) + if obj.system: + if self.system and self.system != obj.system: + raise AttributeError, \ + "conflicting values for system: '%s'/'%s'" % \ + (self.system, obj.system) + self.system = obj.system + + def printinfo(self): + if self.name: + print 'name: %s' % self.name + if self.desc: + print 'desc: %s' % self.desc + if self.system: + print 'system: %s' % self.system + + def printverbose(self): + print 'flags:' + keys = self.flags.keys() + keys.sort() + for key in keys: + print ' %s = %s' % (key, self.flags[key]) + print 'env:' + keys = self.env.keys() + keys.sort() + for key in keys: + print ' %s = %s' % (key, self.env[key]) + print + + def __str__(self): + return self.name + +class Job(Data): + def __init__(self, options): + super(Job, self).__init__('', '') + self.setoptions(options) + + self.checkpoint = False + opts = [] + for opt in options: + cpt = opt.group.checkpoint + if not cpt: + self.checkpoint = True + continue + if isinstance(cpt, Option): + opt = cpt.clone(suboptions=False) + else: + opt = opt.clone(suboptions=False) + + opts.append(opt) + + if not opts: + self.checkpoint = False + + if self.checkpoint: + self.checkpoint = Job(opts) + + def clone(self): + return Job(self.options) + + def __getattribute__(self, attr): + if attr == 'name': + names = [ ] + for opt in self.options: + if opt.name: + names.append(opt.name) + return ':'.join(names) + + if attr == 'desc': + descs = [ ] + for opt in self.options: + if opt.desc: + descs.append(opt.desc) + return ', '.join(descs) + + return super(Job, self).__getattribute__(attr) + + def setoptions(self, options): + config = options[0].config + for opt in options: + if opt.config != config: + raise AttributeError, \ + "All options are not from the same Configuration" + + self.config = config + self.groups = [ opt.group for opt in options ] + self.options = options + + self.update(self.config) + for group in self.groups: + self.update(group) + + for option in self.options: + self.update(option) + if option._suboption: + self.update(option._suboption) + + def printinfo(self): + super(Job, self).printinfo() + if self.checkpoint: + print 'checkpoint: %s' % self.checkpoint.name + print 'config: %s' % self.config.name + print 'groups: %s' % [ g.name for g in self.groups ] + print 'options: %s' % [ o.name for o in self.options ] + super(Job, self).printverbose() + +class SubOption(Data): + def __init__(self, name, desc, **kwargs): + super(SubOption, self).__init__(name, desc, **kwargs) + self.number = None + +class Option(Data): + def __init__(self, name, desc, **kwargs): + super(Option, self).__init__(name, desc, **kwargs) + self._suboptions = [] + self._suboption = None + self.number = None + + def __getattribute__(self, attr): + if attr == 'name': + name = self.__dict__[attr] + if self._suboption is not None: + name = '%s:%s' % (name, self._suboption.name) + return name + + if attr == 'desc': + desc = [ self.__dict__[attr] ] + if self._suboption is not None and self._suboption.desc: + desc.append(self._suboption.desc) + return ', '.join(desc) + + + return super(Option, self).__getattribute__(attr) + + def suboption(self, name, desc, **kwargs): + subo = SubOption(name, desc, **kwargs) + subo.config = self.config + subo.group = self.group + subo.option = self + subo.number = len(self._suboptions) + self._suboptions.append(subo) + return subo + + def clone(self, suboptions=True): + option = Option(self.__dict__['name'], self.__dict__['desc']) + option.update(self) + option.group = self.group + option.config = self.config + option.number = self.number + if suboptions: + option._suboptions.extend(self._suboptions) + option._suboption = self._suboption + return option + + def subopts(self): + if not self._suboptions: + return [ self ] + + subopts = [] + for subo in self._suboptions: + option = self.clone() + option._suboption = subo + subopts.append(option) + + return subopts + + def printinfo(self): + super(Option, self).printinfo() + print 'config: %s' % self.config.name + super(Option, self).printverbose() + +class Group(Data): + def __init__(self, name, desc, **kwargs): + super(Group, self).__init__(name, desc, **kwargs) + self._options = [] + self.checkpoint = False + self.number = None + + def option(self, name, desc, **kwargs): + opt = Option(name, desc, **kwargs) + opt.config = self.config + opt.group = self + opt.number = len(self._options) + self._options.append(opt) + return opt + + def options(self): + return self._options + + def subopts(self): + subopts = [] + for opt in self._options: + for subo in opt.subopts(): + subopts.append(subo) + return subopts + + def printinfo(self): + super(Group, self).printinfo() + print 'config: %s' % self.config.name + print 'options: %s' % [ o.name for o in self._options ] + super(Group, self).printverbose() + +class Configuration(Data): + def __init__(self, name, desc, **kwargs): + super(Configuration, self).__init__(name, desc, **kwargs) + self._groups = [] + self._posfilters = [] + self._negfilters = [] + + def group(self, name, desc, **kwargs): + grp = Group(name, desc, **kwargs) + grp.config = self + grp.number = len(self._groups) + self._groups.append(grp) + return grp + + def groups(self, flags=Flags(), sign=True): + if not flags: + return self._groups + + return [ grp for grp in self._groups if sign ^ grp.flags.match(flags) ] + + def checkchildren(self, kids): + for kid in kids: + if kid.config != self: + raise AttributeError, "child from the wrong configuration" + + def sortgroups(self, groups): + groups = [ (grp.number, grp) for grp in groups ] + groups.sort() + return [ grp[1] for grp in groups ] + + def options(self, groups = None, checkpoint = False): + if groups is None: + groups = self._groups + self.checkchildren(groups) + groups = self.sortgroups(groups) + if checkpoint: + groups = [ grp for grp in groups if grp.checkpoint ] + optgroups = [ g.options() for g in groups ] + else: + optgroups = [ g.subopts() for g in groups ] + for options in crossproduct(optgroups): + for opt in options: + cpt = opt.group.checkpoint + if not isinstance(cpt, bool) and cpt != opt: + if checkpoint: + break + else: + yield options + else: + if checkpoint: + yield options + + def addfilter(self, filt, pos=True): + import re + filt = re.compile(filt) + if pos: + self._posfilters.append(filt) + else: + self._negfilters.append(filt) + + def jobfilter(self, job): + for filt in self._negfilters: + if filt.match(job.name): + return False + + if not self._posfilters: + return True + + for filt in self._posfilters: + if filt.match(job.name): + return True + + return False + + def checkpoints(self, groups = None): + for options in self.options(groups, True): + job = Job(options) + if self.jobfilter(job): + yield job + + def jobs(self, groups = None): + for options in self.options(groups, False): + job = Job(options) + if self.jobfilter(job): + yield job + + def alljobs(self, groups = None): + for options in self.options(groups, True): + yield Job(options) + for options in self.options(groups, False): + yield Job(options) + + def find(self, jobname): + for job in self.alljobs(): + if job.name == jobname: + return job + else: + raise AttributeError, "job '%s' not found" % jobname + + def job(self, options): + self.checkchildren(options) + options = [ (opt.group.number, opt) for opt in options ] + options.sort() + options = [ opt[1] for opt in options ] + job = Job(options) + return job + + def printinfo(self): + super(Configuration, self).printinfo() + print 'groups: %s' % [ g.name for g in self._grouips ] + super(Configuration, self).printverbose() + +def JobFile(jobfile): + from os.path import expanduser, isfile, join as joinpath + filename = expanduser(jobfile) + + # Can't find filename in the current path, search sys.path + if not isfile(filename): + for path in sys.path: + testname = joinpath(path, filename) + if isfile(testname): + filename = testname + break + else: + raise AttributeError, \ + "Could not find file '%s'" % jobfile + + data = {} + execfile(filename, data) + if 'conf' not in data: + raise ImportError, 'cannot import name conf from %s' % jobfile + conf = data['conf'] + import jobfile + if not isinstance(conf, Configuration): + raise AttributeError, \ + 'conf in jobfile: %s (%s) is not type %s' % \ + (jobfile, type(conf), Configuration) + return conf + +if __name__ == '__main__': + from jobfile import * + import sys + + usage = 'Usage: %s [-b] [-c] [-v] ' % sys.argv[0] + + try: + import getopt + opts, args = getopt.getopt(sys.argv[1:], '-bcv') + except getopt.GetoptError: + sys.exit(usage) + + if len(args) != 1: + raise AttributeError, usage + + both = False + checkpoint = False + verbose = False + for opt,arg in opts: + if opt == '-b': + both = True + checkpoint = True + if opt == '-c': + checkpoint = True + if opt == '-v': + verbose = True + + jobfile = args[0] + conf = JobFile(jobfile) + + if both: + gen = conf.alljobs() + elif checkpoint: + gen = conf.checkpoints() + else: + gen = conf.jobs() + + for job in gen: + if not verbose: + cpt = '' + if job.checkpoint: + cpt = job.checkpoint.name + print job.name, cpt + else: + job.printinfo() diff --git a/util/batch/send.py b/util/batch/send.py new file mode 100755 index 000000000..e7bf1958f --- /dev/null +++ b/util/batch/send.py @@ -0,0 +1,306 @@ +#!/usr/bin/env python +# Copyright (c) 2006 The Regents of The University of Michigan +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer; +# redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution; +# neither the name of the copyright holders nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Authors: Kevin Lim + +import os, os.path, re, socket, sys +from os import environ as env, listdir +from os.path import basename, isdir, isfile, islink, join as joinpath, normpath +from filecmp import cmp as filecmp +from shutil import copy + +def nfspath(dir): + if dir.startswith('/.automount/'): + dir = '/n/%s' % dir[12:] + elif not dir.startswith('/n/'): + dir = '/n/%s%s' % (socket.gethostname().split('.')[0], dir) + return dir + +def syncdir(srcdir, destdir): + srcdir = normpath(srcdir) + destdir = normpath(destdir) + if not isdir(destdir): + sys.exit('destination directory "%s" does not exist' % destdir) + + for root, dirs, files in os.walk(srcdir): + root = normpath(root) + prefix = os.path.commonprefix([root, srcdir]) + root = root[len(prefix):] + if root.startswith('/'): + root = root[1:] + for rem in [ d for d in dirs if d.startswith('.') or d == 'SCCS']: + dirs.remove(rem) + + for entry in dirs: + newdir = joinpath(destdir, root, entry) + if not isdir(newdir): + os.mkdir(newdir) + print 'mkdir', newdir + + for i,d in enumerate(dirs): + if islink(joinpath(srcdir, root, d)): + dirs[i] = joinpath(d, '.') + + for entry in files: + dest = normpath(joinpath(destdir, root, entry)) + src = normpath(joinpath(srcdir, root, entry)) + if not isfile(dest) or not filecmp(src, dest): + print 'copy %s %s' % (dest, src) + copy(src, dest) + +progpath = nfspath(sys.path[0]) +progname = basename(sys.argv[0]) +usage = """\ +Usage: + %(progname)s [-c] [-e] [-f] [-j ] [-q queue] [-v] + -c clean directory if job can be run + -C submit the checkpointing runs + -d Make jobs be dependent on the completion of the checkpoint runs + -e only echo pbs command info, don't actually send the job + -f force the job to run regardless of state + -q submit job to the named queue + -j specify the jobfile (default is /Test.py) + -v be verbose + + %(progname)s [-j ] -l [-v] + -j specify the jobfile (default is /Test.py) + -l list job names, don't submit + -v be verbose (list job parameters) + + %(progname)s -h + -h display this help +""" % locals() + +try: + import getopt + opts, args = getopt.getopt(sys.argv[1:], '-Ccdefhj:lnq:Rt:v') +except getopt.GetoptError: + sys.exit(usage) + +depend = False +clean = False +onlyecho = False +exprs = [] +force = False +listonly = False +queue = '' +verbose = False +jfile = 'Test.py' +docpts = False +doruns = True +runflag = False +node_type = 'FAST' +update = True + +for opt,arg in opts: + if opt == '-C': + docpts = True + if opt == '-c': + clean = True + if opt == '-d': + depend = True + if opt == '-e': + onlyecho = True + if opt == '-f': + force = True + if opt == '-h': + print usage + sys.exit(0) + if opt == '-j': + jfile = arg + if opt == '-l': + listonly = True + if opt == '-n': + update = False + if opt == '-q': + queue = arg + if opt == '-R': + runflag = True + if opt == '-t': + node_type = arg + if opt == '-v': + verbose = True + +if docpts: + doruns = runflag + +for arg in args: + exprs.append(re.compile(arg)) + +import jobfile, batch +from job import JobDir, date + +conf = jobfile.JobFile(jfile) + +if update and not listonly and not onlyecho and isdir(conf.linkdir): + if verbose: + print 'Checking for outdated files in Link directory' + if not isdir(conf.basedir): + os.mkdir(conf.basedir) + syncdir(conf.linkdir, conf.basedir) + +jobnames = {} +joblist = [] + +if docpts and doruns: + gen = conf.alljobs() +elif docpts: + gen = conf.checkpoints() +elif doruns: + gen = conf.jobs() + +for job in gen: + if job.name in jobnames: + continue + + if exprs: + for expr in exprs: + if expr.match(job.name): + joblist.append(job) + break + else: + joblist.append(job) + +if listonly: + if verbose: + for job in joblist: + job.printinfo() + else: + for job in joblist: + print job.name + sys.exit(0) + +if not onlyecho: + newlist = [] + for job in joblist: + jobdir = JobDir(joinpath(conf.rootdir, job.name)) + if jobdir.exists(): + if not force: + status = jobdir.getstatus() + if status == 'queued': + continue + + if status == 'running': + continue + + if status == 'success': + continue + + if not clean: + sys.exit('job directory %s not clean!' % jobdir) + + jobdir.clean() + newlist.append(job) + joblist = newlist + +class NameHack(object): + def __init__(self, host='pbs.pool', port=24465): + self.host = host + self.port = port + self.socket = None + + def setname(self, jobid, jobname): + try: + jobid = int(jobid) + except ValueError: + jobid = int(jobid.strip().split('.')[0]) + + jobname = jobname.strip() + # since pbs can handle jobnames of 15 characters or less, + # don't use the raj hack. + if len(jobname) <= 15: + return + + if self.socket is None: + import socket + self.socket = socket.socket() + # Connect to pbs.pool and send the jobid/jobname pair to port + # 24465 (Raj didn't realize that there are only 64k ports and + # setup inetd to point to port 90001) + self.socket.connect((self.host, self.port)) + + self.socket.send("%s %s\n" % (jobid, jobname)) + +namehack = NameHack() + +rootdir = conf.rootdir +script = joinpath(rootdir, 'Base', 'job.py') + +for job in joblist: + jobdir = JobDir(joinpath(rootdir, job.name)) + if depend: + cptdir = JobDir(joinpath(rootdir, job.checkpoint.name)) + path = str(cptdir) + if not isdir(path) or not isfile(joinpath(path, '.success')): + continue + + cptjob = cptdir.readval('.batch_jobid') + + if not onlyecho: + jobdir.create() + os.chdir(str(jobdir)) + os.environ['PWD'] = str(jobdir) + + print 'Job name: %s' % job.name + print 'Job directory: %s' % jobdir + + + qsub = batch.oarsub() + qsub.oarhost = 'poolfs.eecs.umich.edu' + #qsub.stdout = jobdir.file('jobout') + qsub.name = job.name + qsub.walltime = '50' + #qsub.join = True + #qsub.node_type = node_type + #qsub.env['ROOTDIR'] = conf.rootdir + #qsub.env['JOBNAME'] = job.name + #if depend: + # qsub.afterok = cptjob + #if queue: + # qsub.queue = queue + qsub.properties = "64bit = 'Yes' or 64bit = 'No'" + qsub.build(script) + + if verbose: + print 'cwd: %s' % qsub.command + print 'PBS Command: %s' % qsub.command + + if not onlyecho: + ec = qsub.do() + if ec == 0: + jobid = qsub.result + print 'OAR Jobid: %s' % jobid + #namehack.setname(jobid, job.name) + queued = date() + jobdir.echofile('.batch_jobid', jobid) + jobdir.echofile('.batch_jobname', job.name) + jobdir.echofile('.queued', queued) + jobdir.setstatus('queued on %s' % queued) + else: + print 'OAR Failed' + print + print From 4a2c50bc8ff2dfda53d26c6f347ae5b2839daeb3 Mon Sep 17 00:00:00 2001 From: Kevin Lim Date: Wed, 23 Aug 2006 16:57:07 -0400 Subject: [PATCH 08/20] Support loading in a symbol file. arch/alpha/freebsd/system.cc: arch/alpha/isa/decoder.isa: arch/alpha/linux/system.cc: arch/alpha/system.cc: arch/alpha/tru64/system.cc: Let symbol files be read in so that profiling can happen on the binaries as well. python/m5/objects/System.py: Add in symbol files. sim/pseudo_inst.cc: Load in a specified symbol file. sim/pseudo_inst.hh: Allow for symbols to be loaded. sim/system.hh: Support symbol file. util/m5/m5.c: util/m5/m5op.S: Add support to m5 util for loading symbols (and readfile). --HG-- extra : convert_revision : f10c1049bcd7b22b98c73052c0666b964aff222b --- arch/alpha/freebsd/system.cc | 3 +++ arch/alpha/isa/decoder.isa | 3 +++ arch/alpha/linux/system.cc | 3 +++ arch/alpha/system.cc | 3 +++ arch/alpha/tru64/system.cc | 3 +++ python/m5/objects/System.py | 1 + sim/pseudo_inst.cc | 48 ++++++++++++++++++++++++++++++++++++ sim/pseudo_inst.hh | 1 + sim/system.hh | 1 + util/m5/m5.c | 22 +++++++++++++++++ util/m5/m5op.S | 8 ++++++ 11 files changed, 96 insertions(+) diff --git a/arch/alpha/freebsd/system.cc b/arch/alpha/freebsd/system.cc index e32053afd..000c7e55a 100644 --- a/arch/alpha/freebsd/system.cc +++ b/arch/alpha/freebsd/system.cc @@ -111,6 +111,7 @@ BEGIN_DECLARE_SIM_OBJECT_PARAMS(FreebsdAlphaSystem) Param boot_osflags; Param readfile; + Param symbolfile; Param init_param; Param system_type; @@ -133,6 +134,7 @@ BEGIN_INIT_SIM_OBJECT_PARAMS(FreebsdAlphaSystem) INIT_PARAM_DFLT(boot_osflags, "flags to pass to the kernel during boot", "a"), INIT_PARAM_DFLT(readfile, "file to read startup script from", ""), + INIT_PARAM_DFLT(symbolfile, "file to read symbols from", ""), INIT_PARAM_DFLT(init_param, "numerical value to pass into simulator", 0), INIT_PARAM_DFLT(system_type, "Type of system we are emulating", 34), INIT_PARAM_DFLT(system_rev, "Revision of system we are emulating", 1<<10), @@ -155,6 +157,7 @@ CREATE_SIM_OBJECT(FreebsdAlphaSystem) p->boot_osflags = boot_osflags; p->init_param = init_param; p->readfile = readfile; + p->symbolfile = symbolfile; p->system_type = system_type; p->system_rev = system_rev; p->bin = bin; diff --git a/arch/alpha/isa/decoder.isa b/arch/alpha/isa/decoder.isa index 71b9131aa..6cc6f3a84 100644 --- a/arch/alpha/isa/decoder.isa +++ b/arch/alpha/isa/decoder.isa @@ -785,6 +785,9 @@ decode OPCODE default Unknown::unknown() { AlphaPseudo::m5exit(xc->xcBase(), R16); }}, No_OpClass, IsNonSpeculative); 0x30: initparam({{ Ra = xc->xcBase()->getCpuPtr()->system->init_param; }}); + 0x31: loadsymbol({{ + AlphaPseudo::loadsymbol(xc->xcBase()); + }}, No_OpClass, IsNonSpeculative); 0x40: resetstats({{ AlphaPseudo::resetstats(xc->xcBase(), R16, R17); }}, IsNonSpeculative); diff --git a/arch/alpha/linux/system.cc b/arch/alpha/linux/system.cc index f9275d15e..608e98a8c 100644 --- a/arch/alpha/linux/system.cc +++ b/arch/alpha/linux/system.cc @@ -233,6 +233,7 @@ BEGIN_DECLARE_SIM_OBJECT_PARAMS(LinuxAlphaSystem) Param boot_osflags; Param readfile; + Param symbolfile; Param init_param; Param system_type; @@ -255,6 +256,7 @@ BEGIN_INIT_SIM_OBJECT_PARAMS(LinuxAlphaSystem) INIT_PARAM_DFLT(boot_osflags, "flags to pass to the kernel during boot", "a"), INIT_PARAM_DFLT(readfile, "file to read startup script from", ""), + INIT_PARAM_DFLT(symbolfile, "file to read symbols from", ""), INIT_PARAM_DFLT(init_param, "numerical value to pass into simulator", 0), INIT_PARAM_DFLT(system_type, "Type of system we are emulating", 34), INIT_PARAM_DFLT(system_rev, "Revision of system we are emulating", 1<<10), @@ -277,6 +279,7 @@ CREATE_SIM_OBJECT(LinuxAlphaSystem) p->boot_osflags = boot_osflags; p->init_param = init_param; p->readfile = readfile; + p->symbolfile = symbolfile; p->system_type = system_type; p->system_rev = system_rev; p->bin = bin; diff --git a/arch/alpha/system.cc b/arch/alpha/system.cc index 25543da57..a1d00464e 100644 --- a/arch/alpha/system.cc +++ b/arch/alpha/system.cc @@ -242,6 +242,7 @@ BEGIN_DECLARE_SIM_OBJECT_PARAMS(AlphaSystem) Param boot_osflags; Param readfile; + Param symbolfile; Param init_param; Param system_type; @@ -264,6 +265,7 @@ BEGIN_INIT_SIM_OBJECT_PARAMS(AlphaSystem) INIT_PARAM_DFLT(boot_osflags, "flags to pass to the kernel during boot", "a"), INIT_PARAM_DFLT(readfile, "file to read startup script from", ""), + INIT_PARAM_DFLT(symbolfile, "file to read symbols from", ""), INIT_PARAM_DFLT(init_param, "numerical value to pass into simulator", 0), INIT_PARAM_DFLT(system_type, "Type of system we are emulating", 34), INIT_PARAM_DFLT(system_rev, "Revision of system we are emulating", 1<<10), @@ -286,6 +288,7 @@ CREATE_SIM_OBJECT(AlphaSystem) p->boot_osflags = boot_osflags; p->init_param = init_param; p->readfile = readfile; + p->symbolfile = symbolfile; p->system_type = system_type; p->system_rev = system_rev; p->bin = bin; diff --git a/arch/alpha/tru64/system.cc b/arch/alpha/tru64/system.cc index d09a0c85d..06da9fe91 100644 --- a/arch/alpha/tru64/system.cc +++ b/arch/alpha/tru64/system.cc @@ -105,6 +105,7 @@ BEGIN_DECLARE_SIM_OBJECT_PARAMS(Tru64AlphaSystem) Param boot_osflags; Param readfile; + Param symbolfile; Param init_param; Param system_type; @@ -126,6 +127,7 @@ BEGIN_INIT_SIM_OBJECT_PARAMS(Tru64AlphaSystem) INIT_PARAM_DFLT(boot_osflags, "flags to pass to the kernel during boot", "a"), INIT_PARAM_DFLT(readfile, "file to read startup script from", ""), + INIT_PARAM_DFLT(symbolfile, "file to read symbols from", ""), INIT_PARAM_DFLT(init_param, "numerical value to pass into simulator", 0), INIT_PARAM_DFLT(system_type, "Type of system we are emulating", 12), INIT_PARAM_DFLT(system_rev, "Revision of system we are emulating", 2<<1), @@ -147,6 +149,7 @@ CREATE_SIM_OBJECT(Tru64AlphaSystem) p->boot_osflags = boot_osflags; p->init_param = init_param; p->readfile = readfile; + p->symbolfile = symbolfile; p->system_type = system_type; p->system_rev = system_rev; p->bin = bin; diff --git a/python/m5/objects/System.py b/python/m5/objects/System.py index 5925cadf5..40c4f24f2 100644 --- a/python/m5/objects/System.py +++ b/python/m5/objects/System.py @@ -11,6 +11,7 @@ class System(SimObject): binned_fns = VectorParam.String([], "functions broken down and binned") kernel = Param.String("file that contains the kernel code") readfile = Param.String("", "file to read startup script from") + symbolfile = Param.String("", "file to get the symbols from") class AlphaSystem(System): type = 'AlphaSystem' diff --git a/sim/pseudo_inst.cc b/sim/pseudo_inst.cc index 2d737c0a2..3b11eaaeb 100644 --- a/sim/pseudo_inst.cc +++ b/sim/pseudo_inst.cc @@ -149,6 +149,54 @@ namespace AlphaPseudo SimExit(when, "m5_exit instruction encountered"); } + void + loadsymbol(ExecContext *xc) + { + const string &filename = xc->getCpuPtr()->system->params()->symbolfile; + if (filename.empty()) { + return; + } + + std::string buffer; + ifstream file(filename.c_str()); + + if (!file) + fatal("file error: Can't open symbol table file %s\n", filename); + + while (!file.eof()) { + getline(file, buffer); + + if (buffer.empty()) + continue; + + int idx = buffer.find(' '); + if (idx == string::npos) + continue; + + string address = "0x" + buffer.substr(0, idx); + eat_white(address); + if (address.empty()) + continue; + + // Skip over letter and space + string symbol = buffer.substr(idx + 3); + eat_white(symbol); + if (symbol.empty()) + continue; + + Addr addr; + if (!to_number(address, addr)) + continue; + + if (!xc->getSystemPtr()->kernelSymtab->insert(addr, symbol)) + continue; + + + DPRINTF(Loader, "Loaded symbol: %s @ %#llx\n", symbol, addr); + } + file.close(); + } + void resetstats(ExecContext *xc, Tick delay, Tick period) { diff --git a/sim/pseudo_inst.hh b/sim/pseudo_inst.hh index 4dd427c99..595ddef1f 100644 --- a/sim/pseudo_inst.hh +++ b/sim/pseudo_inst.hh @@ -51,6 +51,7 @@ namespace AlphaPseudo void ivle(ExecContext *xc); void m5exit(ExecContext *xc, Tick delay); void m5exit_old(ExecContext *xc); + void loadsymbol(ExecContext *xc); void resetstats(ExecContext *xc, Tick delay, Tick period); void dumpstats(ExecContext *xc, Tick delay, Tick period); void dumpresetstats(ExecContext *xc, Tick delay, Tick period); diff --git a/sim/system.hh b/sim/system.hh index ea482a102..36aeb3700 100644 --- a/sim/system.hh +++ b/sim/system.hh @@ -137,6 +137,7 @@ class System : public SimObject std::string kernel_path; std::string readfile; + std::string symbolfile; }; protected: diff --git a/util/m5/m5.c b/util/m5/m5.c index 6fdbc0500..fa9be96e8 100644 --- a/util/m5/m5.c +++ b/util/m5/m5.c @@ -30,6 +30,7 @@ #include #include #include +#include #include "m5op.h" @@ -165,6 +166,22 @@ main(int argc, char *argv[]) } } + if (COMPARE("readfile")) { + char buf[256*1024]; + int offset = 0; + int len; + + if (argc != 2) + usage(); + + while ((len = m5_readfile(buf, sizeof(buf), offset)) > 0) { + write(STDOUT_FILENO, buf, len); + offset += len; + } + + return 0; + } + if (COMPARE("checkpoint")) { switch (argc) { case 4: @@ -182,5 +199,10 @@ main(int argc, char *argv[]) return 0; } + if (COMPARE("loadsymbol")) { + m5_loadsymbol(arg1); + return 0; + } + usage(); } diff --git a/util/m5/m5op.S b/util/m5/m5op.S index a53c45277..97eb9238d 100644 --- a/util/m5/m5op.S +++ b/util/m5/m5op.S @@ -38,6 +38,7 @@ #define exit_old_func 0x20 // deprectated! #define exit_func 0x21 #define initparam_func 0x30 +#define loadsymbol_func 0x31 #define resetstats_func 0x40 #define dumpstats_func 0x41 #define dumprststats_func 0x42 @@ -72,6 +73,7 @@ func: #define IVLE(reg) INST(m5_op, reg, 0, ivle_func) #define M5EXIT(reg) INST(m5_op, reg, 0, exit_func) #define INITPARAM(reg) INST(m5_op, reg, 0, initparam_func) +#define LOADSYMBOL(reg) INST(m5_op, reg, 0, loadsymbol_func) #define RESET_STATS(r1, r2) INST(m5_op, r1, r2, resetstats_func) #define DUMP_STATS(r1, r2) INST(m5_op, r1, r2, dumpstats_func) #define DUMPRST_STATS(r1, r2) INST(m5_op, r1, r2, dumprststats_func) @@ -139,6 +141,12 @@ LEAF(m5_initparam) RET END(m5_initparam) + .align 4 +LEAF(m5_loadsymbol) + LOADSYMBOL(0) + RET +END(m5_loadsymbol) + .align 4 LEAF(m5_reset_stats) RESET_STATS(16, 17) From 9fef4d46302077775a47b451175fc3bf785338b3 Mon Sep 17 00:00:00 2001 From: Kevin Lim Date: Thu, 24 Aug 2006 16:06:45 -0400 Subject: [PATCH 09/20] Stats reset, profiling stuff. cpu/base.cc: Be sure to deschedule the profile event so it doesn't take profiles while the CPU is switched out. Also include the option to reset stats at a specific instruction. cpu/base.hh: Include the option to reset stats at a specific instruction. cpu/checker/cpu_builder.cc: Handle stats reset inst. cpu/o3/alpha_cpu_builder.cc: Handle stats reset inst, allow for profiling. cpu/ozone/cpu_builder.cc: Handle profiling, stats reset event, slightly different parameters. python/m5/objects/BaseCPU.py: Add in stats reset. --HG-- extra : convert_revision : e27a78f7fb8fd19c53d9f2c1e6edce4a98cbafdb --- cpu/base.cc | 29 ++++++++++++++++++++++++----- cpu/base.hh | 3 +++ cpu/checker/cpu_builder.cc | 5 +++++ cpu/o3/alpha_cpu_builder.cc | 8 ++++++++ cpu/ozone/cpu_builder.cc | 18 ++++++++++++++++-- python/m5/objects/BaseCPU.py | 2 ++ 6 files changed, 58 insertions(+), 7 deletions(-) diff --git a/cpu/base.cc b/cpu/base.cc index 36950a683..044fafca9 100644 --- a/cpu/base.cc +++ b/cpu/base.cc @@ -45,6 +45,9 @@ #include "base/trace.hh" +// Hack +#include "sim/stat_control.hh" + using namespace std; vector BaseCPU::cpuList; @@ -84,6 +87,7 @@ BaseCPU::BaseCPU(Params *p) number_of_threads(p->numberOfThreads) #endif { +// currentTick = curTick; DPRINTF(FullCPU, "BaseCPU: Creating object, mem address %#x.\n", this); // add self to global list of CPUs @@ -145,6 +149,12 @@ BaseCPU::BaseCPU(Params *p) p->max_loads_all_threads, *counter); } + if (p->stats_reset_inst != 0) { + Stats::SetupEvent(Stats::Reset, p->stats_reset_inst, 0, comInstEventQueue[0]); + cprintf("Stats reset event scheduled for %lli insts\n", + p->stats_reset_inst); + } + #if FULL_SYSTEM memset(interrupts, 0, sizeof(interrupts)); intstatus = 0; @@ -261,12 +271,17 @@ BaseCPU::registerExecContexts() void BaseCPU::switchOut(Sampler *sampler) { - panic("This CPU doesn't support sampling!"); +// panic("This CPU doesn't support sampling!"); +#if FULL_SYSTEM + if (profileEvent && profileEvent->scheduled()) + profileEvent->deschedule(); +#endif } void BaseCPU::takeOverFrom(BaseCPU *oldCPU) { +// currentTick = oldCPU->currentTick; assert(execContexts.size() == oldCPU->execContexts.size()); for (int i = 0; i < execContexts.size(); ++i) { @@ -281,18 +296,22 @@ BaseCPU::takeOverFrom(BaseCPU *oldCPU) assert(newXC->getProcessPtr() == oldXC->getProcessPtr()); newXC->getProcessPtr()->replaceExecContext(newXC, newXC->readCpuId()); #endif + +// TheISA::compareXCs(oldXC, newXC); } #if FULL_SYSTEM for (int i = 0; i < TheISA::NumInterruptLevels; ++i) interrupts[i] = oldCPU->interrupts[i]; intstatus = oldCPU->intstatus; + checkInterrupts = oldCPU->checkInterrupts; - for (int i = 0; i < execContexts.size(); ++i) - execContexts[i]->profileClear(); +// for (int i = 0; i < execContexts.size(); ++i) +// execContexts[i]->profileClear(); - if (profileEvent) - profileEvent->schedule(curTick); + // The Sampler must take care of this! +// if (profileEvent) +// profileEvent->schedule(curTick); #endif } diff --git a/cpu/base.hh b/cpu/base.hh index 4f1578f67..3210b9120 100644 --- a/cpu/base.hh +++ b/cpu/base.hh @@ -67,9 +67,11 @@ class BaseCPU : public SimObject Tick clock; public: +// Tick currentTick; inline Tick frequency() const { return Clock::Frequency / clock; } inline Tick cycles(int numCycles) const { return clock * numCycles; } inline Tick curCycle() const { return curTick / clock; } +// inline Tick curCycle() { currentTick+=10000; return currentTick; } #if FULL_SYSTEM protected: @@ -134,6 +136,7 @@ class BaseCPU : public SimObject Counter max_insts_all_threads; Counter max_loads_any_thread; Counter max_loads_all_threads; + Counter stats_reset_inst; Tick clock; bool functionTrace; Tick functionTraceStart; diff --git a/cpu/checker/cpu_builder.cc b/cpu/checker/cpu_builder.cc index d1b5434c3..ec36ae09f 100644 --- a/cpu/checker/cpu_builder.cc +++ b/cpu/checker/cpu_builder.cc @@ -58,6 +58,7 @@ BEGIN_DECLARE_SIM_OBJECT_PARAMS(OzoneChecker) Param max_insts_all_threads; Param max_loads_any_thread; Param max_loads_all_threads; + Param stats_reset_inst; Param progress_interval; #if FULL_SYSTEM @@ -92,6 +93,8 @@ BEGIN_INIT_SIM_OBJECT_PARAMS(OzoneChecker) "terminate when any thread reaches this load count"), INIT_PARAM(max_loads_all_threads, "terminate when all threads have reached this load count"), + INIT_PARAM(stats_reset_inst, + "blah"), INIT_PARAM_DFLT(progress_interval, "CPU Progress Interval", 0), #if FULL_SYSTEM @@ -127,6 +130,7 @@ CREATE_SIM_OBJECT(OzoneChecker) params->max_insts_all_threads = 0; params->max_loads_any_thread = 0; params->max_loads_all_threads = 0; + params->stats_reset_inst = 0; params->exitOnError = exitOnError; params->updateOnError = updateOnError; params->deferRegistration = defer_registration; @@ -142,6 +146,7 @@ CREATE_SIM_OBJECT(OzoneChecker) temp = max_loads_all_threads; Tick temp2 = progress_interval; temp2++; + params->progress_interval = 0; BaseMem *cache = icache; cache = dcache; diff --git a/cpu/o3/alpha_cpu_builder.cc b/cpu/o3/alpha_cpu_builder.cc index fa0e892aa..a1924afc6 100644 --- a/cpu/o3/alpha_cpu_builder.cc +++ b/cpu/o3/alpha_cpu_builder.cc @@ -55,6 +55,7 @@ SimObjectParam system; Param cpu_id; SimObjectParam itb; SimObjectParam dtb; +Param profile; #else SimObjectVectorParam workload; //SimObjectParam page_table; @@ -68,6 +69,7 @@ Param max_insts_any_thread; Param max_insts_all_threads; Param max_loads_any_thread; Param max_loads_all_threads; +Param stats_reset_inst; Param progress_interval; SimObjectParam icache; @@ -167,6 +169,7 @@ BEGIN_INIT_SIM_OBJECT_PARAMS(DerivAlphaFullCPU) INIT_PARAM(cpu_id, "processor ID"), INIT_PARAM(itb, "Instruction translation buffer"), INIT_PARAM(dtb, "Data translation buffer"), + INIT_PARAM(profile, ""), #else INIT_PARAM(workload, "Processes to run"), // INIT_PARAM(page_table, "Page table"), @@ -190,6 +193,9 @@ BEGIN_INIT_SIM_OBJECT_PARAMS(DerivAlphaFullCPU) "Terminate when all threads have reached this load" "count", 0), + INIT_PARAM_DFLT(stats_reset_inst, + "blah", + 0), INIT_PARAM_DFLT(progress_interval, "Progress interval", 0), INIT_PARAM_DFLT(icache, "L1 instruction cache", NULL), @@ -316,6 +322,7 @@ CREATE_SIM_OBJECT(DerivAlphaFullCPU) params->cpu_id = cpu_id; params->itb = itb; params->dtb = dtb; + params->profile = profile; #else params->workload = workload; // params->pTable = page_table; @@ -329,6 +336,7 @@ CREATE_SIM_OBJECT(DerivAlphaFullCPU) params->max_insts_all_threads = max_insts_all_threads; params->max_loads_any_thread = max_loads_any_thread; params->max_loads_all_threads = max_loads_all_threads; + params->stats_reset_inst = stats_reset_inst; params->progress_interval = progress_interval; // diff --git a/cpu/ozone/cpu_builder.cc b/cpu/ozone/cpu_builder.cc index 9df5962c8..c863839d4 100644 --- a/cpu/ozone/cpu_builder.cc +++ b/cpu/ozone/cpu_builder.cc @@ -71,6 +71,7 @@ SimObjectParam system; Param cpu_id; SimObjectParam itb; SimObjectParam dtb; +Param profile; #else SimObjectVectorParam workload; //SimObjectParam page_table; @@ -84,6 +85,7 @@ Param max_insts_any_thread; Param max_insts_all_threads; Param max_loads_any_thread; Param max_loads_all_threads; +Param stats_reset_inst; Param progress_interval; SimObjectParam icache; @@ -91,10 +93,11 @@ SimObjectParam dcache; Param cachePorts; Param width; +Param frontEndLatency; Param frontEndWidth; +Param backEndLatency; Param backEndWidth; Param backEndSquashLatency; -Param backEndLatency; Param maxInstBufferSize; Param numPhysicalRegs; Param maxOutstandingMemOps; @@ -149,6 +152,7 @@ Param RASSize; Param LQEntries; Param SQEntries; +Param lsqLimits; Param LFSTSize; Param SSITSize; @@ -190,6 +194,7 @@ BEGIN_INIT_SIM_OBJECT_PARAMS(DerivOzoneCPU) INIT_PARAM(cpu_id, "processor ID"), INIT_PARAM(itb, "Instruction translation buffer"), INIT_PARAM(dtb, "Data translation buffer"), + INIT_PARAM(profile, ""), #else INIT_PARAM(workload, "Processes to run"), // INIT_PARAM(page_table, "Page table"), @@ -213,6 +218,9 @@ BEGIN_INIT_SIM_OBJECT_PARAMS(DerivOzoneCPU) "Terminate when all threads have reached this load" "count", 0), + INIT_PARAM_DFLT(stats_reset_inst, + "blah", + 0), INIT_PARAM_DFLT(progress_interval, "Progress interval", 0), INIT_PARAM_DFLT(icache, "L1 instruction cache", NULL), @@ -220,10 +228,11 @@ BEGIN_INIT_SIM_OBJECT_PARAMS(DerivOzoneCPU) INIT_PARAM_DFLT(cachePorts, "Cache Ports", 200), INIT_PARAM_DFLT(width, "Width", 1), + INIT_PARAM_DFLT(frontEndLatency, "Front end latency", 1), INIT_PARAM_DFLT(frontEndWidth, "Front end width", 1), + INIT_PARAM_DFLT(backEndLatency, "Back end latency", 1), INIT_PARAM_DFLT(backEndWidth, "Back end width", 1), INIT_PARAM_DFLT(backEndSquashLatency, "Back end squash latency", 1), - INIT_PARAM_DFLT(backEndLatency, "Back end latency", 1), INIT_PARAM_DFLT(maxInstBufferSize, "Maximum instruction buffer size", 16), INIT_PARAM(numPhysicalRegs, "Number of physical registers"), INIT_PARAM_DFLT(maxOutstandingMemOps, "Maximum outstanding memory operations", 4), @@ -284,6 +293,7 @@ BEGIN_INIT_SIM_OBJECT_PARAMS(DerivOzoneCPU) INIT_PARAM(LQEntries, "Number of load queue entries"), INIT_PARAM(SQEntries, "Number of store queue entries"), + INIT_PARAM_DFLT(lsqLimits, "LSQ size limits dispatch", true), INIT_PARAM(LFSTSize, "Last fetched store table size"), INIT_PARAM(SSITSize, "Store set ID table size"), @@ -346,6 +356,7 @@ CREATE_SIM_OBJECT(DerivOzoneCPU) params->cpu_id = cpu_id; params->itb = itb; params->dtb = dtb; + params->profile = profile; #else params->workload = workload; // params->pTable = page_table; @@ -357,6 +368,7 @@ CREATE_SIM_OBJECT(DerivOzoneCPU) params->max_insts_all_threads = max_insts_all_threads; params->max_loads_any_thread = max_loads_any_thread; params->max_loads_all_threads = max_loads_all_threads; + params->stats_reset_inst = stats_reset_inst; params->progress_interval = progress_interval; // @@ -368,6 +380,7 @@ CREATE_SIM_OBJECT(DerivOzoneCPU) params->width = width; params->frontEndWidth = frontEndWidth; + params->frontEndLatency = frontEndLatency; params->backEndWidth = backEndWidth; params->backEndSquashLatency = backEndSquashLatency; params->backEndLatency = backEndLatency; @@ -425,6 +438,7 @@ CREATE_SIM_OBJECT(DerivOzoneCPU) params->LQEntries = LQEntries; params->SQEntries = SQEntries; + params->lsqLimits = lsqLimits; params->SSITSize = SSITSize; params->LFSTSize = LFSTSize; diff --git a/python/m5/objects/BaseCPU.py b/python/m5/objects/BaseCPU.py index 29fb6ebce..91a3bafbf 100644 --- a/python/m5/objects/BaseCPU.py +++ b/python/m5/objects/BaseCPU.py @@ -22,6 +22,8 @@ class BaseCPU(SimObject): "terminate when all threads have reached this load count") max_loads_any_thread = Param.Counter(0, "terminate when any thread reaches this load count") + stats_reset_inst = Param.Counter(0, + "reset stats once this many instructions are committed") progress_interval = Param.Tick(0, "interval to print out the progress message") defer_registration = Param.Bool(False, From 5da3f70560cddce24969840dd97f82b03428ba67 Mon Sep 17 00:00:00 2001 From: Kevin Lim Date: Thu, 24 Aug 2006 17:22:31 -0400 Subject: [PATCH 10/20] Update checker. cpu/checker/cpu.cc: Print better error messages. cpu/checker/cpu.hh: Fix up small bug (similar to Ozone's DynInsts with FPs and float/doubles), output better messages. --HG-- extra : convert_revision : 0e199b3dbbcdb5917cdfbebb4c5c18e4b9056c86 --- cpu/checker/cpu.cc | 38 +++++++++++++++++++++++++++++++------- cpu/checker/cpu.hh | 25 +++++++++++++++++-------- 2 files changed, 48 insertions(+), 15 deletions(-) diff --git a/cpu/checker/cpu.cc b/cpu/checker/cpu.cc index 071559b7c..f34621d45 100644 --- a/cpu/checker/cpu.cc +++ b/cpu/checker/cpu.cc @@ -410,6 +410,14 @@ CheckerCPU::checkFlags(MemReqPtr &req) } } +void +CheckerCPU::dumpAndExit() +{ + warn("%lli: Checker PC:%#x, next PC:%#x", + curTick, cpuXC->readPC(), cpuXC->readNextPC()); + panic("Checker found an error!"); +} + template void Checker::tick(DynInstPtr &completed_inst) @@ -487,7 +495,7 @@ Checker::tick(DynInstPtr &completed_inst) warn("%lli: Changed PC does not match expected PC, " "changed: %#x, expected: %#x", curTick, cpuXC->readPC(), newPC); - handleError(); + CheckerCPU::handleError(); } willChangePC = false; } @@ -523,7 +531,7 @@ Checker::tick(DynInstPtr &completed_inst) // possible that its ITB entry was kicked out. warn("%lli: Instruction PC %#x was not found in the ITB!", curTick, cpuXC->readPC()); - handleError(); + handleError(inst); // go to the next instruction cpuXC->setPC(cpuXC->readNextPC()); @@ -661,7 +669,7 @@ Checker::validateInst(DynInstPtr &inst) warn("%lli: Changed PCs recently, may not be an error", curTick); } else { - handleError(); + handleError(inst); } } @@ -671,7 +679,7 @@ Checker::validateInst(DynInstPtr &inst) warn("%lli: Binary instructions do not match! Inst: %#x, " "checker: %#x", curTick, mi, machInst); - handleError(); + handleError(inst); } } @@ -697,7 +705,7 @@ Checker::validateExecution(DynInstPtr &inst) warn("%lli: Instruction results do not match! (Results may not " "actually be integers) Inst: %#x, checker: %#x", curTick, inst->readIntResult(), result.integer); - handleError(); + handleError(inst); } } @@ -705,7 +713,7 @@ Checker::validateExecution(DynInstPtr &inst) warn("%lli: Instruction next PCs do not match! Inst: %#x, " "checker: %#x", curTick, inst->readNextPC(), cpuXC->readNextPC()); - handleError(); + handleError(inst); } // Checking side effect registers can be difficult if they are not @@ -724,7 +732,7 @@ Checker::validateExecution(DynInstPtr &inst) curTick, misc_reg_idx, inst->xcBase()->readMiscReg(misc_reg_idx), cpuXC->readMiscReg(misc_reg_idx)); - handleError(); + handleError(inst); } } } @@ -753,6 +761,22 @@ Checker::validateState() } } +template +void +Checker::dumpAndExit(DynInstPtr &inst) +{ + cprintf("Error detected, instruction information:\n"); + cprintf("PC:%#x, nextPC:%#x\n[sn:%lli]\n[tid:%i]\n" + "Completed:%i\n", + inst->readPC(), + inst->readNextPC(), + inst->seqNum, + inst->threadNumber, + inst->isCompleted()); + inst->dump(); + CheckerCPU::dumpAndExit(); +} + template void Checker::dumpInsts() diff --git a/cpu/checker/cpu.hh b/cpu/checker/cpu.hh index 3000cee92..ccbbb3728 100644 --- a/cpu/checker/cpu.hh +++ b/cpu/checker/cpu.hh @@ -129,7 +129,7 @@ class CheckerCPU : public BaseCPU union Result { uint64_t integer; - float fp; +// float fp; double dbl; }; @@ -230,7 +230,7 @@ class CheckerCPU : public BaseCPU { int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag; cpuXC->setFloatRegSingle(reg_idx, val); - result.fp = val; + result.dbl = (double)val; } void setFloatRegDouble(const StaticInst *si, int idx, double val) @@ -275,7 +275,7 @@ class CheckerCPU : public BaseCPU return cpuXC->setMiscRegWithEffect(misc_reg, val); } - void recordPCChange(uint64_t val) { changedPC = true; } + void recordPCChange(uint64_t val) { changedPC = true; newPC = val; } void recordNextPCChange(uint64_t val) { changedNextPC = true; } bool translateInstReq(MemReqPtr &req); @@ -295,10 +295,16 @@ class CheckerCPU : public BaseCPU void syscall() { } #endif - virtual void handleError() = 0; + void handleError() + { + if (exitOnError) + dumpAndExit(); + } bool checkFlags(MemReqPtr &req); + void dumpAndExit(); + ExecContext *xcBase() { return xcProxy; } CPUExecContext *cpuXCBase() { return cpuXC; } @@ -338,14 +344,17 @@ class Checker : public CheckerCPU void validateExecution(DynInstPtr &inst); void validateState(); - virtual void handleError() + void handleError(DynInstPtr &inst) { - if (exitOnError) - panic("Checker found error!"); - else if (updateOnError) + if (exitOnError) { + dumpAndExit(inst); + } else if (updateOnError) { updateThisCycle = true; + } } + void dumpAndExit(DynInstPtr &inst); + bool updateThisCycle; DynInstPtr unverifiedInst; From 74e8abd37ecd637a607f90e36aed1a3a16eea7da Mon Sep 17 00:00:00 2001 From: Kevin Lim Date: Thu, 24 Aug 2006 17:29:34 -0400 Subject: [PATCH 11/20] Switch out fixups for the CPUs. cpu/cpu_exec_context.cc: Be sure to switch over the kernel stats so things don't get messed up. This may lead to weird stats files for sampling runs (detailed stats should be correct, regardless of which kernel stats this is defined on). cpu/o3/cpu.cc: Updates for switching out. Also include a bunch of debug info if needed. cpu/o3/fetch_impl.hh: Switch out properly. cpu/o3/inst_queue.hh: cpu/o3/inst_queue_impl.hh: Comment out unused stats (they made the stats file huge). cpu/o3/lsq_unit.hh: cpu/o3/lsq_unit_impl.hh: Add in new stat. cpu/o3/rename.hh: Fix up for switching out. cpu/o3/rename_impl.hh: Fix up for switching out. Be sure to mark any Misc regs as ready if their renamed inst got squashed from being switched out. cpu/ozone/cpu_impl.hh: cpu/simple/cpu.cc: Switch out fixup. sim/eventq.hh: Make CPU switching more immediate. Also comment out the assertion, as it doesn't apply if we're putting it on an inst-based queue. --HG-- extra : convert_revision : f40ed40604738993f061e0c628810ff37a920562 --- cpu/cpu_exec_context.cc | 5 ++++ cpu/o3/cpu.cc | 40 ++++++++++++++++++++++++++ cpu/o3/fetch_impl.hh | 3 +- cpu/o3/inst_queue.hh | 4 +-- cpu/o3/inst_queue_impl.hh | 7 +++-- cpu/o3/lsq_unit.hh | 3 ++ cpu/o3/lsq_unit_impl.hh | 5 ++++ cpu/o3/rename.hh | 2 ++ cpu/o3/rename_impl.hh | 8 +++++- cpu/ozone/cpu_impl.hh | 59 +++++++++++++++++++++++++++++---------- cpu/simple/cpu.cc | 31 +++++++++++++++----- sim/eventq.hh | 6 ++-- 12 files changed, 142 insertions(+), 31 deletions(-) diff --git a/cpu/cpu_exec_context.cc b/cpu/cpu_exec_context.cc index 0dcf149fd..9f151dd6a 100644 --- a/cpu/cpu_exec_context.cc +++ b/cpu/cpu_exec_context.cc @@ -183,6 +183,11 @@ CPUExecContext::takeOverFrom(ExecContext *oldContext) if (quiesceEvent) { quiesceEvent->xc = proxy; } + + Kernel::Statistics *stats = oldContext->getKernelStats(); + if (stats) { + kernelStats = stats; + } #endif storeCondFailures = 0; diff --git a/cpu/o3/cpu.cc b/cpu/o3/cpu.cc index 0025d4144..88de6c746 100644 --- a/cpu/o3/cpu.cc +++ b/cpu/o3/cpu.cc @@ -599,8 +599,11 @@ FullO3CPU::activateContext(int tid, int delay) // Be sure to signal that there's some activity so the CPU doesn't // deschedule itself. activityRec.activity(); + +#if FULL_SYSTEM if (thread[tid]->quiesceEvent && thread[tid]->quiesceEvent->scheduled()) thread[tid]->quiesceEvent->deschedule(); +#endif fetch.wakeFromQuiesce(); @@ -671,6 +674,8 @@ template void FullO3CPU::switchOut(Sampler *_sampler) { + DPRINTF(FullCPU, "Switching out\n"); + BaseCPU::switchOut(_sampler); sampler = _sampler; switchCount = 0; fetch.switchOut(); @@ -694,6 +699,41 @@ FullO3CPU::signalSwitched() rename.doSwitchOut(); commit.doSwitchOut(); instList.clear(); + +#ifndef NDEBUG + PhysRegIndex renamed_reg; + // First loop through the integer registers. + for (int i = 0; i < AlphaISA::NumIntRegs; ++i) { + renamed_reg = renameMap[0].lookup(i); + assert(renamed_reg == commitRenameMap[0].lookup(i)); + + DPRINTF(FullCPU, "FullCPU: Checking if register %i is ready.\n", + renamed_reg); + + assert(scoreboard.getReg(renamed_reg)); + } + + // Then loop through the floating point registers. + for (int i = 0; i < AlphaISA::NumFloatRegs; ++i) { + renamed_reg = renameMap[0].lookup(i + AlphaISA::FP_Base_DepTag); + assert(renamed_reg == commitRenameMap[0].lookup(i + AlphaISA::FP_Base_DepTag)); + + DPRINTF(FullCPU, "FullCPU: Checking if register %i is ready.\n", + renamed_reg); + + assert(scoreboard.getReg(renamed_reg)); + } + + for (int i = 0; i < AlphaISA::NumMiscRegs; ++i) { + renamed_reg = i + ((Params *)params)->numPhysFloatRegs + ((Params *)params)->numPhysIntRegs; + + DPRINTF(FullCPU, "FullCPU: Checking if register %i is ready.\n", + renamed_reg); + + assert(scoreboard.getReg(renamed_reg)); + } +#endif + while (!removeList.empty()) { removeList.pop(); } diff --git a/cpu/o3/fetch_impl.hh b/cpu/o3/fetch_impl.hh index cc09c4a41..7a3292dbe 100644 --- a/cpu/o3/fetch_impl.hh +++ b/cpu/o3/fetch_impl.hh @@ -391,6 +391,7 @@ DefaultFetch::takeOverFrom() wroteToTimeBuffer = false; _status = Inactive; switchedOut = false; + interruptPending = false; branchPred.takeOverFrom(); } @@ -469,7 +470,7 @@ DefaultFetch::fetchCacheLine(Addr fetch_PC, Fault &ret_fault, unsigned tid unsigned flags = 0; #endif // FULL_SYSTEM - if (interruptPending && flags == 0) { + if (isSwitchedOut() || (interruptPending && flags == 0)) { // Hold off fetch from getting new instructions while an interrupt // is pending. return false; diff --git a/cpu/o3/inst_queue.hh b/cpu/o3/inst_queue.hh index 80cd71f0d..e96fbc667 100644 --- a/cpu/o3/inst_queue.hh +++ b/cpu/o3/inst_queue.hh @@ -474,11 +474,11 @@ class InstructionQueue Stats::Scalar<> iqSquashedNonSpecRemoved; /** Distribution of number of instructions in the queue. */ - Stats::VectorDistribution<> queueResDist; +// Stats::VectorDistribution<> queueResDist; /** Distribution of the number of instructions issued. */ Stats::Distribution<> numIssuedDist; /** Distribution of the cycles it takes to issue an instruction. */ - Stats::VectorDistribution<> issueDelayDist; +// Stats::VectorDistribution<> issueDelayDist; /** Number of times an instruction could not be issued because a * FU was busy. diff --git a/cpu/o3/inst_queue_impl.hh b/cpu/o3/inst_queue_impl.hh index 72cb0d708..b6b06ca77 100644 --- a/cpu/o3/inst_queue_impl.hh +++ b/cpu/o3/inst_queue_impl.hh @@ -230,7 +230,7 @@ InstructionQueue::regStats() .name(name() + ".iqSquashedNonSpecRemoved") .desc("Number of squashed non-spec instructions that were removed") .prereq(iqSquashedNonSpecRemoved); - +/* queueResDist .init(Num_OpClasses, 0, 99, 2) .name(name() + ".IQ:residence:") @@ -240,6 +240,7 @@ InstructionQueue::regStats() for (int i = 0; i < Num_OpClasses; ++i) { queueResDist.subname(i, opClassStrings[i]); } +*/ numIssuedDist .init(0,totalWidth,1) .name(name() + ".ISSUE:issued_per_cycle") @@ -268,7 +269,7 @@ InstructionQueue::regStats() // // How long did instructions for a particular FU type wait prior to issue // - +/* issueDelayDist .init(Num_OpClasses,0,99,2) .name(name() + ".ISSUE:") @@ -281,7 +282,7 @@ InstructionQueue::regStats() subname << opClassStrings[i] << "_delay"; issueDelayDist.subname(i, subname.str()); } - +*/ issueRate .name(name() + ".ISSUE:rate") .desc("Inst issue rate") diff --git a/cpu/o3/lsq_unit.hh b/cpu/o3/lsq_unit.hh index fe174a97d..1db6dc02d 100644 --- a/cpu/o3/lsq_unit.hh +++ b/cpu/o3/lsq_unit.hh @@ -382,6 +382,9 @@ class LSQUnit { * ignored due to the instruction already being squashed. */ Stats::Scalar<> lsqIgnoredResponses; + /** Tota number of memory ordering violations. */ + Stats::Scalar<> lsqMemOrderViolation; + /** Total number of squashed stores. */ Stats::Scalar<> lsqSquashedStores; diff --git a/cpu/o3/lsq_unit_impl.hh b/cpu/o3/lsq_unit_impl.hh index 5cc3078f8..7086c381e 100644 --- a/cpu/o3/lsq_unit_impl.hh +++ b/cpu/o3/lsq_unit_impl.hh @@ -144,6 +144,10 @@ LSQUnit::regStats() .name(name() + ".ignoredResponses") .desc("Number of memory responses ignored because the instruction is squashed"); + lsqMemOrderViolation + .name(name() + ".memOrderViolation") + .desc("Number of memory ordering violations"); + lsqSquashedStores .name(name() + ".squashedStores") .desc("Number of stores squashed"); @@ -495,6 +499,7 @@ LSQUnit::executeStore(DynInstPtr &store_inst) // A load incorrectly passed this store. Squash and refetch. // For now return a fault to show that it was unsuccessful. memDepViolator = loadQueue[load_idx]; + ++lsqMemOrderViolation; return genMachineCheckFault(); } diff --git a/cpu/o3/rename.hh b/cpu/o3/rename.hh index 4912431ad..5769dbd37 100644 --- a/cpu/o3/rename.hh +++ b/cpu/o3/rename.hh @@ -411,6 +411,8 @@ class DefaultRename /** The maximum skid buffer size. */ unsigned skidBufferMax; + PhysRegIndex maxPhysicalRegs; + /** Enum to record the source of a structure full stall. Can come from * either ROB, IQ, LSQ, and it is priortized in that order. */ diff --git a/cpu/o3/rename_impl.hh b/cpu/o3/rename_impl.hh index 93f5b3504..49627e3d4 100644 --- a/cpu/o3/rename_impl.hh +++ b/cpu/o3/rename_impl.hh @@ -40,7 +40,8 @@ DefaultRename::DefaultRename(Params *params) commitToRenameDelay(params->commitToRenameDelay), renameWidth(params->renameWidth), commitWidth(params->commitWidth), - numThreads(params->numberOfThreads) + numThreads(params->numberOfThreads), + maxPhysicalRegs(params->numPhysIntRegs + params->numPhysFloatRegs) { _status = Inactive; @@ -283,6 +284,11 @@ DefaultRename::doSwitchOut() // Put the renamed physical register back on the free list. freeList->addReg(hb_it->newPhysReg); + // Be sure to mark its register as ready if it's a misc register. + if (hb_it->newPhysReg >= maxPhysicalRegs) { + scoreboard->setReg(hb_it->newPhysReg); + } + historyBuffer[i].erase(hb_it++); } insts[i].clear(); diff --git a/cpu/ozone/cpu_impl.hh b/cpu/ozone/cpu_impl.hh index 050bdb9a3..1a0de29f5 100644 --- a/cpu/ozone/cpu_impl.hh +++ b/cpu/ozone/cpu_impl.hh @@ -184,7 +184,9 @@ OzoneCPU::OzoneCPU(Params *p) globalSeqNum = 1; +#if FULL_SYSTEM checkInterrupts = false; +#endif lockFlag = 0; @@ -213,6 +215,7 @@ template void OzoneCPU::switchOut(Sampler *_sampler) { + BaseCPU::switchOut(_sampler); sampler = _sampler; switchCount = 0; // Front end needs state from back end, so switch out the back end first. @@ -234,6 +237,16 @@ OzoneCPU::signalSwitched() checker->switchOut(sampler); _status = SwitchedOut; +#ifndef NDEBUG + // Loop through all registers + for (int i = 0; i < AlphaISA::TotalNumRegs; ++i) { + assert(thread.renameTable[i] == frontEnd->renameTable[i]); + + assert(thread.renameTable[i] == backEnd->renameTable[i]); + + DPRINTF(OzoneCPU, "Checking if register %i matches.\n", i); + } +#endif if (tickEvent.scheduled()) tickEvent.squash(); @@ -256,9 +269,16 @@ OzoneCPU::takeOverFrom(BaseCPU *oldCPU) frontEnd->takeOverFrom(); assert(!tickEvent.scheduled()); +#ifndef NDEBUG + // Check rename table. + for (int i = 0; i < TheISA::TotalNumRegs; ++i) { + assert(thread.renameTable[i]->isResultReady()); + } +#endif + // @todo: Fix hardcoded number // Clear out any old information in time buffer. - for (int i = 0; i < 6; ++i) { + for (int i = 0; i < 15; ++i) { comm.advance(); } @@ -291,8 +311,10 @@ OzoneCPU::activateContext(int thread_num, int delay) scheduleTickEvent(delay); _status = Running; thread._status = ExecContext::Active; +#if FULL_SYSTEM if (thread.quiesceEvent && thread.quiesceEvent->scheduled()) thread.quiesceEvent->deschedule(); +#endif frontEnd->wakeFromQuiesce(); } @@ -369,7 +391,7 @@ template void OzoneCPU::resetStats() { - startNumInst = numInst; +// startNumInst = numInst; notIdleFraction = (_status != Idle); } @@ -777,7 +799,9 @@ OzoneCPU::OzoneXC::halt() template void OzoneCPU::OzoneXC::dumpFuncProfile() -{ } +{ + thread->dumpFuncProfile(); +} #endif template @@ -797,6 +821,7 @@ OzoneCPU::OzoneXC::takeOverFrom(ExecContext *old_context) copyArchRegs(old_context); setCpuId(old_context->readCpuId()); + thread->inst = old_context->getInst(); #if !FULL_SYSTEM setFuncExeInst(old_context->readFuncExeInst()); #else @@ -869,16 +894,14 @@ template void OzoneCPU::OzoneXC::profileClear() { - if (thread->profile) - thread->profile->clear(); + thread->profileClear(); } template void OzoneCPU::OzoneXC::profileSample() { - if (thread->profile) - thread->profile->sample(thread->profileNode, thread->profilePC); + thread->profileSample(); } #endif @@ -906,14 +929,20 @@ OzoneCPU::OzoneXC::copyArchRegs(ExecContext *xc) cpu->frontEnd->setPC(thread->PC); cpu->frontEnd->setNextPC(thread->nextPC); - for (int i = 0; i < TheISA::TotalNumRegs; ++i) { - if (i < TheISA::FP_Base_DepTag) { - thread->renameTable[i]->setIntResult(xc->readIntReg(i)); - } else if (i < (TheISA::FP_Base_DepTag + TheISA::NumFloatRegs)) { - int fp_idx = i - TheISA::FP_Base_DepTag; - thread->renameTable[i]->setDoubleResult( - xc->readFloatRegDouble(fp_idx)); - } + // First loop through the integer registers. + for (int i = 0; i < TheISA::NumIntRegs; ++i) { +/* DPRINTF(OzoneCPU, "Copying over register %i, had data %lli, " + "now has data %lli.\n", + i, thread->renameTable[i]->readIntResult(), + xc->readIntReg(i)); +*/ + thread->renameTable[i]->setIntResult(xc->readIntReg(i)); + } + + // Then loop through the floating point registers. + for (int i = 0; i < TheISA::NumFloatRegs; ++i) { + int fp_idx = i + TheISA::FP_Base_DepTag; + thread->renameTable[fp_idx]->setIntResult(xc->readFloatRegInt(i)); } #if !FULL_SYSTEM diff --git a/cpu/simple/cpu.cc b/cpu/simple/cpu.cc index 0a4b3c3e4..eb19115b2 100644 --- a/cpu/simple/cpu.cc +++ b/cpu/simple/cpu.cc @@ -181,7 +181,9 @@ SimpleCPU::switchOut(Sampler *s) _status = SwitchedOut; if (tickEvent.scheduled()) - tickEvent.squash(); + tickEvent.deschedule(); + + assert(!tickEvent.scheduled()); sampler->signalSwitched(); } @@ -294,7 +296,7 @@ SimpleCPU::regStats() void SimpleCPU::resetStats() { - startNumInst = numInst; +// startNumInst = numInst; notIdleFraction = (_status != Idle); } @@ -352,6 +354,7 @@ SimpleCPU::copySrcTranslate(Addr src) Fault fault = cpuXC->translateDataReadReq(memReq); if (fault == NoFault) { + panic("We can't copy!"); cpuXC->copySrcAddr = src; cpuXC->copySrcPhysAddr = memReq->paddr + offset; } else { @@ -600,6 +603,8 @@ SimpleCPU::dbg_vtophys(Addr addr) void SimpleCPU::processCacheCompletion() { + Fault fault; + switch (status()) { case IcacheMissStall: icacheStallCycles += curTick - lastIcacheStall; @@ -618,12 +623,17 @@ SimpleCPU::processCacheCompletion() break; case DcacheMissSwitch: if (memReq->cmd.isRead()) { - curStaticInst->execute(this,traceData); + fault = curStaticInst->execute(this,traceData); if (traceData) traceData->finalize(); + } else { + fault = NoFault; } + assert(fault == NoFault); + assert(!tickEvent.scheduled()); _status = SwitchedOut; sampler->signalSwitched(); + return; case SwitchedOut: // If this CPU has been switched out due to sampling/warm-up, // ignore any further status changes (e.g., due to cache @@ -787,9 +797,10 @@ SimpleCPU::tick() } if (cpuXC->profile) { - bool usermode = - (cpuXC->readMiscReg(AlphaISA::IPR_DTB_CM) & 0x18) != 0; - cpuXC->profilePC = usermode ? 1 : cpuXC->readPC(); +// bool usermode = +// (cpuXC->readMiscReg(AlphaISA::IPR_DTB_CM) & 0x18) != 0; +// cpuXC->profilePC = usermode ? 1 : cpuXC->readPC(); + cpuXC->profilePC = cpuXC->readPC(); ProfileNode *node = cpuXC->profile->consume(xcProxy, inst); if (node) cpuXC->profileNode = node; @@ -849,8 +860,10 @@ SimpleCPU::tick() status() == Idle || status() == DcacheMissStall); - if (status() == Running && !tickEvent.scheduled()) + if (status() == Running && !tickEvent.scheduled()) { + assert(_status != SwitchedOut); tickEvent.schedule(curTick + cycles(1)); + } } //////////////////////////////////////////////////////////////////////// @@ -863,6 +876,7 @@ BEGIN_DECLARE_SIM_OBJECT_PARAMS(SimpleCPU) Param max_insts_all_threads; Param max_loads_any_thread; Param max_loads_all_threads; + Param stats_reset_inst; Param progress_interval; #if FULL_SYSTEM @@ -897,6 +911,8 @@ BEGIN_INIT_SIM_OBJECT_PARAMS(SimpleCPU) "terminate when any thread reaches this load count"), INIT_PARAM(max_loads_all_threads, "terminate when all threads have reached this load count"), + INIT_PARAM(stats_reset_inst, + "instruction to reset stats on"), INIT_PARAM_DFLT(progress_interval, "CPU Progress interval", 0), #if FULL_SYSTEM @@ -930,6 +946,7 @@ CREATE_SIM_OBJECT(SimpleCPU) params->max_insts_all_threads = max_insts_all_threads; params->max_loads_any_thread = max_loads_any_thread; params->max_loads_all_threads = max_loads_all_threads; + params->stats_reset_inst = stats_reset_inst; params->deferRegistration = defer_registration; params->clock = clock; params->functionTrace = function_trace; diff --git a/sim/eventq.hh b/sim/eventq.hh index 5fc73bb53..b9a0abc12 100644 --- a/sim/eventq.hh +++ b/sim/eventq.hh @@ -43,6 +43,7 @@ #include "sim/host.hh" // for Tick #include "base/fast_alloc.hh" +#include "base/misc.hh" #include "base/trace.hh" #include "sim/serialize.hh" @@ -131,7 +132,7 @@ class Event : public Serializable, public FastAlloc /// same cycle (after unscheduling the old CPU's tick event). /// The switch needs to come before any tick events to make /// sure we don't tick both CPUs in the same cycle. - CPU_Switch_Pri = 31, + CPU_Switch_Pri = -31, /// Serailization needs to occur before tick events also, so /// that a serialize/unserialize is identical to an on-line @@ -344,7 +345,8 @@ inline void Event::schedule(Tick t) { assert(!scheduled()); - assert(t >= curTick); +// if (t < curTick) +// warn("t is less than curTick, ensure you don't want cycles"); setFlags(Scheduled); #if TRACING_ON From ad2fa1e1c9587e8c2a2b7f3e5a9c592312042eb4 Mon Sep 17 00:00:00 2001 From: Kevin Lim Date: Thu, 24 Aug 2006 17:43:08 -0400 Subject: [PATCH 12/20] Support profiling. --HG-- extra : convert_revision : eab02dea68442bd3f8c5d1d16b7f93f43cbda2a5 --- cpu/o3/alpha_cpu_impl.hh | 24 +++++++++++++----------- cpu/o3/commit_impl.hh | 14 ++++++++++++++ cpu/o3/thread_state.hh | 29 +++++++++++++++++++++++++++-- cpu/ozone/thread_state.hh | 26 +++++++++++++++++++++++++- cpu/thread_state.hh | 15 +++++++++++++++ python/m5/objects/AlphaFullCPU.py | 2 ++ python/m5/objects/OzoneCPU.py | 4 ++++ 7 files changed, 100 insertions(+), 14 deletions(-) diff --git a/cpu/o3/alpha_cpu_impl.hh b/cpu/o3/alpha_cpu_impl.hh index 1bf0652cd..071a870ef 100644 --- a/cpu/o3/alpha_cpu_impl.hh +++ b/cpu/o3/alpha_cpu_impl.hh @@ -153,15 +153,6 @@ AlphaFullCPU::regStats() this->commit.regStats(); } -#if FULL_SYSTEM -template -void -AlphaFullCPU::AlphaXC::dumpFuncProfile() -{ - // Currently not supported -} -#endif - template void AlphaFullCPU::AlphaXC::takeOverFrom(ExecContext *old_context) @@ -334,15 +325,26 @@ AlphaFullCPU::AlphaXC::readLastSuspend() return thread->lastSuspend; } +template +void +AlphaFullCPU::AlphaXC::dumpFuncProfile() +{ + thread->dumpFuncProfile(); +} + template void AlphaFullCPU::AlphaXC::profileClear() -{} +{ + thread->profileClear(); +} template void AlphaFullCPU::AlphaXC::profileSample() -{} +{ + thread->profileSample(); +} #endif template diff --git a/cpu/o3/commit_impl.hh b/cpu/o3/commit_impl.hh index 364e685c2..cd10ec6b2 100644 --- a/cpu/o3/commit_impl.hh +++ b/cpu/o3/commit_impl.hh @@ -1035,6 +1035,20 @@ DefaultCommit::commitHead(DynInstPtr &head_inst, unsigned inst_num) updateComInstStats(head_inst); +#if FULL_SYSTEM + if (thread[tid]->profile) { +// bool usermode = +// (cpu->readMiscReg(AlphaISA::IPR_DTB_CM, tid) & 0x18) != 0; +// thread[tid]->profilePC = usermode ? 1 : head_inst->readPC(); + thread[tid]->profilePC = head_inst->readPC(); + ProfileNode *node = thread[tid]->profile->consume(thread[tid]->getXCProxy(), + head_inst->staticInst); + + if (node) + thread[tid]->profileNode = node; + } +#endif + if (head_inst->traceData) { head_inst->traceData->setFetchSeq(head_inst->seqNum); head_inst->traceData->setCPSeq(thread[tid]->numInst); diff --git a/cpu/o3/thread_state.hh b/cpu/o3/thread_state.hh index 3f1208ea0..28f488143 100644 --- a/cpu/o3/thread_state.hh +++ b/cpu/o3/thread_state.hh @@ -31,8 +31,11 @@ #include "arch/faults.hh" #include "arch/isa_traits.hh" +#include "base/callback.hh" +#include "base/output.hh" #include "cpu/exec_context.hh" #include "cpu/thread_state.hh" +#include "sim/sim_exit.hh" class Event; class Process; @@ -83,8 +86,22 @@ struct O3ThreadState : public ThreadState { #if FULL_SYSTEM O3ThreadState(FullCPU *_cpu, int _thread_num, FunctionalMemory *_mem) : ThreadState(-1, _thread_num, _mem), - inSyscall(0), trapPending(0) - { } + cpu(_cpu), inSyscall(0), trapPending(0) + { + if (cpu->params->profile) { + profile = new FunctionProfile(cpu->params->system->kernelSymtab); + Callback *cb = + new MakeCallback(this); + registerExitCallback(cb); + } + + // let's fill with a dummy node for now so we don't get a segfault + // on the first cycle when there's no node available. + static ProfileNode dummyNode; + profileNode = &dummyNode; + profilePC = 3; + } #else O3ThreadState(FullCPU *_cpu, int _thread_num, Process *_process, int _asid) : ThreadState(-1, _thread_num, _process->getMemory(), _process, _asid), @@ -138,6 +155,14 @@ struct O3ThreadState : public ThreadState { /** Handles the syscall. */ void syscall() { process->syscall(xcProxy); } #endif + +#if FULL_SYSTEM + void dumpFuncProfile() + { + std::ostream *os = simout.create(csprintf("profile.%s.dat", cpu->name())); + profile->dump(xcProxy, *os); + } +#endif }; #endif // __CPU_O3_THREAD_STATE_HH__ diff --git a/cpu/ozone/thread_state.hh b/cpu/ozone/thread_state.hh index f104dff23..93a56da1b 100644 --- a/cpu/ozone/thread_state.hh +++ b/cpu/ozone/thread_state.hh @@ -31,9 +31,12 @@ #include "arch/faults.hh" #include "arch/isa_traits.hh" +#include "base/callback.hh" +#include "base/output.hh" #include "cpu/exec_context.hh" #include "cpu/thread_state.hh" #include "sim/process.hh" +#include "sim/sim_exit.hh" class Event; //class Process; @@ -62,9 +65,22 @@ struct OzoneThreadState : public ThreadState { #if FULL_SYSTEM OzoneThreadState(FullCPU *_cpu, int _thread_num, FunctionalMemory *_mem) : ThreadState(-1, _thread_num, _mem), - inSyscall(0), trapPending(0) + cpu(_cpu), inSyscall(0), trapPending(0) { memset(®s, 0, sizeof(TheISA::RegFile)); + if (cpu->params->profile) { + profile = new FunctionProfile(cpu->params->system->kernelSymtab); + Callback *cb = + new MakeCallback(this); + registerExitCallback(cb); + } + + // let's fill with a dummy node for now so we don't get a segfault + // on the first cycle when there's no node available. + static ProfileNode dummyNode; + profileNode = &dummyNode; + profilePC = 3; } #else OzoneThreadState(FullCPU *_cpu, int _thread_num, Process *_process, int _asid) @@ -187,6 +203,14 @@ struct OzoneThreadState : public ThreadState { Counter readFuncExeInst() { return funcExeInst; } void setFuncExeInst(Counter new_val) { funcExeInst = new_val; } + +#if FULL_SYSTEM + void dumpFuncProfile() + { + std::ostream *os = simout.create(csprintf("profile.%s.dat", cpu->name())); + profile->dump(xcProxy, *os); + } +#endif }; #endif // __CPU_OZONE_THREAD_STATE_HH__ diff --git a/cpu/thread_state.hh b/cpu/thread_state.hh index 12146bd11..7a19963c8 100644 --- a/cpu/thread_state.hh +++ b/cpu/thread_state.hh @@ -30,6 +30,7 @@ #define __CPU_THREAD_STATE_HH__ #include "cpu/exec_context.hh" +#include "cpu/profile.hh" #if FULL_SYSTEM class EndQuiesceEvent; @@ -103,6 +104,20 @@ struct ThreadState { #endif +#if FULL_SYSTEM + void profileClear() + { + if (profile) + profile->clear(); + } + + void profileSample() + { + if (profile) + profile->sample(profileNode, profilePC); + } +#endif + /** * Temporary storage to pass the source address from copy_load to * copy_store. diff --git a/python/m5/objects/AlphaFullCPU.py b/python/m5/objects/AlphaFullCPU.py index 015e9d872..5b6fa1063 100644 --- a/python/m5/objects/AlphaFullCPU.py +++ b/python/m5/objects/AlphaFullCPU.py @@ -10,6 +10,8 @@ class DerivAlphaFullCPU(BaseCPU): mem = Param.FunctionalMemory(NULL, "memory") checker = Param.BaseCPU(NULL, "checker") + if build_env['FULL_SYSTEM']: + profile = Param.Latency('0ns', "trace the kernel stack") cachePorts = Param.Unsigned("Cache Ports") diff --git a/python/m5/objects/OzoneCPU.py b/python/m5/objects/OzoneCPU.py index ea8b6b537..dadca7990 100644 --- a/python/m5/objects/OzoneCPU.py +++ b/python/m5/objects/OzoneCPU.py @@ -10,9 +10,12 @@ class DerivOzoneCPU(BaseCPU): mem = Param.FunctionalMemory(NULL, "memory") checker = Param.BaseCPU("Checker CPU") + if build_env['FULL_SYSTEM']: + profile = Param.Latency('0ns', "trace the kernel stack") width = Param.Unsigned("Width") frontEndWidth = Param.Unsigned("Front end width") + frontEndLatency = Param.Unsigned("Front end latency") backEndWidth = Param.Unsigned("Back end width") backEndSquashLatency = Param.Unsigned("Back end squash latency") backEndLatency = Param.Unsigned("Back end latency") @@ -75,6 +78,7 @@ class DerivOzoneCPU(BaseCPU): LQEntries = Param.Unsigned("Number of load queue entries") SQEntries = Param.Unsigned("Number of store queue entries") + lsqLimits = Param.Bool(True, "LSQ size limits dispatch") LFSTSize = Param.Unsigned("Last fetched store table size") SSITSize = Param.Unsigned("Store set ID table size") From 4ec5e90c8fa72a4bea34a35d0f0194cefae37f81 Mon Sep 17 00:00:00 2001 From: Kevin Lim Date: Thu, 24 Aug 2006 17:45:04 -0400 Subject: [PATCH 13/20] Ozone updates. cpu/ozone/front_end.hh: cpu/ozone/front_end_impl.hh: cpu/ozone/lw_back_end.hh: Support latency for Ozone FE and BE. cpu/ozone/lw_back_end_impl.hh: Support latency for Ozone FE and BE. Also fixes for switching out, profiling. cpu/ozone/lw_lsq.hh: cpu/ozone/lw_lsq_impl.hh: Fixes for switching out. cpu/ozone/simple_params.hh: Updated parameters. --HG-- extra : convert_revision : 21d4846a59a2239bfdf8fe92e47fd0972debe4f5 --- cpu/ozone/front_end.hh | 7 ++ cpu/ozone/front_end_impl.hh | 38 +++++++- cpu/ozone/lw_back_end.hh | 18 ++-- cpu/ozone/lw_back_end_impl.hh | 170 ++++++++++++++++++++++++++-------- cpu/ozone/lw_lsq.hh | 17 +++- cpu/ozone/lw_lsq_impl.hh | 49 ++++++++-- cpu/ozone/simple_params.hh | 4 +- 7 files changed, 236 insertions(+), 67 deletions(-) diff --git a/cpu/ozone/front_end.hh b/cpu/ozone/front_end.hh index dd382491f..b677e667c 100644 --- a/cpu/ozone/front_end.hh +++ b/cpu/ozone/front_end.hh @@ -31,6 +31,7 @@ #include +#include "base/timebuf.hh" #include "cpu/inst_seq.hh" #include "cpu/o3/bpred_unit.hh" #include "cpu/ozone/rename_table.hh" @@ -210,15 +211,21 @@ class FrontEnd void dumpInsts(); private: + TimeBuffer numInstsReady; + typedef typename std::deque InstBuff; typedef typename InstBuff::iterator InstBuffIt; + InstBuff feBuffer; + InstBuff instBuffer; int instBufferSize; int maxInstBufferSize; + int latency; + int width; int freeRegs; diff --git a/cpu/ozone/front_end_impl.hh b/cpu/ozone/front_end_impl.hh index ca9948b7d..09fc2e2f8 100644 --- a/cpu/ozone/front_end_impl.hh +++ b/cpu/ozone/front_end_impl.hh @@ -41,8 +41,10 @@ template FrontEnd::FrontEnd(Params *params) : branchPred(params), icacheInterface(params->icacheInterface), + numInstsReady(params->frontEndLatency, 0), instBufferSize(0), maxInstBufferSize(params->maxInstBufferSize), + latency(params->frontEndLatency), width(params->frontEndWidth), freeRegs(params->numPhysicalRegs), numPhysRegs(params->numPhysicalRegs), @@ -261,6 +263,18 @@ FrontEnd::tick() if (switchedOut) return; + for (int insts_to_queue = numInstsReady[-latency]; + !instBuffer.empty() && insts_to_queue; + --insts_to_queue) + { + DPRINTF(FE, "Transferring instruction [sn:%lli] to the feBuffer\n", + instBuffer.front()->seqNum); + feBuffer.push_back(instBuffer.front()); + instBuffer.pop_front(); + } + + numInstsReady.advance(); + // @todo: Maybe I want to just have direct communication... if (fromCommit->doneSeqNum) { branchPred.update(fromCommit->doneSeqNum, 0); @@ -349,6 +363,7 @@ FrontEnd::tick() // latency instBuffer.push_back(inst); ++instBufferSize; + numInstsReady[0]++; ++num_inst; #if FULL_SYSTEM @@ -570,6 +585,7 @@ FrontEnd::handleFault(Fault &fault) instruction->fault = fault; instruction->setCanIssue(); instBuffer.push_back(instruction); + numInstsReady[0]++; ++instBufferSize; } @@ -599,6 +615,21 @@ FrontEnd::squash(const InstSeqNum &squash_num, const Addr &next_PC, freeRegs+= inst->numDestRegs(); } + while (!feBuffer.empty() && + feBuffer.back()->seqNum > squash_num) { + DynInstPtr inst = feBuffer.back(); + + DPRINTF(FE, "Squashing instruction [sn:%lli] PC %#x\n", + inst->seqNum, inst->readPC()); + + inst->clearDependents(); + + feBuffer.pop_back(); + --instBufferSize; + + freeRegs+= inst->numDestRegs(); + } + // Copy over rename table from the back end. renameTable.copyFrom(backEnd->renameTable); @@ -633,13 +664,13 @@ template typename Impl::DynInstPtr FrontEnd::getInst() { - if (instBufferSize == 0) { + if (feBuffer.empty()) { return NULL; } - DynInstPtr inst = instBuffer.front(); + DynInstPtr inst = feBuffer.front(); - instBuffer.pop_front(); + feBuffer.pop_front(); --instBufferSize; @@ -857,6 +888,7 @@ FrontEnd::doSwitchOut() squash(0, 0); instBuffer.clear(); instBufferSize = 0; + feBuffer.clear(); status = Idle; } diff --git a/cpu/ozone/lw_back_end.hh b/cpu/ozone/lw_back_end.hh index 19f2b2b61..4e2f5606c 100644 --- a/cpu/ozone/lw_back_end.hh +++ b/cpu/ozone/lw_back_end.hh @@ -78,7 +78,7 @@ class LWBackEnd TimeBuffer i2e; typename TimeBuffer::wire instsToExecute; TimeBuffer e2c; - TimeBuffer numInstsToWB; + TimeBuffer numInstsToWB; TimeBuffer *comm; typename TimeBuffer::wire toIEW; @@ -157,7 +157,7 @@ class LWBackEnd Tick lastCommitCycle; - bool robEmpty() { return instList.empty(); } + bool robEmpty() { return numInsts == 0; } bool isFull() { return numInsts >= numROBEntries; } bool isBlocked() { return status == Blocked || dispatchStatus == Blocked; } @@ -212,6 +212,7 @@ class LWBackEnd } void instToCommit(DynInstPtr &inst); + void readyInstsForCommit(); void switchOut(); void doSwitchOut(); @@ -293,12 +294,13 @@ class LWBackEnd MemReqPtr memReq; + int latency; + // General back end width. Used if the more specific isn't given. int width; // Dispatch width. int dispatchWidth; - int numDispatchEntries; int dispatchSize; int waitingInsts; @@ -323,6 +325,7 @@ class LWBackEnd int numROBEntries; int numInsts; + bool lsqLimits; std::set waitingMemOps; typedef std::set::iterator MemIt; @@ -333,9 +336,6 @@ class LWBackEnd InstSeqNum squashSeqNum; Addr squashNextPC; - Fault faultFromFetch; - bool fetchHasFault; - bool switchedOut; bool switchPending; @@ -359,8 +359,6 @@ class LWBackEnd std::list replayList; std::list writeback; - int latency; - int squashLatency; bool exactFullStall; @@ -397,9 +395,11 @@ class LWBackEnd Stats::Scalar<> lsqInversion; Stats::Vector<> nIssuedDist; +/* Stats::VectorDistribution<> issueDelayDist; Stats::VectorDistribution<> queueResDist; +*/ /* Stats::Vector<> stat_fu_busy; Stats::Vector2d<> stat_fuBusy; @@ -447,7 +447,7 @@ class LWBackEnd Stats::Vector<> ROBCount; // cumulative ROB occupancy Stats::Formula ROBOccRate; - Stats::VectorDistribution<> ROBOccDist; +// Stats::VectorDistribution<> ROBOccDist; public: void dumpInsts(); diff --git a/cpu/ozone/lw_back_end_impl.hh b/cpu/ozone/lw_back_end_impl.hh index 9e1cd28cf..9a6ad4c14 100644 --- a/cpu/ozone/lw_back_end_impl.hh +++ b/cpu/ozone/lw_back_end_impl.hh @@ -151,8 +151,10 @@ LWBackEnd::LdWritebackEvent::process() // iewStage->wakeCPU(); - if (be->isSwitchedOut()) - return; + assert(inst->isSquashed() || !be->isSwitchedOut()); + +// if (be->isSwitchedOut() && inst->isLoad()) +// return; if (dcacheMiss) { be->removeDcacheMiss(inst); @@ -208,14 +210,14 @@ LWBackEnd::DCacheCompletionEvent::description() template LWBackEnd::LWBackEnd(Params *params) - : d2i(5, 5), i2e(5, 5), e2c(5, 5), numInstsToWB(5, 5), + : d2i(5, 5), i2e(5, 5), e2c(5, 5), numInstsToWB(params->backEndLatency, 0), trapSquash(false), xcSquash(false), cacheCompletionEvent(this), - dcacheInterface(params->dcacheInterface), width(params->backEndWidth), + dcacheInterface(params->dcacheInterface), latency(params->backEndLatency), + width(params->backEndWidth), lsqLimits(params->lsqLimits), exactFullStall(true) { numROBEntries = params->numROBEntries; numInsts = 0; - numDispatchEntries = 32; maxOutstandingMemOps = params->maxOutstandingMemOps; numWaitingMemOps = 0; waitingInsts = 0; @@ -251,6 +253,8 @@ void LWBackEnd::regStats() { using namespace Stats; + LSQ.regStats(); + robCapEvents .init(cpu->number_of_threads) .name(name() + ".ROB:cap_events") @@ -377,6 +381,7 @@ LWBackEnd::regStats() .desc("Number of insts issued each cycle") .flags(total | pdf | dist) ; +/* issueDelayDist .init(Num_OpClasses,0,99,2) .name(name() + ".ISSUE:") @@ -393,7 +398,7 @@ LWBackEnd::regStats() for (int i = 0; i < Num_OpClasses; ++i) { queueResDist.subname(i, opClassStrings[i]); } - +*/ writebackCount .init(cpu->number_of_threads) .name(name() + ".WB:count") @@ -555,13 +560,14 @@ LWBackEnd::regStats() .flags(total) ; ROBOccRate = ROBCount / cpu->numCycles; - +/* ROBOccDist .init(cpu->number_of_threads,0,numROBEntries,2) .name(name() + ".ROB:occ_dist") .desc("ROB Occupancy per cycle") .flags(total | cdf) ; +*/ } template @@ -654,18 +660,22 @@ LWBackEnd::tick() { DPRINTF(BE, "Ticking back end\n"); + // Read in any done instruction information and update the IQ or LSQ. + updateStructures(); + if (switchPending && robEmpty() && !LSQ.hasStoresToWB()) { cpu->signalSwitched(); return; } + readyInstsForCommit(); + + numInstsToWB.advance(); + ROBCount[0]+= numInsts; wbCycle = 0; - // Read in any done instruction information and update the IQ or LSQ. - updateStructures(); - #if FULL_SYSTEM checkInterrupts(); @@ -740,6 +750,10 @@ LWBackEnd::dispatchInsts() while (numInsts < numROBEntries && numWaitingMemOps < maxOutstandingMemOps) { // Get instruction from front of time buffer + if (lsqLimits && LSQ.isFull()) { + break; + } + DynInstPtr inst = frontEnd->getInst(); if (!inst) { break; @@ -798,6 +812,7 @@ LWBackEnd::dispatchInsts() inst->setIssued(); inst->setExecuted(); inst->setCanCommit(); + numInstsToWB[0]++; } else { DPRINTF(BE, "Instruction [sn:%lli] ready, addding to " "exeList.\n", @@ -987,16 +1002,10 @@ template void LWBackEnd::instToCommit(DynInstPtr &inst) { - DPRINTF(BE, "Sending instructions to commit [sn:%lli] PC %#x.\n", inst->seqNum, inst->readPC()); if (!inst->isSquashed()) { - DPRINTF(BE, "Writing back instruction [sn:%lli] PC %#x.\n", - inst->seqNum, inst->readPC()); - - inst->setCanCommit(); - if (inst->isExecuted()) { inst->setResultReady(); int dependents = wakeDependents(inst); @@ -1007,8 +1016,32 @@ LWBackEnd::instToCommit(DynInstPtr &inst) } } + writeback.push_back(inst); + + numInstsToWB[0]++; + writebackCount[0]++; } + +template +void +LWBackEnd::readyInstsForCommit() +{ + for (int i = numInstsToWB[-latency]; + !writeback.empty() && i; + --i) + { + DynInstPtr inst = writeback.front(); + writeback.pop_front(); + if (!inst->isSquashed()) { + DPRINTF(BE, "Writing back instruction [sn:%lli] PC %#x.\n", + inst->seqNum, inst->readPC()); + + inst->setCanCommit(); + } + } +} + #if 0 template void @@ -1221,6 +1254,20 @@ LWBackEnd::commitInst(int inst_num) ++freed_regs; } +#if FULL_SYSTEM + if (thread->profile) { +// bool usermode = +// (xc->readMiscReg(AlphaISA::IPR_DTB_CM) & 0x18) != 0; +// thread->profilePC = usermode ? 1 : inst->readPC(); + thread->profilePC = inst->readPC(); + ProfileNode *node = thread->profile->consume(thread->getXCProxy(), + inst->staticInst); + + if (node) + thread->profileNode = node; + } +#endif + if (inst->traceData) { inst->traceData->setFetchSeq(inst->seqNum); inst->traceData->setCPSeq(thread->numInst); @@ -1280,9 +1327,9 @@ LWBackEnd::commitInsts() while (!instList.empty() && inst_num < commitWidth) { if (instList.back()->isSquashed()) { instList.back()->clearDependents(); + ROBSquashedInsts[instList.back()->threadNumber]++; instList.pop_back(); --numInsts; - ROBSquashedInsts[instList.back()->threadNumber]++; continue; } @@ -1304,10 +1351,10 @@ LWBackEnd::squash(const InstSeqNum &sn) LSQ.squash(sn); int freed_regs = 0; - InstListIt waiting_list_end = waitingList.end(); + InstListIt insts_end_it = waitingList.end(); InstListIt insts_it = waitingList.begin(); - while (insts_it != waiting_list_end && (*insts_it)->seqNum > sn) + while (insts_it != insts_end_it && (*insts_it)->seqNum > sn) { if ((*insts_it)->isSquashed()) { ++insts_it; @@ -1333,6 +1380,7 @@ LWBackEnd::squash(const InstSeqNum &sn) while (!instList.empty() && (*insts_it)->seqNum > sn) { if ((*insts_it)->isSquashed()) { + panic("Instruction should not be already squashed and on list!"); ++insts_it; continue; } @@ -1364,18 +1412,6 @@ LWBackEnd::squash(const InstSeqNum &sn) --numInsts; } - insts_it = waitingList.begin(); - while (!waitingList.empty() && insts_it != waitingList.end()) { - if ((*insts_it)->seqNum < sn) { - ++insts_it; - continue; - } - assert((*insts_it)->isSquashed()); - - waitingList.erase(insts_it++); - waitingInsts--; - } - while (memBarrier && memBarrier->seqNum > sn) { DPRINTF(BE, "[sn:%lli] Memory barrier squashed (or previously " "squashed)\n", memBarrier->seqNum); @@ -1393,6 +1429,18 @@ LWBackEnd::squash(const InstSeqNum &sn) } } + insts_it = replayList.begin(); + insts_end_it = replayList.end(); + while (!replayList.empty() && insts_it != insts_end_it) { + if ((*insts_it)->seqNum < sn) { + ++insts_it; + continue; + } + assert((*insts_it)->isSquashed()); + + replayList.erase(insts_it++); + } + frontEnd->addFreeRegs(freed_regs); } @@ -1463,14 +1511,6 @@ LWBackEnd::squashDueToMemBlocked(DynInstPtr &inst) frontEnd->squash(inst->seqNum - 1, inst->readPC()); } -template -void -LWBackEnd::fetchFault(Fault &fault) -{ - faultFromFetch = fault; - fetchHasFault = true; -} - template void LWBackEnd::switchOut() @@ -1489,16 +1529,25 @@ LWBackEnd::doSwitchOut() // yet written back. assert(robEmpty()); assert(!LSQ.hasStoresToWB()); + writeback.clear(); + for (int i = 0; i < numInstsToWB.getSize() + 1; ++i) + numInstsToWB.advance(); +// squash(0); + assert(waitingList.empty()); + assert(instList.empty()); + assert(replayList.empty()); + assert(writeback.empty()); LSQ.switchOut(); - - squash(0); } template void LWBackEnd::takeOverFrom(ExecContext *old_xc) { + assert(!squashPending); + squashSeqNum = 0; + squashNextPC = 0; xcSquash = false; trapSquash = false; @@ -1641,6 +1690,45 @@ LWBackEnd::dumpInsts() ++num; } + inst_list_it = --(writeback.end()); + + cprintf("Writeback list size: %i\n", writeback.size()); + + while (inst_list_it != writeback.end()) + { + cprintf("Instruction:%i\n", + num); + if (!(*inst_list_it)->isSquashed()) { + if (!(*inst_list_it)->isIssued()) { + ++valid_num; + cprintf("Count:%i\n", valid_num); + } else if ((*inst_list_it)->isMemRef() && + !(*inst_list_it)->memOpDone) { + // Loads that have not been marked as executed still count + // towards the total instructions. + ++valid_num; + cprintf("Count:%i\n", valid_num); + } + } + + cprintf("PC:%#x\n[sn:%lli]\n[tid:%i]\n" + "Issued:%i\nSquashed:%i\n", + (*inst_list_it)->readPC(), + (*inst_list_it)->seqNum, + (*inst_list_it)->threadNumber, + (*inst_list_it)->isIssued(), + (*inst_list_it)->isSquashed()); + + if ((*inst_list_it)->isMemRef()) { + cprintf("MemOpDone:%i\n", (*inst_list_it)->memOpDone); + } + + cprintf("\n"); + + inst_list_it--; + ++num; + } + cprintf("Waiting list size: %i\n", waitingList.size()); inst_list_it = --(waitingList.end()); diff --git a/cpu/ozone/lw_lsq.hh b/cpu/ozone/lw_lsq.hh index c0bf0b0fe..07fd1aec5 100644 --- a/cpu/ozone/lw_lsq.hh +++ b/cpu/ozone/lw_lsq.hh @@ -110,6 +110,8 @@ class OzoneLWLSQ { /** Returns the name of the LSQ unit. */ std::string name() const; + void regStats(); + /** Sets the CPU pointer. */ void setCPU(FullCPU *cpu_ptr) { cpu = cpu_ptr; } @@ -203,7 +205,7 @@ class OzoneLWLSQ { int numLoads() { return loads; } /** Returns the number of stores in the SQ. */ - int numStores() { return stores; } + int numStores() { return stores + storesInFlight; } /** Returns if either the LQ or SQ is full. */ bool isFull() { return lqFull() || sqFull(); } @@ -212,7 +214,7 @@ class OzoneLWLSQ { bool lqFull() { return loads >= (LQEntries - 1); } /** Returns if the SQ is full. */ - bool sqFull() { return stores >= (SQEntries - 1); } + bool sqFull() { return (stores + storesInFlight) >= (SQEntries - 1); } /** Debugging function to dump instructions in the LSQ. */ void dumpInsts(); @@ -241,7 +243,9 @@ class OzoneLWLSQ { private: /** Completes the store at the specified index. */ - void completeStore(int store_idx); + void completeStore(DynInstPtr &inst); + + void removeStore(int store_idx); private: /** Pointer to the CPU. */ @@ -342,6 +346,10 @@ class OzoneLWLSQ { int storesToWB; + public: + int storesInFlight; + + private: /// @todo Consider moving to a more advanced model with write vs read ports /** The number of cache ports available each cycle. */ int cachePorts; @@ -351,6 +359,9 @@ class OzoneLWLSQ { //list mshrSeqNums; + /** Tota number of memory ordering violations. */ + Stats::Scalar<> lsqMemOrderViolation; + //Stats::Scalar<> dcacheStallCycles; Counter lastDcacheStall; diff --git a/cpu/ozone/lw_lsq_impl.hh b/cpu/ozone/lw_lsq_impl.hh index f72bbb1cc..c60884fc3 100644 --- a/cpu/ozone/lw_lsq_impl.hh +++ b/cpu/ozone/lw_lsq_impl.hh @@ -57,6 +57,7 @@ OzoneLWLSQ::StoreCompletionEvent::process() // lsqPtr->cpu->wakeCPU(); if (lsqPtr->isSwitchedOut()) { + panic("Should not be switched out!"); if (wbEvent) delete wbEvent; @@ -68,7 +69,11 @@ OzoneLWLSQ::StoreCompletionEvent::process() delete wbEvent; } - lsqPtr->completeStore(inst->sqIdx); + lsqPtr->completeStore(inst); + lsqPtr->removeStore(inst->sqIdx); + --(lsqPtr->storesInFlight); + + DPRINTF(OzoneLSQ, "StoresInFlight: %i\n", lsqPtr->storesInFlight); if (miss) be->removeDcacheMiss(inst); } @@ -82,7 +87,7 @@ OzoneLWLSQ::StoreCompletionEvent::description() template OzoneLWLSQ::OzoneLWLSQ() - : loads(0), stores(0), storesToWB(0), stalled(false), isLoadBlocked(false), + : loads(0), stores(0), storesToWB(0), storesInFlight(0), stalled(false), isLoadBlocked(false), loadBlockedHandled(false) { } @@ -121,6 +126,15 @@ OzoneLWLSQ::name() const return "lsqunit"; } +template +void +OzoneLWLSQ::regStats() +{ + lsqMemOrderViolation + .name(name() + ".memOrderViolation") + .desc("Number of memory ordering violations"); +} + template void OzoneLWLSQ::clearLQ() @@ -257,7 +271,7 @@ unsigned OzoneLWLSQ::numFreeEntries() { unsigned free_lq_entries = LQEntries - loads; - unsigned free_sq_entries = SQEntries - stores; + unsigned free_sq_entries = SQEntries - (stores + storesInFlight); // Both the LQ and SQ entries have an extra dummy entry to differentiate // empty/full conditions. Subtract 1 from the free entries. @@ -397,6 +411,7 @@ OzoneLWLSQ::executeStore(DynInstPtr &store_inst) // A load incorrectly passed this store. Squash and refetch. // For now return a fault to show that it was unsuccessful. memDepViolator = (*lq_it); + ++lsqMemOrderViolation; return TheISA::genMachineCheckFault(); } @@ -483,8 +498,8 @@ OzoneLWLSQ::writebackStores() if ((*sq_it).size == 0 && !(*sq_it).completed) { sq_it--; - completeStore(inst->sqIdx); - + removeStore(inst->sqIdx); + completeStore(inst); continue; } @@ -540,6 +555,8 @@ OzoneLWLSQ::writebackStores() inst->sqIdx,inst->readPC(), req->paddr, *(req->data), inst->seqNum); + DPRINTF(OzoneLSQ, "StoresInFlight: %i\n", + storesInFlight + 1); if (dcacheInterface) { assert(!req->completionEvent); @@ -601,6 +618,8 @@ OzoneLWLSQ::writebackStores() } sq_it--; } + ++storesInFlight; +// removeStore(inst->sqIdx); } else { panic("Must HAVE DCACHE!!!!!\n"); } @@ -617,7 +636,7 @@ void OzoneLWLSQ::squash(const InstSeqNum &squashed_num) { DPRINTF(OzoneLSQ, "Squashing until [sn:%lli]!" - "(Loads:%i Stores:%i)\n",squashed_num,loads,stores); + "(Loads:%i Stores:%i)\n",squashed_num,loads,stores+storesInFlight); LQIt lq_it = loadQueue.begin(); @@ -732,7 +751,7 @@ OzoneLWLSQ::dumpInsts() template void -OzoneLWLSQ::completeStore(int store_idx) +OzoneLWLSQ::removeStore(int store_idx) { SQHashIt sq_hash_it = SQItHash.find(store_idx); assert(sq_hash_it != SQItHash.end()); @@ -742,8 +761,6 @@ OzoneLWLSQ::completeStore(int store_idx) (*sq_it).completed = true; DynInstPtr inst = (*sq_it).inst; - --storesToWB; - if (isStalled() && inst->seqNum == stallingStoreIsn) { DPRINTF(OzoneLSQ, "Unstalling, stalling store [sn:%lli] " @@ -761,6 +778,13 @@ OzoneLWLSQ::completeStore(int store_idx) SQItHash.erase(sq_hash_it); SQIndices.push(inst->sqIdx); storeQueue.erase(sq_it); +} + +template +void +OzoneLWLSQ::completeStore(DynInstPtr &inst) +{ + --storesToWB; --stores; inst->setCompleted(); @@ -839,9 +863,14 @@ OzoneLWLSQ::switchOut() } // Clear the queue to free up resources + assert(stores == 0); + assert(storeQueue.empty()); + assert(loads == 0); + assert(loadQueue.empty()); + assert(storesInFlight == 0); storeQueue.clear(); loadQueue.clear(); - loads = stores = storesToWB = 0; + loads = stores = storesToWB = storesInFlight = 0; } template diff --git a/cpu/ozone/simple_params.hh b/cpu/ozone/simple_params.hh index 7b5c6f67b..d28d040f8 100644 --- a/cpu/ozone/simple_params.hh +++ b/cpu/ozone/simple_params.hh @@ -70,10 +70,11 @@ class SimpleParams : public BaseCPU::Params unsigned cachePorts; unsigned width; + unsigned frontEndLatency; unsigned frontEndWidth; + unsigned backEndLatency; unsigned backEndWidth; unsigned backEndSquashLatency; - unsigned backEndLatency; unsigned maxInstBufferSize; unsigned numPhysicalRegs; unsigned maxOutstandingMemOps; @@ -149,6 +150,7 @@ class SimpleParams : public BaseCPU::Params // unsigned LQEntries; unsigned SQEntries; + bool lsqLimits; // // Memory dependence From 9ef831eeefb691eb73531471f7c04bca286f464a Mon Sep 17 00:00:00 2001 From: Kevin Lim Date: Thu, 24 Aug 2006 17:51:35 -0400 Subject: [PATCH 15/20] Stats updates. dev/ide_disk.cc: dev/ide_disk.hh: Add in stats. sim/stat_control.cc: sim/stat_control.hh: Allow setup event to be called with a specific queue. --HG-- extra : convert_revision : 9310b132b70f967a198cb2e646433f3a5332671e --- dev/ide_disk.cc | 33 +++++++++++++++++++++++++++++++++ dev/ide_disk.hh | 4 ++++ sim/stat_control.cc | 13 ++++++++----- sim/stat_control.hh | 4 +++- 4 files changed, 48 insertions(+), 6 deletions(-) diff --git a/dev/ide_disk.cc b/dev/ide_disk.cc index c13556ed6..701d3bf7d 100644 --- a/dev/ide_disk.cc +++ b/dev/ide_disk.cc @@ -406,6 +406,39 @@ IdeDisk::regStats() .name(name() + ".dma_write_txs") .desc("Number of DMA write transactions.") ; + + rdBandwidth + .name(name() + ".rdBandwidth") + .desc("Read Bandwidth (bits/s)") + .precision(0) + .prereq(dmaReadBytes) + ; + + wrBandwidth + .name(name() + ".wrBandwidth") + .desc("Write Bandwidth (bits/s)") + .precision(0) + .prereq(dmaWriteBytes) + ; + + totBandwidth + .name(name() + ".totBandwidth") + .desc("Total Bandwidth (bits/s)") + .precision(0) + .prereq(totBytes) + ; + + totBytes + .name(name() + ".totBytes") + .desc("Total Bytes") + .precision(0) + .prereq(totBytes) + ; + + rdBandwidth = dmaReadBytes * Stats::constant(8) / simSeconds; + wrBandwidth = dmaWriteBytes * Stats::constant(8) / simSeconds; + totBandwidth = rdBandwidth + wrBandwidth; + totBytes = dmaReadBytes + dmaWriteBytes; } void diff --git a/dev/ide_disk.hh b/dev/ide_disk.hh index 402ae44ee..91ea33f4a 100644 --- a/dev/ide_disk.hh +++ b/dev/ide_disk.hh @@ -244,6 +244,10 @@ class IdeDisk : public SimObject Stats::Scalar<> dmaWriteFullPages; Stats::Scalar<> dmaWriteBytes; Stats::Scalar<> dmaWriteTxs; + Stats::Formula rdBandwidth; + Stats::Formula wrBandwidth; + Stats::Formula totBandwidth; + Stats::Formula totBytes; public: /** diff --git a/sim/stat_control.cc b/sim/stat_control.cc index e4394cfa3..33b3ccdb6 100644 --- a/sim/stat_control.cc +++ b/sim/stat_control.cc @@ -158,13 +158,13 @@ class StatEvent : public Event Tick repeat; public: - StatEvent(int _flags, Tick _when, Tick _repeat); + StatEvent(EventQueue *queue, int _flags, Tick _when, Tick _repeat); virtual void process(); virtual const char *description(); }; -StatEvent::StatEvent(int _flags, Tick _when, Tick _repeat) - : Event(&mainEventQueue, Stat_Event_Pri), +StatEvent::StatEvent(EventQueue *queue, int _flags, Tick _when, Tick _repeat) + : Event(queue, Stat_Event_Pri), flags(_flags), repeat(_repeat) { setFlags(AutoDelete); @@ -214,9 +214,12 @@ DumpNow() } void -SetupEvent(int flags, Tick when, Tick repeat) +SetupEvent(int flags, Tick when, Tick repeat, EventQueue *queue) { - new StatEvent(flags, when, repeat); + if (queue == NULL) + queue = &mainEventQueue; + + new StatEvent(queue, flags, when, repeat); } /* namespace Stats */ } diff --git a/sim/stat_control.hh b/sim/stat_control.hh index a22ce76af..806c4be6b 100644 --- a/sim/stat_control.hh +++ b/sim/stat_control.hh @@ -32,6 +32,8 @@ #include #include +class EventQueue; + namespace Stats { enum { @@ -43,7 +45,7 @@ class Output; extern std::list OutputList; void DumpNow(); -void SetupEvent(int flags, Tick when, Tick repeat = 0); +void SetupEvent(int flags, Tick when, Tick repeat = 0, EventQueue *queue = NULL); void InitSimStats(); From 65741cd048933214df43982979079fccfffb3fce Mon Sep 17 00:00:00 2001 From: Kevin Lim Date: Thu, 24 Aug 2006 18:01:07 -0400 Subject: [PATCH 16/20] Updates to configs to support various sampling forms, truncated execution forms. --HG-- extra : convert_revision : a6cf77f6c902e5f4f0a96206093d123eec2e0167 --- configs/boot/ammp.rcS | 12 + configs/boot/ammp.symbol | 257 +++ configs/boot/art.rcS | 7 + configs/boot/bonnie.symbol | 309 ++++ configs/boot/bzip.rcS | 6 + configs/boot/cc1.symbol | 3454 ++++++++++++++++++++++++++++++++++++ configs/boot/equake.rcS | 12 + configs/boot/equake.symbol | 94 + configs/boot/gcc.rcS | 12 + configs/boot/gzip.rcS | 12 + configs/boot/gzip.symbol | 268 +++ configs/boot/mcf.rcS | 12 + configs/boot/mcf.symbol | 65 + configs/boot/mesa.rcS | 12 + configs/boot/mesa.symbol | 1135 ++++++++++++ 15 files changed, 5667 insertions(+) create mode 100644 configs/boot/ammp.rcS create mode 100644 configs/boot/ammp.symbol create mode 100644 configs/boot/art.rcS create mode 100644 configs/boot/bonnie.symbol create mode 100644 configs/boot/bzip.rcS create mode 100644 configs/boot/cc1.symbol create mode 100644 configs/boot/equake.rcS create mode 100644 configs/boot/equake.symbol create mode 100644 configs/boot/gcc.rcS create mode 100644 configs/boot/gzip.rcS create mode 100644 configs/boot/gzip.symbol create mode 100644 configs/boot/mcf.rcS create mode 100644 configs/boot/mcf.symbol create mode 100644 configs/boot/mesa.rcS create mode 100644 configs/boot/mesa.symbol diff --git a/configs/boot/ammp.rcS b/configs/boot/ammp.rcS new file mode 100644 index 000000000..485244c3c --- /dev/null +++ b/configs/boot/ammp.rcS @@ -0,0 +1,12 @@ +#!/bin/sh + +cd /benchmarks/spec/ammp00/ + +/sbin/m5 checkpoint 0 0 +/sbin/m5 checkpoint 100000000 200000000 + +/sbin/m5 loadsymbol + +/sbin/m5 resetstats +./ammp < input/mdred.in +/sbin/m5 exit diff --git a/configs/boot/ammp.symbol b/configs/boot/ammp.symbol new file mode 100644 index 000000000..93ef40555 --- /dev/null +++ b/configs/boot/ammp.symbol @@ -0,0 +1,257 @@ +000000012001da40 T AMMPmonitor +000000012001dfc0 T AMMPmonitor_mute +0000000120034338 D _DYNAMIC +00000001200346c8 D _GLOBAL_OFFSET_TABLE_ +0000000120034d60 G _IO_stdin_used +0000000120034500 T _PROCEDURE_LINKAGE_TABLE_ +00000001200344e0 d __CTOR_END__ +00000001200344d8 d __CTOR_LIST__ +00000001200344f0 d __DTOR_END__ +00000001200344e8 d __DTOR_LIST__ +0000000120034334 r __FRAME_END__ +00000001200344f8 d __JCR_END__ +00000001200344f8 d __JCR_LIST__ +0000000120034da0 A __bss_start +00000001200328c8 D __data_start +0000000120020c40 t __do_global_ctors_aux +0000000120001090 t __do_global_dtors_aux +0000000120034d68 G __dso_handle +00000001200328c8 A __fini_array_end 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smvp +00000001200070f8 T smvp_opt +000000012001a880 S source_elms +000000012001a8e0 S vel +000000012000561c T vv12x12 diff --git a/configs/boot/gcc.rcS b/configs/boot/gcc.rcS new file mode 100644 index 000000000..6bcd7e03d --- /dev/null +++ b/configs/boot/gcc.rcS @@ -0,0 +1,12 @@ +#!/bin/sh + +cd /benchmarks/spec/gcc00/ + +/sbin/m5 checkpoint 0 0 +/sbin/m5 checkpoint 100000000 200000000 + +/sbin/m5 loadsymbol + +/sbin/m5 resetstats +./cc1 mdred.rtlanal.i +/sbin/m5 exit diff --git a/configs/boot/gzip.rcS b/configs/boot/gzip.rcS new file mode 100644 index 000000000..c7aca7e9b --- /dev/null +++ b/configs/boot/gzip.rcS @@ -0,0 +1,12 @@ +#!/bin/sh + +cd /benchmarks/spec/gzip00/ + +/sbin/m5 checkpoint 0 0 +/sbin/m5 checkpoint 100000000 200000000 + +/sbin/m5 loadsymbol + +/sbin/m5 resetstats +./gzip lgred.log 1 +/sbin/m5 exit diff --git a/configs/boot/gzip.symbol b/configs/boot/gzip.symbol new file mode 100644 index 000000000..d965c99a9 --- /dev/null +++ b/configs/boot/gzip.symbol @@ -0,0 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z_suffix +0000000120023504 s zfile +000000012000ef80 T zip diff --git a/configs/boot/mcf.rcS b/configs/boot/mcf.rcS new file mode 100644 index 000000000..864966dfc --- /dev/null +++ b/configs/boot/mcf.rcS @@ -0,0 +1,12 @@ +#!/bin/sh + +cd /benchmarks/spec/mcf00/ + +/sbin/m5 checkpoint 0 0 +/sbin/m5 checkpoint 100000000 200000000 + +/sbin/m5 loadsymbol + +/sbin/m5 resetstats +/benchmarks/spec/mcf00/mcf mdred.in +/sbin/m5 exit diff --git a/configs/boot/mcf.symbol b/configs/boot/mcf.symbol new file mode 100644 index 000000000..878f12961 --- /dev/null +++ b/configs/boot/mcf.symbol @@ -0,0 +1,65 @@ +0000000120014350 D _DYNAMIC +0000000120014608 D _GLOBAL_OFFSET_TABLE_ +0000000120014770 G _IO_stdin_used +0000000120014518 T _PROCEDURE_LINKAGE_TABLE_ +00000001200144f8 d __CTOR_END__ +00000001200144f0 d __CTOR_LIST__ +0000000120014508 d __DTOR_END__ +0000000120014500 d __DTOR_LIST__ +000000012001434c r __FRAME_END__ +0000000120014510 d __JCR_END__ +0000000120014510 d __JCR_LIST__ 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sample_lambda_2d +000000012007e680 t sample_lambda_3d +000000012007ccb0 t sample_linear_1d +000000012007d700 t sample_linear_2d +000000012007e5a0 t sample_linear_3d +000000012007cbf0 t sample_nearest_1d +000000012007d630 t sample_nearest_2d +000000012007e4c0 t sample_nearest_3d +000000012004fbb0 t select_line +0000000120067950 t select_points +0000000120083f60 t select_triangle +000000012005ef50 t set_buffer +000000012005f300 t set_color +000000012005f2f0 t set_index +0000000120096f30 t shade_vertices +0000000120086820 t simple_textured_triangle +0000000120087250 t simple_z_textured_triangle +0000000120067280 T size1_ci_points +0000000120067a30 t size1_rgba_points +0000000120050960 t smooth_ci_line +0000000120084850 t smooth_ci_triangle +0000000120050bc0 t smooth_ci_z_line +0000000120060460 t smooth_color_z_triangle +0000000120050f00 t smooth_rgba_line +0000000120085a20 t smooth_rgba_triangle +00000001200513f0 t smooth_rgba_z_line +0000000120056630 t smooth_textured_line +00000001200b9de8 b sqrttab +00000001200affa0 d texPlane.0 +0000000120078040 t texture_1d_error_check +0000000120078250 t texture_2d_error_check +00000001200784a0 t texture_3d_error_check +00000001200683e0 t textured_rgba_points +00000001200b9618 b tmp +0000000120095830 t transform_points3 +0000000120095c40 t transform_points4 +00000001200960b0 t transform_texcoords +000000012002fc50 t translate_id +0000000120095020 t unfilled_polygon +000000012001e720 t update_clipmask +0000000120097630 t update_material +000000012001e320 t update_pixel_logic +000000012001e3f0 t update_pixel_masking +000000012001e520 t update_rasterflags +0000000120096b10 t userclip_vertices +00000001200b93b8 g vendor.1 +00000001200b93c0 g version.2 +00000001200916b0 t vertex2f_color +0000000120091500 t vertex2f_color_tex2 +00000001200915d0 t vertex2f_color_tex4 +0000000120090b20 t vertex2f_feedback +0000000120091770 t vertex2f_index +0000000120091440 t vertex2f_normal +0000000120091250 t vertex2f_normal_color_tex2 +0000000120091340 t vertex2f_normal_color_tex4 +00000001200910d0 t vertex3f_color +0000000120090f20 t vertex3f_color_tex2 +0000000120090ff0 t vertex3f_color_tex4 +0000000120090b00 t vertex3f_feedback +0000000120091190 t vertex3f_index +0000000120090e60 t vertex3f_normal +0000000120090c70 t vertex3f_normal_color_tex2 +0000000120090d60 t vertex3f_normal_color_tex4 +0000000120091ce0 t vertex3fv_color +0000000120091b10 t vertex3fv_color_tex2 +0000000120091bf0 t vertex3fv_color_tex4 +0000000120090b40 t vertex3fv_feedback +0000000120091db0 t vertex3fv_index +0000000120091a40 t vertex3fv_normal +0000000120091830 t vertex3fv_normal_color_tex2 +0000000120091930 t vertex3fv_normal_color_tex4 +0000000120090b60 t vertex4 +00000001200909f0 t vertex4f_feedback +0000000120096c50 t viewport_map_vertices +00000001200affc0 d white.2 +000000012005f520 t write_color_pixels +000000012005fde0 t write_color_pixels3 +000000012005f360 t write_color_span +000000012005fb50 t write_color_span3 +000000012003c8c0 t write_hit_record +000000012005f780 t write_index_pixels +000000012005f6a0 t write_index_span +000000012005f630 t write_monocolor_pixels +000000012005fef0 t write_monocolor_pixels3 +000000012005f4d0 t write_monocolor_span +000000012005fcf0 t write_monocolor_span3 +000000012005f810 t write_monoindex_pixels +000000012005f710 t write_monoindex_span From 51f19f2e28a30054d4a9cc06b059b602e17e504f Mon Sep 17 00:00:00 2001 From: Kevin Lim Date: Thu, 28 Sep 2006 00:09:27 -0400 Subject: [PATCH 17/20] Minor changes plus updates to O3. cpu/base.cc: Have output message regardless of build. cpu/checker/cpu_builder.cc: cpu/checker/o3_cpu_builder.cc: Be sure to include all parameters. cpu/o3/cpu.cc: IEW also needs to switch out. cpu/o3/iew_impl.hh: Handle stores with faults properly. cpu/o3/inst_queue_impl.hh: Switch out properly, handle squashing properly. cpu/o3/lsq_unit_impl.hh: Minor fixes. cpu/o3/mem_dep_unit_impl.hh: Make sure mem dep unit is switched out properly. cpu/o3/rename_impl.hh: Switch out fix. --HG-- extra : convert_revision : b94deb83f724225c01166c84a1b3fdd3543cbe9a --- cpu/base.cc | 8 +++-- cpu/checker/cpu_builder.cc | 1 + cpu/checker/o3_cpu_builder.cc | 6 ++++ cpu/o3/cpu.cc | 1 + cpu/o3/iew_impl.hh | 18 +++++++++-- cpu/o3/inst_queue_impl.hh | 21 +++++++++--- cpu/o3/lsq_unit_impl.hh | 61 +++++------------------------------ cpu/o3/mem_dep_unit_impl.hh | 3 ++ cpu/o3/rename_impl.hh | 5 +++ 9 files changed, 61 insertions(+), 63 deletions(-) diff --git a/cpu/base.cc b/cpu/base.cc index 044fafca9..d4ba8c812 100644 --- a/cpu/base.cc +++ b/cpu/base.cc @@ -60,15 +60,19 @@ int maxThreadsPerCPU = 1; void CPUProgressEvent::process() { -#ifndef NDEBUG Counter temp = cpu->totalInstructions(); +#ifndef NDEBUG double ipc = double(temp - lastNumInst) / (interval / cpu->cycles(1)); + DPRINTFN("%s progress event, instructions committed: %lli, IPC: %0.8d\n", cpu->name(), temp - lastNumInst, ipc); ipc = 0.0; +#else + cprintf("%lli: %s progress event, instructions committed: %lli\n", + curTick, cpu->name(), temp - lastNumInst); +#endif lastNumInst = temp; schedule(curTick + interval); -#endif } const char * diff --git a/cpu/checker/cpu_builder.cc b/cpu/checker/cpu_builder.cc index ec36ae09f..d68dcdcd9 100644 --- a/cpu/checker/cpu_builder.cc +++ b/cpu/checker/cpu_builder.cc @@ -144,6 +144,7 @@ CREATE_SIM_OBJECT(OzoneChecker) temp = max_insts_all_threads; temp = max_loads_any_thread; temp = max_loads_all_threads; + temp = stats_reset_inst; Tick temp2 = progress_interval; temp2++; params->progress_interval = 0; diff --git a/cpu/checker/o3_cpu_builder.cc b/cpu/checker/o3_cpu_builder.cc index 496cca779..079217b0c 100644 --- a/cpu/checker/o3_cpu_builder.cc +++ b/cpu/checker/o3_cpu_builder.cc @@ -58,6 +58,7 @@ BEGIN_DECLARE_SIM_OBJECT_PARAMS(O3Checker) Param max_insts_all_threads; Param max_loads_any_thread; Param max_loads_all_threads; + Param stats_reset_inst; Param progress_interval; #if FULL_SYSTEM @@ -92,6 +93,8 @@ BEGIN_INIT_SIM_OBJECT_PARAMS(O3Checker) "terminate when any thread reaches this load count"), INIT_PARAM(max_loads_all_threads, "terminate when all threads have reached this load count"), + INIT_PARAM(stats_reset_inst, + "blah"), INIT_PARAM_DFLT(progress_interval, "CPU Progress Interval", 0), #if FULL_SYSTEM @@ -127,6 +130,7 @@ CREATE_SIM_OBJECT(O3Checker) params->max_insts_all_threads = 0; params->max_loads_any_thread = 0; params->max_loads_all_threads = 0; + params->stats_reset_inst = 0; params->exitOnError = exitOnError; params->updateOnError = updateOnError; params->deferRegistration = defer_registration; @@ -140,7 +144,9 @@ CREATE_SIM_OBJECT(O3Checker) temp = max_insts_all_threads; temp = max_loads_any_thread; temp = max_loads_all_threads; + temp = stats_reset_inst; Tick temp2 = progress_interval; + params->progress_interval = 0; temp2++; BaseMem *cache = icache; cache = dcache; diff --git a/cpu/o3/cpu.cc b/cpu/o3/cpu.cc index 88de6c746..21cd1c599 100644 --- a/cpu/o3/cpu.cc +++ b/cpu/o3/cpu.cc @@ -697,6 +697,7 @@ FullO3CPU::signalSwitched() if (++switchCount == NumStages) { fetch.doSwitchOut(); rename.doSwitchOut(); + iew.doSwitchOut(); commit.doSwitchOut(); instList.clear(); diff --git a/cpu/o3/iew_impl.hh b/cpu/o3/iew_impl.hh index 102be4f8d..33fd0f6b9 100644 --- a/cpu/o3/iew_impl.hh +++ b/cpu/o3/iew_impl.hh @@ -431,6 +431,8 @@ DefaultIEW::doSwitchOut() { // Clear any state. switchedOut = true; + assert(insts[0].empty()); + assert(skidBuffer[0].empty()); instQueue.switchOut(); ldstQueue.switchOut(); @@ -1281,13 +1283,23 @@ DefaultIEW::executeInsts() // event adds the instruction to the queue to commit fault = ldstQueue.executeLoad(inst); } else if (inst->isStore()) { - ldstQueue.executeStore(inst); + fault = ldstQueue.executeStore(inst); // If the store had a fault then it may not have a mem req - if (inst->req && !(inst->req->flags & LOCKED)) { + if (!inst->isStoreConditional() && fault == NoFault) { inst->setExecuted(); instToCommit(inst); + } else if (fault != NoFault) { + // If the instruction faulted, then we need to send it along to commit + // without the instruction completing. + + // Send this instruction to commit, also make sure iew stage + // realizes there is activity. + inst->setExecuted(); + + instToCommit(inst); + activityThisCycle(); } // Store conditionals will mark themselves as @@ -1408,7 +1420,7 @@ DefaultIEW::writebackInsts() // E.g. Uncached loads have not actually executed when they // are first sent to commit. Instead commit must tell the LSQ // when it's ready to execute the uncached load. - if (!inst->isSquashed() && inst->isExecuted()) { + if (!inst->isSquashed() && inst->isExecuted() && inst->getFault() == NoFault) { int dependents = instQueue.wakeDependents(inst); for (int i = 0; i < inst->numDestRegs(); i++) { diff --git a/cpu/o3/inst_queue_impl.hh b/cpu/o3/inst_queue_impl.hh index b6b06ca77..0a17cae5c 100644 --- a/cpu/o3/inst_queue_impl.hh +++ b/cpu/o3/inst_queue_impl.hh @@ -386,8 +386,16 @@ template void InstructionQueue::switchOut() { +/* + if (!instList[0].empty() || (numEntries != freeEntries) || + !readyInsts[0].empty() || !nonSpecInsts.empty() || !listOrder.empty()) { + dumpInsts(); +// assert(0); + } +*/ resetState(); dependGraph.reset(); + instsToExecute.clear(); switchedOut = true; for (int i = 0; i < numThreads; ++i) { memDepUnit[i].switchOut(); @@ -643,9 +651,12 @@ template void InstructionQueue::processFUCompletion(DynInstPtr &inst, int fu_idx) { + DPRINTF(IQ, "Processing FU completion [sn:%lli]\n", inst->seqNum); // The CPU could have been sleeping until this op completed (*extremely* // long latency op). Wake it if it was. This may be overkill. if (isSwitchedOut()) { + DPRINTF(IQ, "FU completion not processed, IQ is switched out [sn:%lli]\n", + inst->seqNum); return; } @@ -1033,6 +1044,10 @@ InstructionQueue::doSquash(unsigned tid) (squashed_inst->isMemRef() && !squashed_inst->memOpDone)) { + DPRINTF(IQ, "[tid:%i]: Instruction [sn:%lli] PC %#x " + "squashed.\n", + tid, squashed_inst->seqNum, squashed_inst->readPC()); + // Remove the instruction from the dependency list. if (!squashed_inst->isNonSpeculative() && !squashed_inst->isStoreConditional() && @@ -1063,7 +1078,7 @@ InstructionQueue::doSquash(unsigned tid) ++iqSquashedOperandsExamined; } - } else { + } else if (!squashed_inst->isStoreConditional() || !squashed_inst->isCompleted()) { NonSpecMapIt ns_inst_it = nonSpecInsts.find(squashed_inst->seqNum); assert(ns_inst_it != nonSpecInsts.end()); @@ -1090,10 +1105,6 @@ InstructionQueue::doSquash(unsigned tid) count[squashed_inst->threadNumber]--; ++freeEntries; - - DPRINTF(IQ, "[tid:%i]: Instruction [sn:%lli] PC %#x " - "squashed.\n", - tid, squashed_inst->seqNum, squashed_inst->readPC()); } instList[tid].erase(squash_it--); diff --git a/cpu/o3/lsq_unit_impl.hh b/cpu/o3/lsq_unit_impl.hh index 7086c381e..f75a41cfe 100644 --- a/cpu/o3/lsq_unit_impl.hh +++ b/cpu/o3/lsq_unit_impl.hh @@ -198,62 +198,12 @@ void LSQUnit::switchOut() { switchedOut = true; - for (int i = 0; i < loadQueue.size(); ++i) + for (int i = 0; i < loadQueue.size(); ++i) { + assert(!loadQueue[i]); loadQueue[i] = NULL; + } assert(storesToWB == 0); - - while (storesToWB > 0 && - storeWBIdx != storeTail && - storeQueue[storeWBIdx].inst && - storeQueue[storeWBIdx].canWB) { - - if (storeQueue[storeWBIdx].size == 0 || - storeQueue[storeWBIdx].inst->isDataPrefetch() || - storeQueue[storeWBIdx].committed || - storeQueue[storeWBIdx].req->flags & LOCKED) { - incrStIdx(storeWBIdx); - - continue; - } - - assert(storeQueue[storeWBIdx].req); - assert(!storeQueue[storeWBIdx].committed); - - MemReqPtr req = storeQueue[storeWBIdx].req; - storeQueue[storeWBIdx].committed = true; - - req->cmd = Write; - req->completionEvent = NULL; - req->time = curTick; - assert(!req->data); - req->data = new uint8_t[64]; - memcpy(req->data, (uint8_t *)&storeQueue[storeWBIdx].data, req->size); - - DPRINTF(LSQUnit, "D-Cache: Writing back store idx:%i PC:%#x " - "to Addr:%#x, data:%#x [sn:%lli]\n", - storeWBIdx,storeQueue[storeWBIdx].inst->readPC(), - req->paddr, *(req->data), - storeQueue[storeWBIdx].inst->seqNum); - - switch(storeQueue[storeWBIdx].size) { - case 1: - cpu->write(req, (uint8_t &)storeQueue[storeWBIdx].data); - break; - case 2: - cpu->write(req, (uint16_t &)storeQueue[storeWBIdx].data); - break; - case 4: - cpu->write(req, (uint32_t &)storeQueue[storeWBIdx].data); - break; - case 8: - cpu->write(req, (uint64_t &)storeQueue[storeWBIdx].data); - break; - default: - panic("Unexpected store size!\n"); - } - incrStIdx(storeWBIdx); - } } template @@ -439,6 +389,11 @@ LSQUnit::executeLoad(DynInstPtr &inst) if (load_fault != NoFault) { // Send this instruction to commit, also make sure iew stage // realizes there is activity. + // Mark it as executed unless it is an uncached load that + // needs to hit the head of commit. + if (!(inst->req->flags & UNCACHEABLE) || inst->isAtCommit()) { + inst->setExecuted(); + } iewStage->instToCommit(inst); iewStage->activityThisCycle(); } diff --git a/cpu/o3/mem_dep_unit_impl.hh b/cpu/o3/mem_dep_unit_impl.hh index bfe694bd8..a2d04ece9 100644 --- a/cpu/o3/mem_dep_unit_impl.hh +++ b/cpu/o3/mem_dep_unit_impl.hh @@ -107,6 +107,9 @@ template void MemDepUnit::switchOut() { + assert(instList[0].empty()); + assert(instsToReplay.empty()); + assert(memDepHash.empty()); // Clear any state. for (int i = 0; i < Impl::MaxThreads; ++i) { instList[i].clear(); diff --git a/cpu/o3/rename_impl.hh b/cpu/o3/rename_impl.hh index 49627e3d4..a41e8d016 100644 --- a/cpu/o3/rename_impl.hh +++ b/cpu/o3/rename_impl.hh @@ -864,6 +864,11 @@ DefaultRename::doSquash(unsigned tid) // Put the renamed physical register back on the free list. freeList->addReg(hb_it->newPhysReg); + // Be sure to mark its register as ready if it's a misc register. + if (hb_it->newPhysReg >= maxPhysicalRegs) { + scoreboard->setReg(hb_it->newPhysReg); + } + historyBuffer[tid].erase(hb_it++); ++renameUndoneMaps; From 30b719fd768115bb26e848a02096350c11c1b0bd Mon Sep 17 00:00:00 2001 From: Kevin Lim Date: Thu, 28 Sep 2006 00:14:15 -0400 Subject: [PATCH 18/20] Updates to Ozone CPU. cpu/ozone/cpu_impl.hh: Be sure to update rename tables. cpu/ozone/front_end_impl.hh: Handle serialize instructions slightly differently. This allows front end to continue even if back end hasn't processed it yet. cpu/ozone/lw_back_end_impl.hh: Handle stores with faults properly. cpu/ozone/lw_lsq.hh: Handle committed stores properly. cpu/ozone/lw_lsq_impl.hh: Handle uncacheable loads properly. --HG-- extra : convert_revision : 093edc2eee890139a9962c97c938575e6d313f09 --- cpu/ozone/cpu_impl.hh | 2 ++ cpu/ozone/front_end_impl.hh | 34 ++++++++++++++++++++++------------ cpu/ozone/lw_back_end_impl.hh | 15 ++++++++++++--- cpu/ozone/lw_lsq.hh | 2 +- cpu/ozone/lw_lsq_impl.hh | 3 +++ 5 files changed, 40 insertions(+), 16 deletions(-) diff --git a/cpu/ozone/cpu_impl.hh b/cpu/ozone/cpu_impl.hh index 1a0de29f5..cd82e6d20 100644 --- a/cpu/ozone/cpu_impl.hh +++ b/cpu/ozone/cpu_impl.hh @@ -267,6 +267,8 @@ OzoneCPU::takeOverFrom(BaseCPU *oldCPU) backEnd->takeOverFrom(); frontEnd->takeOverFrom(); + frontEnd->renameTable.copyFrom(thread.renameTable); + backEnd->renameTable.copyFrom(thread.renameTable); assert(!tickEvent.scheduled()); #ifndef NDEBUG diff --git a/cpu/ozone/front_end_impl.hh b/cpu/ozone/front_end_impl.hh index 09fc2e2f8..959803aee 100644 --- a/cpu/ozone/front_end_impl.hh +++ b/cpu/ozone/front_end_impl.hh @@ -288,8 +288,8 @@ FrontEnd::tick() cacheBlkValid = true; status = Running; - if (barrierInst) - status = SerializeBlocked; +// if (barrierInst) +// status = SerializeBlocked; if (freeRegs <= 0) status = RenameBlocked; checkBE(); @@ -537,10 +537,10 @@ FrontEnd::processBarriers(DynInstPtr &inst) // Change status over to SerializeBlocked so that other stages know // what this is blocked on. - status = SerializeBlocked; +// status = SerializeBlocked; - barrierInst = inst; - return true; +// barrierInst = inst; +// return true; } else if ((inst->isStoreConditional() || inst->isSerializeAfter()) && !inst->isSerializeHandled()) { DPRINTF(FE, "Serialize after instruction encountered.\n"); @@ -647,12 +647,12 @@ FrontEnd::squash(const InstSeqNum &squash_num, const Addr &next_PC, DPRINTF(FE, "Squashing outstanding Icache miss.\n"); memReq = NULL; } - +/* if (status == SerializeBlocked) { assert(barrierInst->seqNum > squash_num); barrierInst = NULL; } - +*/ // Unless this squash originated from the front end, we're probably // in running mode now. // Actually might want to make this latency dependent. @@ -670,6 +670,15 @@ FrontEnd::getInst() DynInstPtr inst = feBuffer.front(); + if (inst->isSerializeBefore() || inst->isIprAccess()) { + DPRINTF(FE, "Back end is getting a serialize before inst\n"); + if (!backEnd->robEmpty()) { + DPRINTF(FE, "Rob is not empty yet, not returning inst\n"); + return NULL; + } + inst->clearSerializeBefore(); + } + feBuffer.pop_front(); --instBufferSize; @@ -740,11 +749,11 @@ FrontEnd::updateStatus() } if (status == BEBlocked && !be_block) { - if (barrierInst) { - status = SerializeBlocked; - } else { +// if (barrierInst) { +// status = SerializeBlocked; +// } else { status = Running; - } +// } ret_val = true; } return ret_val; @@ -766,6 +775,7 @@ template typename Impl::DynInstPtr FrontEnd::getInstFromCacheline() { +/* if (status == SerializeComplete) { DynInstPtr inst = barrierInst; status = Running; @@ -773,7 +783,7 @@ FrontEnd::getInstFromCacheline() inst->clearSerializeBefore(); return inst; } - +*/ InstSeqNum inst_seq; MachInst inst; // @todo: Fix this magic number used here to handle word offset (and diff --git a/cpu/ozone/lw_back_end_impl.hh b/cpu/ozone/lw_back_end_impl.hh index 9a6ad4c14..cbca34d68 100644 --- a/cpu/ozone/lw_back_end_impl.hh +++ b/cpu/ozone/lw_back_end_impl.hh @@ -952,8 +952,17 @@ LWBackEnd::executeInsts() if (inst->isLoad()) { LSQ.executeLoad(inst); } else if (inst->isStore()) { - LSQ.executeStore(inst); - if (inst->req && !(inst->req->flags & LOCKED)) { + Fault fault = LSQ.executeStore(inst); + + if (!inst->isStoreConditional() && fault == NoFault) { + inst->setExecuted(); + + instToCommit(inst); + } else if (fault != NoFault) { + // If the instruction faulted, then we need to send it along to commit + // without the instruction completing. + // Send this instruction to commit, also make sure iew stage + // realizes there is activity. inst->setExecuted(); instToCommit(inst); @@ -1114,7 +1123,7 @@ LWBackEnd::commitInst(int inst_num) // or store inst. Signal backwards that it should be executed. if (!inst->isExecuted()) { if (inst->isNonSpeculative() || - inst->isStoreConditional() || + (inst->isStoreConditional() && inst->getFault() == NoFault) || inst->isMemBarrier() || inst->isWriteBarrier()) { #if !FULL_SYSTEM diff --git a/cpu/ozone/lw_lsq.hh b/cpu/ozone/lw_lsq.hh index 07fd1aec5..310f8351b 100644 --- a/cpu/ozone/lw_lsq.hh +++ b/cpu/ozone/lw_lsq.hh @@ -486,7 +486,7 @@ OzoneLWLSQ::read(MemReqPtr &req, T &data, int load_idx) store_size = (*sq_it).size; - if (store_size == 0) { + if (store_size == 0 || (*sq_it).committed) { sq_it++; continue; } diff --git a/cpu/ozone/lw_lsq_impl.hh b/cpu/ozone/lw_lsq_impl.hh index c60884fc3..5ceb36518 100644 --- a/cpu/ozone/lw_lsq_impl.hh +++ b/cpu/ozone/lw_lsq_impl.hh @@ -335,6 +335,9 @@ OzoneLWLSQ::executeLoad(DynInstPtr &inst) // Actually probably want the oldest faulting load if (load_fault != NoFault) { DPRINTF(OzoneLSQ, "Load [sn:%lli] has a fault\n", inst->seqNum); + if (!(inst->req->flags & UNCACHEABLE && !inst->isAtCommit())) { + inst->setExecuted(); + } // Maybe just set it as can commit here, although that might cause // some other problems with sending traps to the ROB too quickly. be->instToCommit(inst); From 568fa11084413913c2917bb2981d22db5bb2f495 Mon Sep 17 00:00:00 2001 From: Kevin Lim Date: Mon, 2 Oct 2006 11:58:09 -0400 Subject: [PATCH 19/20] Updates to fix merge issues and bring almost everything up to working speed. Ozone CPU remains untested, but everything else compiles and runs. src/arch/alpha/isa_traits.hh: This got changed to the wrong version by accident. src/cpu/base.cc: Fix up progress event to not schedule itself if the interval is set to 0. src/cpu/base.hh: Fix up the CPU Progress Event to not print itself if it's set to 0. Also remove stats_reset_inst (something I added to m5 but isn't necessary here). src/cpu/base_dyn_inst.hh: src/cpu/checker/cpu.hh: Remove float variable of instResult; it's always held within the double part now. src/cpu/checker/cpu_impl.hh: Use thread and not cpuXC. src/cpu/o3/alpha/cpu_builder.cc: src/cpu/o3/checker_builder.cc: src/cpu/ozone/checker_builder.cc: src/cpu/ozone/cpu_builder.cc: src/python/m5/objects/BaseCPU.py: Remove stats_reset_inst. src/cpu/o3/commit_impl.hh: src/cpu/ozone/lw_back_end_impl.hh: Get TC, not XCProxy. src/cpu/o3/cpu.cc: Switch out updates from the version of m5 I have. Also remove serialize code that got added twice. src/cpu/o3/iew_impl.hh: src/cpu/o3/lsq_impl.hh: src/cpu/thread_state.hh: Remove code that was added twice. src/cpu/o3/lsq_unit.hh: Add back in stats that got lost in the merge. src/cpu/o3/lsq_unit_impl.hh: Use proper method to get flags. Also wake CPU if we're coming back from a cache miss. src/cpu/o3/thread_context_impl.hh: src/cpu/o3/thread_state.hh: Support profiling. src/cpu/ozone/cpu.hh: Update to use proper typename. src/cpu/ozone/cpu_impl.hh: src/cpu/ozone/dyn_inst_impl.hh: Updates for newmem. src/cpu/ozone/lw_lsq_impl.hh: Get flags correctly. src/cpu/ozone/thread_state.hh: Reorder constructor initialization, use tc. src/sim/pseudo_inst.cc: Allow for loading of symbol file. Be sure to use ThreadContext and not ExecContext. --HG-- extra : convert_revision : c5657f84155807475ab4a1e20d944bb6f0d79d94 --- src/arch/alpha/isa_traits.hh | 452 +++++++++++++----------------- src/cpu/base.cc | 15 +- src/cpu/base.hh | 5 +- src/cpu/base_dyn_inst.hh | 2 +- src/cpu/checker/cpu.hh | 2 +- src/cpu/checker/cpu_impl.hh | 13 +- src/cpu/o3/alpha/cpu_builder.cc | 5 - src/cpu/o3/checker_builder.cc | 5 - src/cpu/o3/commit_impl.hh | 2 +- src/cpu/o3/cpu.cc | 44 +-- src/cpu/o3/iew_impl.hh | 16 -- src/cpu/o3/lsq_impl.hh | 10 - src/cpu/o3/lsq_unit.hh | 13 + src/cpu/o3/lsq_unit_impl.hh | 3 +- src/cpu/o3/thread_context_impl.hh | 10 +- src/cpu/o3/thread_state.hh | 2 +- src/cpu/ozone/checker_builder.cc | 5 - src/cpu/ozone/cpu.hh | 5 +- src/cpu/ozone/cpu_builder.cc | 5 - src/cpu/ozone/cpu_impl.hh | 20 +- src/cpu/ozone/dyn_inst_impl.hh | 4 +- src/cpu/ozone/lw_back_end_impl.hh | 2 +- src/cpu/ozone/lw_lsq_impl.hh | 8 +- src/cpu/ozone/thread_state.hh | 4 +- src/cpu/thread_state.hh | 14 - src/python/m5/objects/BaseCPU.py | 2 - src/sim/pseudo_inst.cc | 6 +- 27 files changed, 273 insertions(+), 401 deletions(-) diff --git a/src/arch/alpha/isa_traits.hh b/src/arch/alpha/isa_traits.hh index c59d93238..4f439b8df 100644 --- a/src/arch/alpha/isa_traits.hh +++ b/src/arch/alpha/isa_traits.hh @@ -42,10 +42,190 @@ class StaticInstPtr; namespace AlphaISA { + using namespace LittleEndianGuest; - typedef uint32_t MachInst; - typedef uint64_t ExtMachInst; - typedef uint8_t RegIndex; + // These enumerate all the registers for dependence tracking. + enum DependenceTags { + // 0..31 are the integer regs 0..31 + // 32..63 are the FP regs 0..31, i.e. use (reg + FP_Base_DepTag) + FP_Base_DepTag = 40, + Ctrl_Base_DepTag = 72, + Fpcr_DepTag = 72, // floating point control register + Uniq_DepTag = 73, + Lock_Flag_DepTag = 74, + Lock_Addr_DepTag = 75, + IPR_Base_DepTag = 76 + }; + + StaticInstPtr decodeInst(ExtMachInst); + + // Alpha Does NOT have a delay slot + #define ISA_HAS_DELAY_SLOT 0 + + const Addr PageShift = 13; + const Addr PageBytes = ULL(1) << PageShift; + const Addr PageMask = ~(PageBytes - 1); + const Addr PageOffset = PageBytes - 1; + +#if FULL_SYSTEM + + //////////////////////////////////////////////////////////////////////// + // + // Translation stuff + // + + const Addr PteShift = 3; + const Addr NPtePageShift = PageShift - PteShift; + const Addr NPtePage = ULL(1) << NPtePageShift; + const Addr PteMask = NPtePage - 1; + + // User Virtual + const Addr USegBase = ULL(0x0); + const Addr USegEnd = ULL(0x000003ffffffffff); + + // Kernel Direct Mapped + const Addr K0SegBase = ULL(0xfffffc0000000000); + const Addr K0SegEnd = ULL(0xfffffdffffffffff); + + // Kernel Virtual + const Addr K1SegBase = ULL(0xfffffe0000000000); + const Addr K1SegEnd = ULL(0xffffffffffffffff); + + // For loading... XXX This maybe could be USegEnd?? --ali + const Addr LoadAddrMask = ULL(0xffffffffff); + + //////////////////////////////////////////////////////////////////////// + // + // Interrupt levels + // + enum InterruptLevels + { + INTLEVEL_SOFTWARE_MIN = 4, + INTLEVEL_SOFTWARE_MAX = 19, + + INTLEVEL_EXTERNAL_MIN = 20, + INTLEVEL_EXTERNAL_MAX = 34, + + INTLEVEL_IRQ0 = 20, + INTLEVEL_IRQ1 = 21, + INTINDEX_ETHERNET = 0, + INTINDEX_SCSI = 1, + INTLEVEL_IRQ2 = 22, + INTLEVEL_IRQ3 = 23, + + INTLEVEL_SERIAL = 33, + + NumInterruptLevels = INTLEVEL_EXTERNAL_MAX + }; + + + // EV5 modes + enum mode_type + { + mode_kernel = 0, // kernel + mode_executive = 1, // executive (unused by unix) + mode_supervisor = 2, // supervisor (unused by unix) + mode_user = 3, // user mode + mode_number // number of modes + }; + +#endif + +#if FULL_SYSTEM + //////////////////////////////////////////////////////////////////////// + // + // Internal Processor Reigsters + // + enum md_ipr_names + { + IPR_ISR = 0x100, // interrupt summary register + IPR_ITB_TAG = 0x101, // ITLB tag register + IPR_ITB_PTE = 0x102, // ITLB page table entry register + IPR_ITB_ASN = 0x103, // ITLB address space register + IPR_ITB_PTE_TEMP = 0x104, // ITLB page table entry temp register + IPR_ITB_IA = 0x105, // ITLB invalidate all register + IPR_ITB_IAP = 0x106, // ITLB invalidate all process register + IPR_ITB_IS = 0x107, // ITLB invalidate select register + IPR_SIRR = 0x108, // software interrupt request register + IPR_ASTRR = 0x109, // asynchronous system trap request register + IPR_ASTER = 0x10a, // asynchronous system trap enable register + IPR_EXC_ADDR = 0x10b, // exception address register + IPR_EXC_SUM = 0x10c, // exception summary register + IPR_EXC_MASK = 0x10d, // exception mask register + IPR_PAL_BASE = 0x10e, // PAL base address register + IPR_ICM = 0x10f, // instruction current mode + IPR_IPLR = 0x110, // interrupt priority level register + IPR_INTID = 0x111, // interrupt ID register + IPR_IFAULT_VA_FORM = 0x112, // formatted faulting virtual addr register + IPR_IVPTBR = 0x113, // virtual page table base register + IPR_HWINT_CLR = 0x115, // H/W interrupt clear register + IPR_SL_XMIT = 0x116, // serial line transmit register + IPR_SL_RCV = 0x117, // serial line receive register + IPR_ICSR = 0x118, // instruction control and status register + IPR_IC_FLUSH = 0x119, // instruction cache flush control + IPR_IC_PERR_STAT = 0x11a, // inst cache parity error status register + IPR_PMCTR = 0x11c, // performance counter register + + // PAL temporary registers... + // register meanings gleaned from osfpal.s source code + IPR_PALtemp0 = 0x140, // local scratch + IPR_PALtemp1 = 0x141, // local scratch + IPR_PALtemp2 = 0x142, // entUna + IPR_PALtemp3 = 0x143, // CPU specific impure area pointer + IPR_PALtemp4 = 0x144, // memory management temp + IPR_PALtemp5 = 0x145, // memory management temp + IPR_PALtemp6 = 0x146, // memory management temp + IPR_PALtemp7 = 0x147, // entIF + IPR_PALtemp8 = 0x148, // intmask + IPR_PALtemp9 = 0x149, // entSys + IPR_PALtemp10 = 0x14a, // ?? + IPR_PALtemp11 = 0x14b, // entInt + IPR_PALtemp12 = 0x14c, // entArith + IPR_PALtemp13 = 0x14d, // reserved for platform specific PAL + IPR_PALtemp14 = 0x14e, // reserved for platform specific PAL + IPR_PALtemp15 = 0x14f, // reserved for platform specific PAL + IPR_PALtemp16 = 0x150, // scratch / whami<7:0> / mces<4:0> + IPR_PALtemp17 = 0x151, // sysval + IPR_PALtemp18 = 0x152, // usp + IPR_PALtemp19 = 0x153, // ksp + IPR_PALtemp20 = 0x154, // PTBR + IPR_PALtemp21 = 0x155, // entMM + IPR_PALtemp22 = 0x156, // kgp + IPR_PALtemp23 = 0x157, // PCBB + + IPR_DTB_ASN = 0x200, // DTLB address space number register + IPR_DTB_CM = 0x201, // DTLB current mode register + IPR_DTB_TAG = 0x202, // DTLB tag register + IPR_DTB_PTE = 0x203, // DTLB page table entry register + IPR_DTB_PTE_TEMP = 0x204, // DTLB page table entry temporary register + + IPR_MM_STAT = 0x205, // data MMU fault status register + IPR_VA = 0x206, // fault virtual address register + IPR_VA_FORM = 0x207, // formatted virtual address register + IPR_MVPTBR = 0x208, // MTU virtual page table base register + IPR_DTB_IAP = 0x209, // DTLB invalidate all process register + IPR_DTB_IA = 0x20a, // DTLB invalidate all register + IPR_DTB_IS = 0x20b, // DTLB invalidate single register + IPR_ALT_MODE = 0x20c, // alternate mode register + IPR_CC = 0x20d, // cycle counter register + IPR_CC_CTL = 0x20e, // cycle counter control register + IPR_MCSR = 0x20f, // MTU control register + + IPR_DC_FLUSH = 0x210, + IPR_DC_PERR_STAT = 0x212, // Dcache parity error status register + IPR_DC_TEST_CTL = 0x213, // Dcache test tag control register + IPR_DC_TEST_TAG = 0x214, // Dcache test tag register + IPR_DC_TEST_TAG_TEMP = 0x215, // Dcache test tag temporary register + IPR_DC_MODE = 0x216, // Dcache mode register + IPR_MAF_MODE = 0x217, // miss address file mode register + + NumInternalProcRegs // number of IPR registers + }; +#else + const int NumInternalProcRegs = 0; +#endif + + // Constants Related to the number of registers const int NumIntArchRegs = 32; const int NumPALShadowRegs = 8; @@ -53,6 +233,15 @@ namespace AlphaISA // @todo: Figure out what this number really should be. const int NumMiscArchRegs = 32; + const int NumIntRegs = NumIntArchRegs + NumPALShadowRegs; + const int NumFloatRegs = NumFloatArchRegs; + const int NumMiscRegs = NumMiscArchRegs; + + const int TotalNumRegs = NumIntRegs + NumFloatRegs + + NumMiscRegs + NumInternalProcRegs; + + const int TotalDataRegs = NumIntRegs + NumFloatRegs; + // Static instruction parameters const int MaxInstSrcRegs = 3; const int MaxInstDestRegs = 2; @@ -76,270 +265,23 @@ namespace AlphaISA const int SyscallPseudoReturnReg = ArgumentReg4; const int SyscallSuccessReg = 19; - - const int LogVMPageSize = 13; // 8K bytes const int VMPageSize = (1 << LogVMPageSize); const int BranchPredAddrShiftAmt = 2; // instructions are 4-byte aligned + const int MachineBytes = 8; const int WordBytes = 4; const int HalfwordBytes = 2; const int ByteBytes = 1; - - const int NumIntRegs = NumIntArchRegs + NumPALShadowRegs; - const int NumFloatRegs = NumFloatArchRegs; - const int NumMiscRegs = NumMiscArchRegs; - - // These enumerate all the registers for dependence tracking. - enum DependenceTags { - // 0..31 are the integer regs 0..31 - // 32..63 are the FP regs 0..31, i.e. use (reg + FP_Base_DepTag) - FP_Base_DepTag = 40, - Ctrl_Base_DepTag = 72, - Fpcr_DepTag = 72, // floating point control register - Uniq_DepTag = 73, - Lock_Flag_DepTag = 74, - Lock_Addr_DepTag = 75, - IPR_Base_DepTag = 76 - }; - - typedef uint64_t IntReg; - typedef IntReg IntRegFile[NumIntRegs]; - - // floating point register file entry type - typedef union { - uint64_t q; - double d; - } FloatReg; - - typedef union { - uint64_t q[NumFloatRegs]; // integer qword view - double d[NumFloatRegs]; // double-precision floating point view - - void clear() - { bzero(d, sizeof(d)); } - } FloatRegFile; - -extern const Addr PageShift; -extern const Addr PageBytes; -extern const Addr PageMask; -extern const Addr PageOffset; - -// redirected register map, really only used for the full system case. -extern const int reg_redir[NumIntRegs]; - -#if FULL_SYSTEM - - typedef uint64_t InternalProcReg; - -#include "arch/alpha/isa_fullsys_traits.hh" - -#else - const int NumInternalProcRegs = 0; -#endif - - // control register file contents - typedef uint64_t MiscReg; - class MiscRegFile { - protected: - uint64_t fpcr; // floating point condition codes - uint64_t uniq; // process-unique register - bool lock_flag; // lock flag for LL/SC - Addr lock_addr; // lock address for LL/SC - - public: - MiscReg readReg(int misc_reg); - - //These functions should be removed once the simplescalar cpu model - //has been replaced. - int getInstAsid(); - int getDataAsid(); - - MiscReg readRegWithEffect(int misc_reg, Fault &fault, ExecContext *xc); - - Fault setReg(int misc_reg, const MiscReg &val); - - Fault setRegWithEffect(int misc_reg, const MiscReg &val, - ExecContext *xc); - - void serialize(std::ostream &os); - - void unserialize(Checkpoint *cp, const std::string §ion); - - void clear() - { - fpcr = uniq = 0; - lock_flag = 0; - lock_addr = 0; - } - -#if FULL_SYSTEM - protected: - InternalProcReg ipr[NumInternalProcRegs]; // Internal processor regs - - private: - MiscReg readIpr(int idx, Fault &fault, ExecContext *xc); - - Fault setIpr(int idx, uint64_t val, ExecContext *xc); - - void copyIprs(ExecContext *xc); -#endif - friend class RegFile; - }; - - const int TotalNumRegs = NumIntRegs + NumFloatRegs + - NumMiscRegs + NumInternalProcRegs; - - const int TotalDataRegs = NumIntRegs + NumFloatRegs; - - typedef union { - IntReg intreg; - FloatReg fpreg; - MiscReg ctrlreg; - } AnyReg; - - struct RegFile { - IntRegFile intRegFile; // (signed) integer register file - FloatRegFile floatRegFile; // floating point register file - MiscRegFile miscRegs; // control register file - Addr pc; // program counter - Addr npc; // next-cycle program counter - Addr nnpc; - -#if FULL_SYSTEM - int intrflag; // interrupt flag - inline int instAsid() - { return EV5::ITB_ASN_ASN(miscRegs.ipr[IPR_ITB_ASN]); } - inline int dataAsid() - { return EV5::DTB_ASN_ASN(miscRegs.ipr[IPR_DTB_ASN]); } -#endif // FULL_SYSTEM - - void serialize(std::ostream &os); - void unserialize(Checkpoint *cp, const std::string §ion); - - void clear() - { - bzero(intRegFile, sizeof(intRegFile)); - floatRegFile.clear(); - miscRegs.clear(); - } - }; - - static inline ExtMachInst makeExtMI(MachInst inst, const uint64_t &pc); - - StaticInstPtr decodeInst(ExtMachInst); - - // Alpha Does NOT have a delay slot - #define ISA_HAS_DELAY_SLOT 0 - // return a no-op instruction... used for instruction fetch faults - extern const ExtMachInst NoopMachInst; + // Alpha UNOP (ldq_u r31,0(r0)) + const ExtMachInst NoopMachInst = 0x2ffe0000; - enum annotes { - ANNOTE_NONE = 0, - // An impossible number for instruction annotations - ITOUCH_ANNOTE = 0xffffffff, - }; + // redirected register map, really only used for the full system case. + extern const int reg_redir[NumIntRegs]; - static inline bool isCallerSaveIntegerRegister(unsigned int reg) { - panic("register classification not implemented"); - return (reg >= 1 && reg <= 8 || reg >= 22 && reg <= 25 || reg == 27); - } - - static inline bool isCalleeSaveIntegerRegister(unsigned int reg) { - panic("register classification not implemented"); - return (reg >= 9 && reg <= 15); - } - - static inline bool isCallerSaveFloatRegister(unsigned int reg) { - panic("register classification not implemented"); - return false; - } - - static inline bool isCalleeSaveFloatRegister(unsigned int reg) { - panic("register classification not implemented"); - return false; - } - - static inline Addr alignAddress(const Addr &addr, - unsigned int nbytes) { - return (addr & ~(nbytes - 1)); - } - - // Instruction address compression hooks - static inline Addr realPCToFetchPC(const Addr &addr) { - return addr; - } - - static inline Addr fetchPCToRealPC(const Addr &addr) { - return addr; - } - - // the size of "fetched" instructions (not necessarily the size - // of real instructions for PISA) - static inline size_t fetchInstSize() { - return sizeof(MachInst); - } - - static inline MachInst makeRegisterCopy(int dest, int src) { - panic("makeRegisterCopy not implemented"); - return 0; - } - - // Machine operations - - void saveMachineReg(AnyReg &savereg, const RegFile ®_file, - int regnum); - - void restoreMachineReg(RegFile ®s, const AnyReg ®, - int regnum); - -#if 0 - static void serializeSpecialRegs(const Serializable::Proxy &proxy, - const RegFile ®s); - - static void unserializeSpecialRegs(const IniFile *db, - const std::string &category, - ConfigNode *node, - RegFile ®s); -#endif - - /** - * Function to insure ISA semantics about 0 registers. - * @param xc The execution context. - */ - template - void zeroRegisters(XC *xc); - - const Addr MaxAddr = (Addr)-1; - -#if !FULL_SYSTEM - static inline void setSyscallReturn(SyscallReturn return_value, RegFile *regs) - { - // check for error condition. Alpha syscall convention is to - // indicate success/failure in reg a3 (r19) and put the - // return value itself in the standard return value reg (v0). - if (return_value.successful()) { - // no error - regs->intRegFile[SyscallSuccessReg] = 0; - regs->intRegFile[ReturnValueReg] = return_value.value(); - } else { - // got an error, return details - regs->intRegFile[SyscallSuccessReg] = (IntReg) -1; - regs->intRegFile[ReturnValueReg] = -return_value.value(); - } - } -#endif - - void copyRegs(ExecContext *src, ExecContext *dest); - - void copyMiscRegs(ExecContext *src, ExecContext *dest); - -#if FULL_SYSTEM - void copyIprs(ExecContext *src, ExecContext *dest); -#endif }; #endif // __ARCH_ALPHA_ISA_TRAITS_HH__ diff --git a/src/cpu/base.cc b/src/cpu/base.cc index f00dad7d6..513dd7c55 100644 --- a/src/cpu/base.cc +++ b/src/cpu/base.cc @@ -60,6 +60,15 @@ vector BaseCPU::cpuList; // been initialized int maxThreadsPerCPU = 1; +CPUProgressEvent::CPUProgressEvent(EventQueue *q, Tick ival, + BaseCPU *_cpu) + : Event(q, Event::Stat_Event_Pri), interval(ival), + lastNumInst(0), cpu(_cpu) +{ + if (interval) + schedule(curTick + interval); +} + void CPUProgressEvent::process() { @@ -156,12 +165,6 @@ BaseCPU::BaseCPU(Params *p) p->max_loads_all_threads, *counter); } - if (p->stats_reset_inst != 0) { - Stats::SetupEvent(Stats::Reset, p->stats_reset_inst, 0, comInstEventQueue[0]); - cprintf("Stats reset event scheduled for %lli insts\n", - p->stats_reset_inst); - } - #if FULL_SYSTEM memset(interrupts, 0, sizeof(interrupts)); intstatus = 0; diff --git a/src/cpu/base.hh b/src/cpu/base.hh index 2a3fd9b56..e02527371 100644 --- a/src/cpu/base.hh +++ b/src/cpu/base.hh @@ -54,9 +54,7 @@ class CPUProgressEvent : public Event BaseCPU *cpu; public: - CPUProgressEvent(EventQueue *q, Tick ival, BaseCPU *_cpu) - : Event(q, Event::Stat_Event_Pri), interval(ival), lastNumInst(0), cpu(_cpu) - { schedule(curTick + interval); } + CPUProgressEvent(EventQueue *q, Tick ival, BaseCPU *_cpu); void process(); @@ -138,7 +136,6 @@ class BaseCPU : public MemObject Counter max_insts_all_threads; Counter max_loads_any_thread; Counter max_loads_all_threads; - Counter stats_reset_inst; Tick clock; bool functionTrace; Tick functionTraceStart; diff --git a/src/cpu/base_dyn_inst.hh b/src/cpu/base_dyn_inst.hh index 926bfcbb2..c68810954 100644 --- a/src/cpu/base_dyn_inst.hh +++ b/src/cpu/base_dyn_inst.hh @@ -409,7 +409,7 @@ class BaseDynInst : public FastAlloc, public RefCounted void setFloatReg(const StaticInst *si, int idx, FloatReg val, int width) { if (width == 32) - instResult.fp = val; + instResult.dbl = (double)val; else if (width == 64) instResult.dbl = val; else diff --git a/src/cpu/checker/cpu.hh b/src/cpu/checker/cpu.hh index 737b4b5d4..00b01171f 100644 --- a/src/cpu/checker/cpu.hh +++ b/src/cpu/checker/cpu.hh @@ -258,7 +258,7 @@ class CheckerCPU : public BaseCPU thread->setFloatReg(reg_idx, val, width); switch(width) { case 32: - result.fp = val; + result.dbl = (double)val; break; case 64: result.dbl = val; diff --git a/src/cpu/checker/cpu_impl.hh b/src/cpu/checker/cpu_impl.hh index 3bb81c4b9..8aec79754 100644 --- a/src/cpu/checker/cpu_impl.hh +++ b/src/cpu/checker/cpu_impl.hh @@ -403,19 +403,20 @@ Checker::validateState() warn("%lli: Instruction PC %#x results didn't match up, copying all " "registers from main CPU", curTick, unverifiedInst->readPC()); // Heavy-weight copying of all registers - cpuXC->copyArchRegs(unverifiedInst->xcBase()); + thread->copyArchRegs(unverifiedInst->tcBase()); // Also advance the PC. Hopefully no PC-based events happened. #if THE_ISA != MIPS_ISA // go to the next instruction - cpuXC->setPC(cpuXC->readNextPC()); - cpuXC->setNextPC(cpuXC->readNextPC() + sizeof(MachInst)); + thread->setPC(thread->readNextPC()); + thread->setNextPC(thread->readNextPC() + sizeof(MachInst)); #else // go to the next instruction - cpuXC->setPC(cpuXC->readNextPC()); - cpuXC->setNextPC(cpuXC->readNextNPC()); - cpuXC->setNextNPC(cpuXC->readNextNPC() + sizeof(MachInst)); + thread->setPC(thread->readNextPC()); + thread->setNextPC(thread->readNextNPC()); + thread->setNextNPC(thread->readNextNPC() + sizeof(MachInst)); #endif updateThisCycle = false; + } } template diff --git a/src/cpu/o3/alpha/cpu_builder.cc b/src/cpu/o3/alpha/cpu_builder.cc index fbf1f342c..ff123a6f7 100644 --- a/src/cpu/o3/alpha/cpu_builder.cc +++ b/src/cpu/o3/alpha/cpu_builder.cc @@ -69,7 +69,6 @@ Param max_insts_any_thread; Param max_insts_all_threads; Param max_loads_any_thread; Param max_loads_all_threads; -Param stats_reset_inst; Param progress_interval; Param cachePorts; @@ -188,9 +187,6 @@ BEGIN_INIT_SIM_OBJECT_PARAMS(DerivO3CPU) "Terminate when all threads have reached this load" "count", 0), - INIT_PARAM_DFLT(stats_reset_inst, - "blah", - 0), INIT_PARAM_DFLT(progress_interval, "Progress interval", 0), INIT_PARAM_DFLT(cachePorts, "Cache Ports", 200), @@ -326,7 +322,6 @@ CREATE_SIM_OBJECT(DerivO3CPU) params->max_insts_all_threads = max_insts_all_threads; params->max_loads_any_thread = max_loads_any_thread; params->max_loads_all_threads = max_loads_all_threads; - params->stats_reset_inst = stats_reset_inst; params->progress_interval = progress_interval; // diff --git a/src/cpu/o3/checker_builder.cc b/src/cpu/o3/checker_builder.cc index ad83ec57a..02c817499 100644 --- a/src/cpu/o3/checker_builder.cc +++ b/src/cpu/o3/checker_builder.cc @@ -64,7 +64,6 @@ BEGIN_DECLARE_SIM_OBJECT_PARAMS(O3Checker) Param max_insts_all_threads; Param max_loads_any_thread; Param max_loads_all_threads; - Param stats_reset_inst; Param progress_interval; #if FULL_SYSTEM @@ -97,8 +96,6 @@ BEGIN_INIT_SIM_OBJECT_PARAMS(O3Checker) "terminate when any thread reaches this load count"), INIT_PARAM(max_loads_all_threads, "terminate when all threads have reached this load count"), - INIT_PARAM(stats_reset_inst, - "blah"), INIT_PARAM_DFLT(progress_interval, "CPU Progress Interval", 0), #if FULL_SYSTEM @@ -133,7 +130,6 @@ CREATE_SIM_OBJECT(O3Checker) params->max_insts_all_threads = 0; params->max_loads_any_thread = 0; params->max_loads_all_threads = 0; - params->stats_reset_inst = 0; params->exitOnError = exitOnError; params->updateOnError = updateOnError; params->warnOnlyOnLoadError = warnOnlyOnLoadError; @@ -148,7 +144,6 @@ CREATE_SIM_OBJECT(O3Checker) temp = max_insts_all_threads; temp = max_loads_any_thread; temp = max_loads_all_threads; - temp = stats_reset_inst; Tick temp2 = progress_interval; params->progress_interval = 0; temp2++; diff --git a/src/cpu/o3/commit_impl.hh b/src/cpu/o3/commit_impl.hh index 6ae01ae67..c80e4d8c1 100644 --- a/src/cpu/o3/commit_impl.hh +++ b/src/cpu/o3/commit_impl.hh @@ -1095,7 +1095,7 @@ DefaultCommit::commitHead(DynInstPtr &head_inst, unsigned inst_num) // (cpu->readMiscReg(AlphaISA::IPR_DTB_CM, tid) & 0x18) != 0; // thread[tid]->profilePC = usermode ? 1 : head_inst->readPC(); thread[tid]->profilePC = head_inst->readPC(); - ProfileNode *node = thread[tid]->profile->consume(thread[tid]->getXCProxy(), + ProfileNode *node = thread[tid]->profile->consume(thread[tid]->getTC(), head_inst->staticInst); if (node) diff --git a/src/cpu/o3/cpu.cc b/src/cpu/o3/cpu.cc index 4279df6f7..7386dfadd 100644 --- a/src/cpu/o3/cpu.cc +++ b/src/cpu/o3/cpu.cc @@ -795,7 +795,6 @@ unsigned int FullO3CPU::drain(Event *drain_event) { DPRINTF(O3CPU, "Switching out\n"); - BaseCPU::switchOut(_sampler); drainCount = 0; fetch.drain(); decode.drain(); @@ -852,6 +851,8 @@ FullO3CPU::signalDrained() changeState(SimObject::Drained); + BaseCPU::switchOut(); + if (drainEvent) { drainEvent->process(); drainEvent = NULL; @@ -878,6 +879,8 @@ FullO3CPU::switchOut() if (checker) checker->switchOut(); #endif + if (tickEvent.scheduled()) + tickEvent.squash(); } template @@ -934,45 +937,6 @@ FullO3CPU::takeOverFrom(BaseCPU *oldCPU) tickEvent.schedule(curTick); } -template -void -FullO3CPU::serialize(std::ostream &os) -{ - BaseCPU::serialize(os); - nameOut(os, csprintf("%s.tickEvent", name())); - tickEvent.serialize(os); - - // Use SimpleThread's ability to checkpoint to make it easier to - // write out the registers. Also make this static so it doesn't - // get instantiated multiple times (causes a panic in statistics). - static CPUExecContext temp; - - for (int i = 0; i < thread.size(); i++) { - nameOut(os, csprintf("%s.xc.%i", name(), i)); - temp.copyXC(thread[i]->getXCProxy()); - temp.serialize(os); - } -} - -template -void -FullO3CPU::unserialize(Checkpoint *cp, const std::string §ion) -{ - BaseCPU::unserialize(cp, section); - tickEvent.unserialize(cp, csprintf("%s.tickEvent", section)); - - // Use SimpleThread's ability to checkpoint to make it easier to - // read in the registers. Also make this static so it doesn't - // get instantiated multiple times (causes a panic in statistics). - static CPUExecContext temp; - - for (int i = 0; i < thread.size(); i++) { - temp.copyXC(thread[i]->getXCProxy()); - temp.unserialize(cp, csprintf("%s.xc.%i", section, i)); - thread[i]->getXCProxy()->copyArchRegs(temp.getProxy()); - } -} - template uint64_t FullO3CPU::readIntReg(int reg_idx) diff --git a/src/cpu/o3/iew_impl.hh b/src/cpu/o3/iew_impl.hh index c82f6dd21..b2baae296 100644 --- a/src/cpu/o3/iew_impl.hh +++ b/src/cpu/o3/iew_impl.hh @@ -904,22 +904,6 @@ DefaultIEW::emptyRenameInsts(unsigned tid) } } -template -void -DefaultIEW::emptyRenameInsts(unsigned tid) -{ - while (!insts[tid].empty()) { - if (insts[tid].front()->isLoad() || - insts[tid].front()->isStore() ) { - toRename->iewInfo[tid].dispatchedToLSQ++; - } - - toRename->iewInfo[tid].dispatched++; - - insts[tid].pop(); - } -} - template void DefaultIEW::wakeCPU() diff --git a/src/cpu/o3/lsq_impl.hh b/src/cpu/o3/lsq_impl.hh index a1ac5adb8..2bbab71f0 100644 --- a/src/cpu/o3/lsq_impl.hh +++ b/src/cpu/o3/lsq_impl.hh @@ -165,16 +165,6 @@ LSQ::regStats() } } -template -void -LSQ::regStats() -{ - //Initialize LSQs - for (int tid=0; tid < numThreads; tid++) { - thread[tid].regStats(); - } -} - template void LSQ::setActiveThreads(std::list *at_ptr) diff --git a/src/cpu/o3/lsq_unit.hh b/src/cpu/o3/lsq_unit.hh index 8537e9dd7..90d1a3d53 100644 --- a/src/cpu/o3/lsq_unit.hh +++ b/src/cpu/o3/lsq_unit.hh @@ -410,6 +410,19 @@ class LSQUnit { /** Total number of loads forwaded from LSQ stores. */ Stats::Scalar<> lsqForwLoads; + /** Total number of loads ignored due to invalid addresses. */ + Stats::Scalar<> invAddrLoads; + + /** Total number of squashed loads. */ + Stats::Scalar<> lsqSquashedLoads; + + /** Total number of responses from the memory system that are + * ignored due to the instruction already being squashed. */ + Stats::Scalar<> lsqIgnoredResponses; + + /** Tota number of memory ordering violations. */ + Stats::Scalar<> lsqMemOrderViolation; + /** Total number of squashed stores. */ Stats::Scalar<> lsqSquashedStores; diff --git a/src/cpu/o3/lsq_unit_impl.hh b/src/cpu/o3/lsq_unit_impl.hh index 2922b81bd..98bea74fb 100644 --- a/src/cpu/o3/lsq_unit_impl.hh +++ b/src/cpu/o3/lsq_unit_impl.hh @@ -416,7 +416,7 @@ LSQUnit::executeLoad(DynInstPtr &inst) // realizes there is activity. // Mark it as executed unless it is an uncached load that // needs to hit the head of commit. - if (!(inst->req->flags & UNCACHEABLE) || inst->isAtCommit()) { + if (!(inst->req->getFlags() & UNCACHEABLE) || inst->isAtCommit()) { inst->setExecuted(); } iewStage->instToCommit(inst); @@ -832,6 +832,7 @@ LSQUnit::completeStore(int store_idx) // A bit conservative because a store completion may not free up entries, // but hopefully avoids two store completions in one cycle from making // the CPU tick twice. + cpu->wakeCPU(); cpu->activityThisCycle(); if (store_idx == storeHead) { diff --git a/src/cpu/o3/thread_context_impl.hh b/src/cpu/o3/thread_context_impl.hh index a4546e669..25e1db21c 100755 --- a/src/cpu/o3/thread_context_impl.hh +++ b/src/cpu/o3/thread_context_impl.hh @@ -54,7 +54,7 @@ template void O3ThreadContext::dumpFuncProfile() { - // Currently not supported + thread->dumpFuncProfile(); } #endif @@ -239,12 +239,16 @@ O3ThreadContext::readLastSuspend() template void O3ThreadContext::profileClear() -{} +{ + thread->profileClear(); +} template void O3ThreadContext::profileSample() -{} +{ + thread->profileSample(); +} #endif template diff --git a/src/cpu/o3/thread_state.hh b/src/cpu/o3/thread_state.hh index 0247deb52..5fe7bb94d 100644 --- a/src/cpu/o3/thread_state.hh +++ b/src/cpu/o3/thread_state.hh @@ -117,7 +117,7 @@ struct O3ThreadState : public ThreadState { void dumpFuncProfile() { std::ostream *os = simout.create(csprintf("profile.%s.dat", cpu->name())); - profile->dump(xcProxy, *os); + profile->dump(tc, *os); } #endif }; diff --git a/src/cpu/ozone/checker_builder.cc b/src/cpu/ozone/checker_builder.cc index 99ba3e308..b4c4686b7 100644 --- a/src/cpu/ozone/checker_builder.cc +++ b/src/cpu/ozone/checker_builder.cc @@ -65,7 +65,6 @@ BEGIN_DECLARE_SIM_OBJECT_PARAMS(OzoneChecker) Param max_insts_all_threads; Param max_loads_any_thread; Param max_loads_all_threads; - Param stats_reset_inst; Param progress_interval; #if FULL_SYSTEM @@ -98,8 +97,6 @@ BEGIN_INIT_SIM_OBJECT_PARAMS(OzoneChecker) "terminate when any thread reaches this load count"), INIT_PARAM(max_loads_all_threads, "terminate when all threads have reached this load count"), - INIT_PARAM(stats_reset_inst, - "blah"), INIT_PARAM_DFLT(progress_interval, "CPU Progress Interval", 0), #if FULL_SYSTEM @@ -134,7 +131,6 @@ CREATE_SIM_OBJECT(OzoneChecker) params->max_insts_all_threads = 0; params->max_loads_any_thread = 0; params->max_loads_all_threads = 0; - params->stats_reset_inst = 0; params->exitOnError = exitOnError; params->updateOnError = updateOnError; params->warnOnlyOnLoadError = warnOnlyOnLoadError; @@ -149,7 +145,6 @@ CREATE_SIM_OBJECT(OzoneChecker) temp = max_insts_all_threads; temp = max_loads_any_thread; temp = max_loads_all_threads; - temp = stats_reset_inst; Tick temp2 = progress_interval; temp2++; params->progress_interval = 0; diff --git a/src/cpu/ozone/cpu.hh b/src/cpu/ozone/cpu.hh index ece68282f..8c5be9424 100644 --- a/src/cpu/ozone/cpu.hh +++ b/src/cpu/ozone/cpu.hh @@ -33,6 +33,7 @@ #include +#include "arch/regfile.hh" #include "base/statistics.hh" #include "base/timebuf.hh" #include "config/full_system.hh" @@ -257,8 +258,8 @@ class OzoneCPU : public BaseCPU void setFuncExeInst(Counter new_val) { thread->funcExeInst = new_val; } #endif - void changeRegFileContext(TheISA::RegFile::ContextParam param, - TheISA::RegFile::ContextVal val) + void changeRegFileContext(TheISA::RegContextParam param, + TheISA::RegContextVal val) { panic("Not supported on Alpha!"); } }; diff --git a/src/cpu/ozone/cpu_builder.cc b/src/cpu/ozone/cpu_builder.cc index e3e4ec433..730158258 100644 --- a/src/cpu/ozone/cpu_builder.cc +++ b/src/cpu/ozone/cpu_builder.cc @@ -77,7 +77,6 @@ Param max_insts_any_thread; Param max_insts_all_threads; Param max_loads_any_thread; Param max_loads_all_threads; -Param stats_reset_inst; Param progress_interval; //SimObjectParam icache; @@ -210,9 +209,6 @@ BEGIN_INIT_SIM_OBJECT_PARAMS(DerivOzoneCPU) "Terminate when all threads have reached this load" "count", 0), - INIT_PARAM_DFLT(stats_reset_inst, - "blah", - 0), INIT_PARAM_DFLT(progress_interval, "Progress interval", 0), // INIT_PARAM_DFLT(icache, "L1 instruction cache", NULL), @@ -360,7 +356,6 @@ CREATE_SIM_OBJECT(DerivOzoneCPU) params->max_insts_all_threads = max_insts_all_threads; params->max_loads_any_thread = max_loads_any_thread; params->max_loads_all_threads = max_loads_all_threads; - params->stats_reset_inst = stats_reset_inst; params->progress_interval = progress_interval; // diff --git a/src/cpu/ozone/cpu_impl.hh b/src/cpu/ozone/cpu_impl.hh index 5c8b5001d..bf547bf94 100644 --- a/src/cpu/ozone/cpu_impl.hh +++ b/src/cpu/ozone/cpu_impl.hh @@ -35,6 +35,7 @@ #include "arch/isa_traits.hh" // For MachInst #include "base/trace.hh" #include "cpu/base.hh" +#include "cpu/simple_thread.hh" #include "cpu/thread_context.hh" #include "cpu/exetrace.hh" #include "cpu/ozone/cpu.hh" @@ -52,6 +53,7 @@ #include "base/callback.hh" #include "cpu/profile.hh" #include "kern/kernel_stats.hh" +#include "mem/physical.hh" #include "sim/faults.hh" #include "sim/sim_events.hh" #include "sim/sim_exit.hh" @@ -102,7 +104,7 @@ OzoneCPU::OzoneCPU(Params *p) _status = Idle; if (p->checker) { - +#if USE_CHECKER BaseCPU *temp_checker = p->checker; checker = dynamic_cast *>(temp_checker); checker->setMemory(mem); @@ -240,7 +242,7 @@ template void OzoneCPU::switchOut() { - BaseCPU::switchOut(_sampler); + BaseCPU::switchOut(); switchCount = 0; // Front end needs state from back end, so switch out the back end first. backEnd->switchOut(); @@ -468,10 +470,10 @@ OzoneCPU::serialize(std::ostream &os) // Use SimpleThread's ability to checkpoint to make it easier to // write out the registers. Also make this static so it doesn't // get instantiated multiple times (causes a panic in statistics). - static CPUExecContext temp; + static SimpleThread temp; nameOut(os, csprintf("%s.xc.0", name())); - temp.copyXC(thread.getXCProxy()); + temp.copyTC(thread.getTC()); temp.serialize(os); } @@ -487,11 +489,11 @@ OzoneCPU::unserialize(Checkpoint *cp, const std::string §ion) // Use SimpleThread's ability to checkpoint to make it easier to // read in the registers. Also make this static so it doesn't // get instantiated multiple times (causes a panic in statistics). - static CPUExecContext temp; + static SimpleThread temp; - temp.copyXC(thread.getXCProxy()); + temp.copyTC(thread.getTC()); temp.unserialize(cp, csprintf("%s.xc.0", section)); - thread.getXCProxy()->copyArchRegs(temp.getProxy()); + thread.getTC()->copyArchRegs(temp.getTC()); } template @@ -746,11 +748,13 @@ OzoneCPU::processInterrupts() if (ipl && ipl > thread.readMiscReg(IPR_IPLR)) { thread.setMiscReg(IPR_ISR, summary); thread.setMiscReg(IPR_INTID, ipl); +#if USE_CHECKER // @todo: Make this more transparent if (checker) { checker->threadBase()->setMiscReg(IPR_ISR, summary); checker->threadBase()->setMiscReg(IPR_INTID, ipl); } +#endif Fault fault = new InterruptFault; fault->invoke(thread.getTC()); DPRINTF(Flow, "Interrupt! IPLR=%d ipl=%d summary=%x\n", @@ -872,7 +876,7 @@ OzoneCPU::OzoneTC::takeOverFrom(ThreadContext *old_context) copyArchRegs(old_context); setCpuId(old_context->readCpuId()); - thread->inst = old_context->getInst(); + thread->setInst(old_context->getInst()); #if !FULL_SYSTEM setFuncExeInst(old_context->readFuncExeInst()); #else diff --git a/src/cpu/ozone/dyn_inst_impl.hh b/src/cpu/ozone/dyn_inst_impl.hh index ba0d70417..db1460eba 100644 --- a/src/cpu/ozone/dyn_inst_impl.hh +++ b/src/cpu/ozone/dyn_inst_impl.hh @@ -215,14 +215,14 @@ OzoneDynInst::clearMemDependents() } template -MiscReg +TheISA::MiscReg OzoneDynInst::readMiscReg(int misc_reg) { return this->thread->readMiscReg(misc_reg); } template -MiscReg +TheISA::MiscReg OzoneDynInst::readMiscRegWithEffect(int misc_reg, Fault &fault) { return this->thread->readMiscRegWithEffect(misc_reg, fault); diff --git a/src/cpu/ozone/lw_back_end_impl.hh b/src/cpu/ozone/lw_back_end_impl.hh index f87a2bc57..c39b9e08b 100644 --- a/src/cpu/ozone/lw_back_end_impl.hh +++ b/src/cpu/ozone/lw_back_end_impl.hh @@ -1197,7 +1197,7 @@ LWBackEnd::commitInst(int inst_num) // (xc->readMiscReg(AlphaISA::IPR_DTB_CM) & 0x18) != 0; // thread->profilePC = usermode ? 1 : inst->readPC(); thread->profilePC = inst->readPC(); - ProfileNode *node = thread->profile->consume(thread->getXCProxy(), + ProfileNode *node = thread->profile->consume(thread->getTC(), inst->staticInst); if (node) diff --git a/src/cpu/ozone/lw_lsq_impl.hh b/src/cpu/ozone/lw_lsq_impl.hh index 31ffa9d67..4c96ad149 100644 --- a/src/cpu/ozone/lw_lsq_impl.hh +++ b/src/cpu/ozone/lw_lsq_impl.hh @@ -121,7 +121,7 @@ OzoneLWLSQ::completeDataAccess(PacketPtr pkt) } if (inst->isStore()) { - completeStore(state->idx); + completeStore(inst); } } @@ -178,6 +178,10 @@ OzoneLWLSQ::regStats() lsqMemOrderViolation .name(name() + ".memOrderViolation") .desc("Number of memory ordering violations"); +} + +template +void OzoneLWLSQ::setCPU(OzoneCPU *cpu_ptr) { cpu = cpu_ptr; @@ -390,7 +394,7 @@ OzoneLWLSQ::executeLoad(DynInstPtr &inst) // Actually probably want the oldest faulting load if (load_fault != NoFault) { DPRINTF(OzoneLSQ, "Load [sn:%lli] has a fault\n", inst->seqNum); - if (!(inst->req->flags & UNCACHEABLE && !inst->isAtCommit())) { + if (!(inst->req->getFlags() & UNCACHEABLE && !inst->isAtCommit())) { inst->setExecuted(); } // Maybe just set it as can commit here, although that might cause diff --git a/src/cpu/ozone/thread_state.hh b/src/cpu/ozone/thread_state.hh index adaa8e71b..c86f3552e 100644 --- a/src/cpu/ozone/thread_state.hh +++ b/src/cpu/ozone/thread_state.hh @@ -68,7 +68,7 @@ struct OzoneThreadState : public ThreadState { #if FULL_SYSTEM OzoneThreadState(CPUType *_cpu, int _thread_num) : ThreadState(-1, _thread_num), - cpu(_cpu), intrflag(0), inSyscall(0), trapPending(0) + intrflag(0), cpu(_cpu), inSyscall(0), trapPending(0) { if (cpu->params->profile) { profile = new FunctionProfile(cpu->params->system->kernelSymtab); @@ -151,7 +151,7 @@ struct OzoneThreadState : public ThreadState { void dumpFuncProfile() { std::ostream *os = simout.create(csprintf("profile.%s.dat", cpu->name())); - profile->dump(xcProxy, *os); + profile->dump(tc, *os); } #endif }; diff --git a/src/cpu/thread_state.hh b/src/cpu/thread_state.hh index 5479f8478..14e033b7f 100644 --- a/src/cpu/thread_state.hh +++ b/src/cpu/thread_state.hh @@ -195,20 +195,6 @@ struct ThreadState { #endif -#if FULL_SYSTEM - void profileClear() - { - if (profile) - profile->clear(); - } - - void profileSample() - { - if (profile) - profile->sample(profileNode, profilePC); - } -#endif - /** Current instruction the thread is committing. Only set and * used for DTB faults currently. */ diff --git a/src/python/m5/objects/BaseCPU.py b/src/python/m5/objects/BaseCPU.py index 05ccbca6a..0b887cceb 100644 --- a/src/python/m5/objects/BaseCPU.py +++ b/src/python/m5/objects/BaseCPU.py @@ -26,8 +26,6 @@ class BaseCPU(SimObject): "terminate when all threads have reached this load count") max_loads_any_thread = Param.Counter(0, "terminate when any thread reaches this load count") - stats_reset_inst = Param.Counter(0, - "reset stats once this many instructions are committed") progress_interval = Param.Tick(0, "interval to print out the progress message") defer_registration = Param.Bool(False, diff --git a/src/sim/pseudo_inst.cc b/src/sim/pseudo_inst.cc index aae2f6021..b66c78b2c 100644 --- a/src/sim/pseudo_inst.cc +++ b/src/sim/pseudo_inst.cc @@ -149,9 +149,9 @@ namespace AlphaPseudo } void - loadsymbol(ExecContext *xc) + loadsymbol(ThreadContext *tc) { - const string &filename = xc->getCpuPtr()->system->params()->symbolfile; + const string &filename = tc->getCpuPtr()->system->params()->symbolfile; if (filename.empty()) { return; } @@ -187,7 +187,7 @@ namespace AlphaPseudo if (!to_number(address, addr)) continue; - if (!xc->getSystemPtr()->kernelSymtab->insert(addr, symbol)) + if (!tc->getSystemPtr()->kernelSymtab->insert(addr, symbol)) continue; From e08aa72b3d74dcccee6b9648c546df19d6c3cdd3 Mon Sep 17 00:00:00 2001 From: Kevin Lim Date: Mon, 2 Oct 2006 12:04:24 -0400 Subject: [PATCH 20/20] Add in ability to start a trace at a specific cycle. --HG-- extra : convert_revision : 54098f3974d2a05d60e57113f7ceb46cb7a26672 --- src/python/m5/main.py | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/python/m5/main.py b/src/python/m5/main.py index e296453db..e93ef3a36 100644 --- a/src/python/m5/main.py +++ b/src/python/m5/main.py @@ -144,6 +144,8 @@ add_option("--trace-flags", metavar="FLAG[,FLAG]", action='append', split=',', help="Sets the flags for tracing") add_option("--trace-start", metavar="TIME", default='0s', help="Start tracing at TIME (must have units)") +add_option("--trace-cycle", metavar="CYCLE", default='0', + help="Start tracing at CYCLE") add_option("--trace-file", metavar="FILE", default="cout", help="Sets the output file for tracing [Default: %default]") add_option("--trace-circlebuf", metavar="SIZE", type="int", default=0,