X86: Pass whether an access was a read/write/fetch so faults can behave accordingly.
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parent
6c5afe6346
commit
e8c1c3e72e
6 changed files with 21 additions and 12 deletions
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@ -166,13 +166,13 @@ namespace X86ISA
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void FakeITLBFault::invoke(ThreadContext * tc)
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void FakeITLBFault::invoke(ThreadContext * tc)
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{
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{
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// Start the page table walker.
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// Start the page table walker.
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tc->getITBPtr()->walk(tc, vaddr);
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tc->getITBPtr()->walk(tc, vaddr, write, execute);
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}
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}
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void FakeDTLBFault::invoke(ThreadContext * tc)
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void FakeDTLBFault::invoke(ThreadContext * tc)
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{
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{
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// Start the page table walker.
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// Start the page table walker.
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tc->getDTBPtr()->walk(tc, vaddr);
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tc->getDTBPtr()->walk(tc, vaddr, write, execute);
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}
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}
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#else // !FULL_SYSTEM
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#else // !FULL_SYSTEM
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@ -429,10 +429,12 @@ namespace X86ISA
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{
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{
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protected:
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protected:
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Addr vaddr;
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Addr vaddr;
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bool write;
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bool execute;
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public:
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public:
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FakeITLBFault(Addr _vaddr) :
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FakeITLBFault(Addr _vaddr, bool _write, bool _execute) :
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X86Fault("fake instruction tlb fault", "itlb", 0),
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X86Fault("fake instruction tlb fault", "itlb", 0),
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vaddr(_vaddr)
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vaddr(_vaddr), write(_write), execute(_execute)
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{}
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{}
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void invoke(ThreadContext * tc);
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void invoke(ThreadContext * tc);
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@ -442,10 +444,12 @@ namespace X86ISA
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{
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{
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protected:
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protected:
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Addr vaddr;
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Addr vaddr;
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bool write;
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bool execute;
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public:
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public:
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FakeDTLBFault(Addr _vaddr) :
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FakeDTLBFault(Addr _vaddr, bool _write, bool _execute) :
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X86Fault("fake data tlb fault", "dtlb", 0),
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X86Fault("fake data tlb fault", "dtlb", 0),
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vaddr(_vaddr)
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vaddr(_vaddr), write(_write), execute(_execute)
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{}
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{}
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void invoke(ThreadContext * tc);
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void invoke(ThreadContext * tc);
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@ -319,11 +319,13 @@ Walker::doNext(PacketPtr &read, PacketPtr &write)
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}
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}
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void
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void
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Walker::start(ThreadContext * _tc, Addr vaddr)
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Walker::start(ThreadContext * _tc, Addr vaddr, bool _write, bool _execute)
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{
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{
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assert(state == Ready);
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assert(state == Ready);
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assert(!tc);
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assert(!tc);
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tc = _tc;
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tc = _tc;
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execute = _execute;
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write = _write;
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VAddr addr = vaddr;
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VAddr addr = vaddr;
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@ -95,7 +95,7 @@ namespace X86ISA
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void doNext(PacketPtr &read, PacketPtr &write);
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void doNext(PacketPtr &read, PacketPtr &write);
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// Kick off the state machine.
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// Kick off the state machine.
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void start(ThreadContext * _tc, Addr vaddr);
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void start(ThreadContext * _tc, Addr vaddr, bool write, bool execute);
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protected:
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protected:
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@ -165,8 +165,11 @@ namespace X86ISA
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State nextState;
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State nextState;
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int size;
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int size;
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bool enableNX;
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bool enableNX;
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bool write, execute;
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TlbEntry entry;
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TlbEntry entry;
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Fault pageFault(bool present);
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public:
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public:
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void setTLB(TLB * _tlb)
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void setTLB(TLB * _tlb)
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@ -140,9 +140,9 @@ TLB::lookup(Addr va, bool update_lru)
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#if FULL_SYSTEM
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#if FULL_SYSTEM
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void
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void
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TLB::walk(ThreadContext * _tc, Addr vaddr)
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TLB::walk(ThreadContext * _tc, Addr vaddr, bool write, bool execute)
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{
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{
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walker->start(_tc, vaddr);
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walker->start(_tc, vaddr, write, execute);
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}
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}
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#endif
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#endif
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@ -616,7 +616,7 @@ TLB::translate(RequestPtr &req, ThreadContext *tc, bool write, bool execute)
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// The vaddr already has the segment base applied.
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// The vaddr already has the segment base applied.
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TlbEntry *entry = lookup(vaddr);
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TlbEntry *entry = lookup(vaddr);
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if (!entry) {
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if (!entry) {
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return new TlbFault(vaddr);
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return new TlbFault(vaddr, write, execute);
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} else {
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} else {
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// Do paging protection checks.
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// Do paging protection checks.
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DPRINTF(TLB, "Entry found with paddr %#x, doing protection checks.\n", entry->paddr);
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DPRINTF(TLB, "Entry found with paddr %#x, doing protection checks.\n", entry->paddr);
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@ -119,7 +119,7 @@ namespace X86ISA
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Walker * walker;
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Walker * walker;
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void walk(ThreadContext * _tc, Addr vaddr);
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void walk(ThreadContext * _tc, Addr vaddr, bool write, bool execute);
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#endif
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#endif
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public:
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public:
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