Enforce the timing cpu ticking at it's clock rate

Add a max time option in seconds and a single system root clock be 1THz

configs/test/fs.py:
    Add a max time option in seconds and a single system root clock be 1THz
src/cpu/simple/timing.cc:
src/cpu/simple/timing.hh:
    Enforce the timing cpu ticking at it's clock rate

--HG--
extra : convert_revision : a1b0de27abde867f9c3da5bec11639e3d82a95f5
This commit is contained in:
Ali Saidi 2006-07-20 19:00:40 -04:00
parent 15e5ce96c7
commit e8a3295075
3 changed files with 88 additions and 10 deletions

View file

@ -10,6 +10,7 @@ parser = optparse.OptionParser()
parser.add_option("-d", "--detailed", action="store_true") parser.add_option("-d", "--detailed", action="store_true")
parser.add_option("-t", "--timing", action="store_true") parser.add_option("-t", "--timing", action="store_true")
parser.add_option("-m", "--maxtick", type="int") parser.add_option("-m", "--maxtick", type="int")
parser.add_option("--maxtime", type="float")
parser.add_option("--dual", help="Run full system using dual systems", parser.add_option("--dual", help="Run full system using dual systems",
action="store_true") action="store_true")
@ -102,7 +103,7 @@ if options.dual:
MyLinuxAlphaSystem(readfile=script('netperf-stream-nt-client.rcS')), MyLinuxAlphaSystem(readfile=script('netperf-stream-nt-client.rcS')),
MyLinuxAlphaSystem(readfile=script('netperf-server.rcS'))) MyLinuxAlphaSystem(readfile=script('netperf-server.rcS')))
else: else:
root = TsunamiRoot(clock = '2GHz', system = MyLinuxAlphaSystem()) root = TsunamiRoot(clock = '1THz', system = MyLinuxAlphaSystem())
m5.instantiate(root) m5.instantiate(root)
@ -116,6 +117,10 @@ m5.instantiate(root)
if options.maxtick: if options.maxtick:
exit_event = m5.simulate(options.maxtick) exit_event = m5.simulate(options.maxtick)
elif options.maxtime:
simtime = int(options.maxtime * root.clock.value)
print "simulating for: ", simtime
exit_event = m5.simulate(simtime)
else: else:
exit_event = m5.simulate() exit_event = m5.simulate()

View file

@ -85,8 +85,16 @@ TimingSimpleCPU::CpuPort::recvStatusChange(Status status)
panic("TimingSimpleCPU doesn't expect recvStatusChange callback!"); panic("TimingSimpleCPU doesn't expect recvStatusChange callback!");
} }
void
TimingSimpleCPU::CpuPort::TickEvent::schedule(Packet *_pkt, Tick t)
{
pkt = _pkt;
Event::schedule(t);
}
TimingSimpleCPU::TimingSimpleCPU(Params *p) TimingSimpleCPU::TimingSimpleCPU(Params *p)
: BaseSimpleCPU(p), icachePort(this), dcachePort(this) : BaseSimpleCPU(p), icachePort(this, p->clock), dcachePort(this, p->clock)
{ {
_status = Idle; _status = Idle;
ifetch_pkt = dcache_pkt = NULL; ifetch_pkt = dcache_pkt = NULL;
@ -462,11 +470,26 @@ TimingSimpleCPU::completeIfetch(Packet *pkt)
} }
} }
void
TimingSimpleCPU::IcachePort::ITickEvent::process()
{
cpu->completeIfetch(pkt);
}
bool bool
TimingSimpleCPU::IcachePort::recvTiming(Packet *pkt) TimingSimpleCPU::IcachePort::recvTiming(Packet *pkt)
{ {
cpu->completeIfetch(pkt); // These next few lines could be replaced with something faster
// who knows what though
Tick time = pkt->req->getTime();
while (time < curTick)
time += lat;
if (time == curTick)
cpu->completeIfetch(pkt);
else
tickEvent.schedule(pkt, time);
return true; return true;
} }
@ -523,10 +546,24 @@ TimingSimpleCPU::completeDrain()
bool bool
TimingSimpleCPU::DcachePort::recvTiming(Packet *pkt) TimingSimpleCPU::DcachePort::recvTiming(Packet *pkt)
{ {
cpu->completeDataAccess(pkt); Tick time = pkt->req->getTime();
while (time < curTick)
time += lat;
if (time == curTick)
cpu->completeDataAccess(pkt);
else
tickEvent.schedule(pkt, time);
return true; return true;
} }
void
TimingSimpleCPU::DcachePort::DTickEvent::process()
{
cpu->completeDataAccess(pkt);
}
void void
TimingSimpleCPU::DcachePort::recvRetry() TimingSimpleCPU::DcachePort::recvRetry()
{ {

View file

@ -74,11 +74,12 @@ class TimingSimpleCPU : public BaseSimpleCPU
{ {
protected: protected:
TimingSimpleCPU *cpu; TimingSimpleCPU *cpu;
Tick lat;
public: public:
CpuPort(const std::string &_name, TimingSimpleCPU *_cpu) CpuPort(const std::string &_name, TimingSimpleCPU *_cpu, Tick _lat)
: Port(_name), cpu(_cpu) : Port(_name), cpu(_cpu), lat(_lat)
{ } { }
protected: protected:
@ -92,14 +93,26 @@ class TimingSimpleCPU : public BaseSimpleCPU
virtual void getDeviceAddressRanges(AddrRangeList &resp, virtual void getDeviceAddressRanges(AddrRangeList &resp,
AddrRangeList &snoop) AddrRangeList &snoop)
{ resp.clear(); snoop.clear(); } { resp.clear(); snoop.clear(); }
struct TickEvent : public Event
{
Packet *pkt;
TimingSimpleCPU *cpu;
TickEvent(TimingSimpleCPU *_cpu)
:Event(&mainEventQueue), cpu(_cpu) {}
const char *description() { return "Timing CPU clock event"; }
void schedule(Packet *_pkt, Tick t);
};
}; };
class IcachePort : public CpuPort class IcachePort : public CpuPort
{ {
public: public:
IcachePort(TimingSimpleCPU *_cpu) IcachePort(TimingSimpleCPU *_cpu, Tick _lat)
: CpuPort(_cpu->name() + "-iport", _cpu) : CpuPort(_cpu->name() + "-iport", _cpu, _lat), tickEvent(_cpu)
{ } { }
protected: protected:
@ -107,14 +120,26 @@ class TimingSimpleCPU : public BaseSimpleCPU
virtual bool recvTiming(Packet *pkt); virtual bool recvTiming(Packet *pkt);
virtual void recvRetry(); virtual void recvRetry();
struct ITickEvent : public TickEvent
{
ITickEvent(TimingSimpleCPU *_cpu)
: TickEvent(_cpu) {}
void process();
const char *description() { return "Timing CPU clock event"; }
};
ITickEvent tickEvent;
}; };
class DcachePort : public CpuPort class DcachePort : public CpuPort
{ {
public: public:
DcachePort(TimingSimpleCPU *_cpu) DcachePort(TimingSimpleCPU *_cpu, Tick _lat)
: CpuPort(_cpu->name() + "-dport", _cpu) : CpuPort(_cpu->name() + "-dport", _cpu, _lat), tickEvent(_cpu)
{ } { }
protected: protected:
@ -122,6 +147,17 @@ class TimingSimpleCPU : public BaseSimpleCPU
virtual bool recvTiming(Packet *pkt); virtual bool recvTiming(Packet *pkt);
virtual void recvRetry(); virtual void recvRetry();
struct DTickEvent : public TickEvent
{
DTickEvent(TimingSimpleCPU *_cpu)
: TickEvent(_cpu) {}
void process();
const char *description() { return "Timing CPU clock event"; }
};
DTickEvent tickEvent;
}; };
IcachePort icachePort; IcachePort icachePort;