Merge with main repository.

configs/example/se.py

@@ -181,7 +181,6 @@ if options.ruby:
     options.use_map = True
     Ruby.create_system(options, system)
     assert(options.num_cpus == len(system.ruby._cpu_ruby_ports))
-    system.system_port = system.ruby._sys_port_proxy.port
 else:
     system.system_port = system.membus.port
     system.physmem.port = system.membus.port

configs/ruby/Ruby.py

@@ -105,6 +105,10 @@ def create_system(options, system, piobus = None, dma_devices = []):
     # full-fledged controller
     system.sys_port_proxy = sys_port_proxy
 
+    # Connect the system port for loading of binaries etc
+    system.system_port = system.sys_port_proxy.port
+
+
     #
     # Set the network classes based on the command line options
     #
@@ -182,5 +186,4 @@ def create_system(options, system, piobus = None, dma_devices = []):
     ruby.profiler = ruby_profiler
     ruby.mem_size = total_mem_size
     ruby._cpu_ruby_ports = cpu_sequencers
-    ruby._sys_port_proxy = sys_port_proxy
     ruby.random_seed    = options.random_seed

src/arch/arm/vtophys.hh

@@ -38,7 +38,6 @@
 #include "arch/arm/utility.hh"
 
 class ThreadContext;
-class FunctionalPort;
 
 namespace ArmISA {
     inline Addr PteAddr(Addr a) { return (a & PteMask) << PteShift; }

src/arch/mips/vtophys.hh

@@ -38,7 +38,6 @@
 #include "arch/mips/utility.hh"
 
 class ThreadContext;
-class FunctionalPort;
 
 namespace MipsISA {
     Addr vtophys(Addr vaddr);

src/arch/power/vtophys.hh

@@ -40,7 +40,6 @@
 #include "arch/power/utility.hh"
 
 class ThreadContext;
-class FunctionalPort;
 
 namespace PowerISA {
 

src/arch/sparc/vtophys.hh

@@ -36,13 +36,9 @@
 #include "arch/sparc/pagetable.hh"
 
 class ThreadContext;
-class FunctionalPort;
 
 namespace SparcISA {
 
-PageTableEntry
-kernel_pte_lookup(FunctionalPort *mem, Addr ptbr, SparcISA::VAddr vaddr);
-
 Addr vtophys(Addr vaddr);
 Addr vtophys(ThreadContext *tc, Addr vaddr);
 

src/cpu/inorder/thread_context.hh

@@ -44,8 +44,6 @@ namespace Kernel {
     class Statistics;
 };
 
-class TranslatingPort;
-
 /**
  * Derived ThreadContext class for use with the InOrderCPU.  It
  * provides the interface for any external objects to access a

src/cpu/o3/thread_context.hh

@@ -40,8 +40,6 @@ namespace Kernel {
     class Statistics;
 };
 
-class TranslatingPort;
-
 /**
  * Derived ThreadContext class for use with the O3CPU.  It
  * provides the interface for any external objects to access a

src/cpu/simple_thread.hh

@@ -57,8 +57,6 @@ class BaseCPU;
 
 class FunctionProfile;
 class ProfileNode;
-class PhysicalPort;
-class TranslatingPort;
 
 namespace TheISA {
     namespace Kernel {

src/kern/solaris/solaris.hh

@@ -34,8 +34,6 @@
 #include "base/types.hh"
 #include "kern/operatingsystem.hh"
 
-class TranslatingPort;
-
 ///
 /// This class encapsulates the types, structures, constants,
 /// functions, and syscall-number mappings specific to the Solaris

src/mem/ruby/system/RubyPort.cc

@@ -88,8 +88,7 @@ RubyPort::getPort(const std::string &if_name, int idx)
         // RubyPort should only have one port to physical memory
         assert (physMemPort == NULL);
 
-        physMemPort = new M5Port(csprintf("%s-physMemPort", name()), this,
+        physMemPort = new PioPort(csprintf("%s-physMemPort", name()), this);
-                                 ruby_system, access_phys_mem);
 
         return physMemPort;
     }

src/mem/ruby/system/RubyPort.hh

@@ -155,7 +155,7 @@ class RubyPort : public MemObject
     uint16_t m_port_id;
     uint64_t m_request_cnt;
 
-    M5Port* physMemPort;
+    PioPort* physMemPort;
 
     /*! Vector of CPU Port attached to this Ruby port. */
     typedef std::vector<M5Port*>::iterator CpuPortIter;

tests/configs/memtest-ruby.py

@@ -106,10 +106,6 @@ for (i, ruby_port) in enumerate(system.ruby._cpu_ruby_ports):
      #
      ruby_port.access_phys_mem = False
 
-
-# Connect the system port for loading of binaries etc
-system.system_port = system.ruby._sys_port_proxy.port
-
 # -----------------------
 # run simulation
 # -----------------------

tests/configs/o3-timing-mp-ruby.py

@@ -46,6 +46,8 @@ for cpu in cpus:
 # connect memory to membus
 system.physmem.port = system.membus.port
 
+# Connect the system port for loading of binaries etc
+system.system_port = system.membus.port
 
 # -----------------------
 # run simulation

tests/configs/o3-timing-ruby.py

@@ -43,4 +43,7 @@ system = System(cpu = cpu,
 system.physmem.port = system.membus.port
 cpu.connectAllPorts(system.membus)
 
+# Connect the system port for loading of binaries etc
+system.system_port = system.membus.port
+
 root = Root(full_system = False, system = system)

tests/configs/rubytest-ruby.py

@@ -102,9 +102,6 @@ for ruby_port in system.ruby._cpu_ruby_ports:
     #
     ruby_port.access_phys_mem = False
 
-# Connect the system port for loading of binaries etc
-system.system_port = system.ruby._sys_port_proxy.port
-
 # -----------------------
 # run simulation
 # -----------------------

tests/configs/simple-atomic-mp-ruby.py

@@ -47,6 +47,8 @@ for cpu in cpus:
 # connect memory to membus
 system.physmem.port = system.membus.port
 
+# Connect the system port for loading of binaries etc
+system.system_port = system.membus.port
 
 # -----------------------
 # run simulation

tests/configs/simple-timing-mp-ruby.py

@@ -85,9 +85,6 @@ for (i, cpu) in enumerate(system.cpu):
     cpu.icache_port = system.ruby._cpu_ruby_ports[i].port
     cpu.dcache_port = system.ruby._cpu_ruby_ports[i].port
 
-# Connect the system port for loading of binaries etc
-system.system_port = system.ruby._sys_port_proxy.port
-
 # -----------------------
 # run simulation
 # -----------------------

tests/configs/simple-timing-ruby.py

@@ -81,9 +81,6 @@ assert(len(system.ruby._cpu_ruby_ports) == 1)
 #
 cpu.connectAllPorts(system.ruby._cpu_ruby_ports[0])
 
-# Connect the system port for loading of binaries etc
-system.system_port = system.ruby._sys_port_proxy.port
-
 # -----------------------
 # run simulation
 # -----------------------