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Merge zizzer.eecs.umich.edu:/bk/newmem

Browse source 
into  zower.eecs.umich.edu:/home/gblack/m5/newmem-o3-spec

--HG--
extra : convert_revision : 6b1c8025d29f3e8f90906805dd51a5d523d56004
This commit is contained in:
Gabe Black 2007-03-23 21:47:03 -04:00
commit e7bbd85ae6
1 changed files with 16 additions and 4 deletions
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20
src/arch/sparc/isa/decoder.isa
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@ -1324,8 +1324,14 @@ decode OP default Unknown::unknown()
0x05: stb({{Mem.ub = Rd.sb;}}); 0x05: stb({{Mem.ub = Rd.sb;}});
0x06: sth({{Mem.uhw = Rd.shw;}}); 0x06: sth({{Mem.uhw = Rd.shw;}});
0x07: sttw({{ 0x07: sttw({{
(Mem.tuw).a = RdLow<31:0>; //This temporary needs to be here so that the parser
(Mem.tuw).b = RdHigh<31:0>; //will correctly identify this instruction as a store.
//It's probably either the parenthesis or referencing
//the member variable that throws confuses it.
Twin32_t temp;
temp.a = RdLow<31:0>;
temp.b = RdHigh<31:0>;
Mem.tuw = temp;
}}); }});
} }
format Load { format Load {
@ -1417,8 +1423,14 @@ decode OP default Unknown::unknown()
0x15: stba({{Mem.ub = Rd;}}, {{EXT_ASI}}); 0x15: stba({{Mem.ub = Rd;}}, {{EXT_ASI}});
0x16: stha({{Mem.uhw = Rd;}}, {{EXT_ASI}}); 0x16: stha({{Mem.uhw = Rd;}}, {{EXT_ASI}});
0x17: sttwa({{ 0x17: sttwa({{
(Mem.tuw).a = RdLow<31:0>; //This temporary needs to be here so that the parser
(Mem.tuw).b = RdHigh<31:0>; //will correctly identify this instruction as a store.
//It's probably either the parenthesis or referencing
//the member variable that throws confuses it.
Twin32_t temp;
temp.a = RdLow<31:0>;
temp.b = RdHigh<31:0>;
Mem.tuw = temp;
}}, {{EXT_ASI}}); }}, {{EXT_ASI}});
} }
format LoadAlt { format LoadAlt {