diff --git a/dev/alpha_console.cc b/dev/alpha_console.cc index 79317b15b..ad9d0a239 100644 --- a/dev/alpha_console.cc +++ b/dev/alpha_console.cc @@ -81,7 +81,7 @@ AlphaConsole::read(MemReqPtr &req, uint8_t *data) memset(data, 0, req->size); uint64_t val; - Addr daddr = req->paddr - addr; + Addr daddr = req->paddr - (addr & PA_IMPL_MASK); switch (daddr) { case offsetof(AlphaAccess, inputChar): @@ -129,7 +129,7 @@ AlphaConsole::write(MemReqPtr &req, const uint8_t *data) return Machine_Check_Fault; } - Addr daddr = req->paddr - addr; + Addr daddr = req->paddr - (addr & PA_IMPL_MASK); ExecContext *other_xc; switch (daddr) { diff --git a/dev/pciconfigall.cc b/dev/pciconfigall.cc index 0c1efd898..63943c7be 100644 --- a/dev/pciconfigall.cc +++ b/dev/pciconfigall.cc @@ -68,7 +68,7 @@ PCIConfigAll::read(MemReqPtr &req, uint8_t *data) DPRINTF(PCIConfigAll, "read va=%#x size=%d\n", req->vaddr, req->size); - Addr daddr = (req->paddr & size); + Addr daddr = (req->paddr - (addr & PA_IMPL_MASK)); int device = (daddr >> 11) & 0x1F; int func = (daddr >> 8) & 0x7; @@ -112,7 +112,7 @@ PCIConfigAll::read(MemReqPtr &req, uint8_t *data) Fault PCIConfigAll::write(MemReqPtr &req, const uint8_t *data) { - Addr daddr = (req->paddr & size); + Addr daddr = (req->paddr - (addr & PA_IMPL_MASK)); int device = (daddr >> 11) & 0x1F; int func = (daddr >> 8) & 0x7; diff --git a/dev/tsunami_cchip.cc b/dev/tsunami_cchip.cc index 374c50d66..b825a91bc 100644 --- a/dev/tsunami_cchip.cc +++ b/dev/tsunami_cchip.cc @@ -47,7 +47,7 @@ TsunamiCChip::read(MemReqPtr &req, uint8_t *data) DPRINTF(Tsunami, "read va=%#x size=%d\n", req->vaddr, req->size); - Addr daddr = (req->paddr & size) >> 6; + Addr daddr = (req->paddr - (addr & PA_IMPL_MASK)) >> 6; ExecContext *xc = req->xc; switch (req->size) { @@ -133,7 +133,7 @@ TsunamiCChip::write(MemReqPtr &req, const uint8_t *data) DPRINTF(Tsunami, "write - va=%#x size=%d \n", req->vaddr, req->size); - Addr daddr = (req->paddr & size) >> 6; + Addr daddr = (req->paddr - (addr & PA_IMPL_MASK)) >> 6; switch (req->size) { diff --git a/dev/tsunami_io.cc b/dev/tsunami_io.cc index dd2ac3acc..15727631b 100644 --- a/dev/tsunami_io.cc +++ b/dev/tsunami_io.cc @@ -153,7 +153,7 @@ TsunamiIO::read(MemReqPtr &req, uint8_t *data) DPRINTF(Tsunami, "io read va=%#x size=%d IOPorrt=%#x\n", req->vaddr, req->size, req->vaddr & 0xfff); - Addr daddr = (req->paddr & size); + Addr daddr = (req->paddr - (addr & PA_IMPL_MASK)); // ExecContext *xc = req->xc; // int cpuid = xc->cpu_id; @@ -228,7 +228,7 @@ TsunamiIO::write(MemReqPtr &req, const uint8_t *data) DPRINTF(Tsunami, "io write - va=%#x size=%d IOPort=%#x Data=%#x\n", req->vaddr, req->size, req->vaddr & 0xfff, dt64); - Addr daddr = (req->paddr & size); + Addr daddr = (req->paddr - (addr & PA_IMPL_MASK)); switch(req->size) { case sizeof(uint8_t): diff --git a/dev/tsunami_pchip.cc b/dev/tsunami_pchip.cc index b67bd476d..59e085361 100644 --- a/dev/tsunami_pchip.cc +++ b/dev/tsunami_pchip.cc @@ -52,7 +52,7 @@ TsunamiPChip::read(MemReqPtr &req, uint8_t *data) DPRINTF(Tsunami, "read va=%#x size=%d\n", req->vaddr, req->size); - Addr daddr = (req->paddr & size) >> 6; + Addr daddr = (req->paddr - (addr & PA_IMPL_MASK)) >> 6; // ExecContext *xc = req->xc; // int cpuid = xc->cpu_id; @@ -142,7 +142,7 @@ TsunamiPChip::write(MemReqPtr &req, const uint8_t *data) DPRINTF(Tsunami, "write - va=%#x size=%d \n", req->vaddr, req->size); - Addr daddr = (req->paddr & size) >> 6; + Addr daddr = (req->paddr - (addr & PA_IMPL_MASK)) >> 6; switch (req->size) { diff --git a/dev/tsunami_uart.cc b/dev/tsunami_uart.cc index ab9236081..9e7207d9c 100644 --- a/dev/tsunami_uart.cc +++ b/dev/tsunami_uart.cc @@ -36,13 +36,15 @@ TsunamiUart::TsunamiUart(const string &name, SimConsole *c, Addr a, : FunctionalMemory(name), addr(a), cons(c), status_store(0), valid_char(false) { + mmu->add_child(this, Range(addr, addr + size)); + IER = 0; } Fault TsunamiUart::read(MemReqPtr &req, uint8_t *data) { - Addr daddr = req->paddr & size; + Addr daddr = req->paddr - (addr & PA_IMPL_MASK); DPRINTF(TsunamiUart, " read register %#x\n", daddr); switch (req->size) { @@ -61,7 +63,7 @@ TsunamiUart::read(MemReqPtr &req, uint8_t *data) } switch (daddr) { - case 0xD: // Status Register + case 0x5: // Status Register { int status = cons->intStatus(); if (!valid_char) { @@ -95,7 +97,7 @@ TsunamiUart::read(MemReqPtr &req, uint8_t *data) break; } - case 0x8: // Data register (RX) + case 0x0: // Data register (RX) // if (!valid_char) // panic("Invalid character"); @@ -106,7 +108,7 @@ TsunamiUart::read(MemReqPtr &req, uint8_t *data) valid_char = false; return No_Fault; - case 0x9: // Interrupt Enable Register + case 0x1: // Interrupt Enable Register // This is the lovely way linux checks there is actually a serial // port at the desired address if (IER == 0) @@ -116,7 +118,7 @@ TsunamiUart::read(MemReqPtr &req, uint8_t *data) else *data = 0; return No_Fault; - case 0xA: + case 0x2: //*data = 2<<6; // This means a 8250 serial port, do we want a 16550? *data = 0; // This means a 8250 serial port, do we want a 16550? return No_Fault; @@ -130,11 +132,11 @@ TsunamiUart::read(MemReqPtr &req, uint8_t *data) Fault TsunamiUart::write(MemReqPtr &req, const uint8_t *data) { - Addr daddr = req->paddr & size; + Addr daddr = req->paddr - (addr & PA_IMPL_MASK); DPRINTF(TsunamiUart, " write register %#x value %#x\n", daddr, *(uint8_t*)data); switch (daddr) { - case 0xb: + case 0x3: status_store = *data; switch (*data) { case 0x03: // going to read RR3 @@ -161,14 +163,14 @@ TsunamiUart::write(MemReqPtr &req, const uint8_t *data) return No_Fault; } - case 0x8: // Data register (TX) + case 0x0: // Data register (TX) cons->out(*(uint64_t *)data); return No_Fault; - case 0x9: // DLM + case 0x1: // DLM DPRINTF(TsunamiUart, "writing to DLM/IER %#x\n", *(uint8_t*)data); IER = *(uint8_t*)data; return No_Fault; - case 0xc: // MCR + case 0x4: // MCR DPRINTF(TsunamiUart, "writing to MCR %#x\n", *(uint8_t*)data); return No_Fault; diff --git a/dev/tsunami_uart.hh b/dev/tsunami_uart.hh index 2beefc7ea..f0a9b644b 100644 --- a/dev/tsunami_uart.hh +++ b/dev/tsunami_uart.hh @@ -44,7 +44,7 @@ class TsunamiUart : public FunctionalMemory { private: Addr addr; - static const Addr size = 0xf; + static const Addr size = 0x8; protected: SimConsole *cons;