Revamp cache timing access mshr check to make stats sane again.
--HG-- extra : convert_revision : 37009b8ee536807073b5a5ca07ed1d097a496aea
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parent
bdf3323915
commit
e6d6adc731
2 changed files with 45 additions and 21 deletions
18
src/mem/cache/blk.hh
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18
src/mem/cache/blk.hh
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@ -51,8 +51,10 @@ enum CacheBlkStatusBits {
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BlkValid = 0x01,
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/** write permission */
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BlkWritable = 0x02,
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/** read permission (yes, block can be valid but not readable) */
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BlkReadable = 0x04,
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/** dirty (modified) */
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BlkDirty = 0x04,
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BlkDirty = 0x08,
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/** block was referenced */
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BlkReferenced = 0x10,
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/** block was a hardware prefetch yet unaccessed*/
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@ -162,7 +164,19 @@ class CacheBlk
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}
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/**
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* Checks that a block is valid (readable).
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* Checks the read permissions of this block. Note that a block
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* can be valid but not readable if there is an outstanding write
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* upgrade miss.
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* @return True if the block is readable.
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*/
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bool isReadable() const
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{
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const int needed_bits = BlkReadable | BlkValid;
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return (status & needed_bits) == needed_bits;
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}
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/**
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* Checks that a block is valid.
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* @return True if the block is valid.
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*/
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bool isValid() const
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46
src/mem/cache/cache_impl.hh
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46
src/mem/cache/cache_impl.hh
vendored
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@ -292,7 +292,7 @@ Cache<TagStore>::access(PacketPtr pkt, BlkType *&blk, int &lat)
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}
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}
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if (pkt->needsExclusive() ? blk->isWritable() : blk->isValid()) {
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if (pkt->needsExclusive() ? blk->isWritable() : blk->isReadable()) {
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// OK to satisfy access
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hits[pkt->cmdToIndex()][0/*pkt->req->getThreadNum()*/]++;
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satisfyCpuSideRequest(pkt, blk);
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@ -318,7 +318,7 @@ Cache<TagStore>::access(PacketPtr pkt, BlkType *&blk, int &lat)
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incMissCount(pkt);
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return false;
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}
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blk->status = BlkValid;
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blk->status = BlkValid | BlkReadable;
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}
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std::memcpy(blk->data, pkt->getPtr<uint8_t>(), blkSize);
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blk->status |= BlkDirty;
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@ -422,21 +422,8 @@ Cache<TagStore>::timingAccess(PacketPtr pkt)
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}
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int lat = hitLatency;
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bool satisfied = false;
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Addr blk_addr = pkt->getAddr() & ~(Addr(blkSize-1));
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MSHR *mshr = mshrQueue.findMatch(blk_addr);
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if (!mshr) {
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// no outstanding access to this block, look up in cache
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// (otherwise if we allow reads while there's an outstanding
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// write miss, the read could return stale data out of the
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// cache block... a more aggressive system could detect the
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// overlap (if any) and forward data out of the MSHRs, but we
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// don't do that yet)
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BlkType *blk = NULL;
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satisfied = access(pkt, blk, lat);
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}
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bool satisfied = access(pkt, blk, lat);
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#if 0
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/** @todo make the fast write alloc (wh64) work with coherence. */
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@ -483,6 +470,9 @@ Cache<TagStore>::timingAccess(PacketPtr pkt)
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if (prefetchMiss)
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prefetcher->handleMiss(pkt, time);
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Addr blk_addr = pkt->getAddr() & ~(Addr(blkSize-1));
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MSHR *mshr = mshrQueue.findMatch(blk_addr);
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if (mshr) {
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// MSHR hit
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//@todo remove hw_pf here
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@ -508,6 +498,26 @@ Cache<TagStore>::timingAccess(PacketPtr pkt)
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if (pkt->cmd == MemCmd::Writeback) {
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allocateWriteBuffer(pkt, time, true);
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} else {
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if (blk && blk->isValid()) {
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// If we have a write miss to a valid block, we
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// need to mark the block non-readable. Otherwise
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// if we allow reads while there's an outstanding
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// write miss, the read could return stale data
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// out of the cache block... a more aggressive
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// system could detect the overlap (if any) and
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// forward data out of the MSHRs, but we don't do
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// that yet. Note that we do need to leave the
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// block valid so that it stays in the cache, in
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// case we get an upgrade response (and hence no
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// new data) when the write miss completes.
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// As long as CPUs do proper store/load forwarding
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// internally, and have a sufficiently weak memory
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// model, this is probably unnecessary, but at some
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// point it must have seemed like we needed it...
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assert(pkt->needsExclusive() && !blk->isWritable());
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blk->status &= ~BlkReadable;
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}
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allocateMissBuffer(pkt, time, true);
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}
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}
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@ -934,10 +944,10 @@ Cache<TagStore>::handleFill(PacketPtr pkt, BlkType *blk,
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}
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if (!pkt->sharedAsserted()) {
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blk->status = BlkValid | BlkWritable;
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blk->status = BlkValid | BlkReadable | BlkWritable;
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} else {
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assert(!pkt->needsExclusive());
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blk->status = BlkValid;
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blk->status = BlkValid | BlkReadable;
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}
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DPRINTF(Cache, "Block addr %x moving from state %i to %i\n",
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