ARM: Update regression tests for ldr/str microcode changes.
This commit is contained in:
Ali Saidi
parent
4d8f4db8d1
commit
e6d3fe8a0c
34 changed files with 190 additions and 190 deletions
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@ -5,9 +5,9 @@ The Regents of The University of Michigan
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All Rights Reserved
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M5 compiled Jul 25 2010 20:52:35
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M5 revision ffac9df60637 7512 default tip
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M5 started Jul 26 2010 23:53:12
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M5 compiled Aug 24 2010 15:34:40
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M5 revision 1c687284910c 7619 default qtip round2.patch tip qbase
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M5 started Aug 24 2010 15:35:18
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M5 executing on zizzer
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command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/00.gzip/arm/linux/simple-atomic -re tests/run.py build/ARM_SE/tests/fast/long/00.gzip/arm/linux/simple-atomic
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Global frequency set at 1000000000000 ticks per second
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@ -43,4 +43,4 @@ Uncompressing Data
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Uncompressed data 1048576 bytes in length
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Uncompressed data compared correctly
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Tested 1MB buffer: OK!
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Exiting @ tick 298674141000 because target called exit()
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Exiting @ tick 300302141500 because target called exit()
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@ -1,13 +1,13 @@
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---------- Begin Simulation Statistics ----------
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host_inst_rate 2670640 # Simulator instruction rate (inst/s)
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host_mem_usage 197140 # Number of bytes of host memory used
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host_seconds 223.66 # Real time elapsed on the host
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host_tick_rate 1335369827 # Simulator tick rate (ticks/s)
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host_inst_rate 4210115 # Simulator instruction rate (inst/s)
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host_mem_usage 202336 # Number of bytes of host memory used
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host_seconds 142.65 # Real time elapsed on the host
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host_tick_rate 2105134486 # Simulator tick rate (ticks/s)
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sim_freq 1000000000000 # Frequency of simulated ticks
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sim_insts 597325393 # Number of instructions simulated
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sim_seconds 0.298674 # Number of seconds simulated
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sim_ticks 298674141000 # Number of ticks simulated
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sim_insts 600581394 # Number of instructions simulated
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sim_seconds 0.300302 # Number of seconds simulated
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sim_ticks 300302141500 # Number of ticks simulated
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system.cpu.dtb.accesses 0 # DTB accesses
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system.cpu.dtb.hits 0 # DTB hits
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system.cpu.dtb.misses 0 # DTB misses
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@ -28,8 +28,8 @@ system.cpu.itb.write_accesses 0 # DT
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system.cpu.itb.write_hits 0 # DTB write hits
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system.cpu.itb.write_misses 0 # DTB write misses
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system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
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system.cpu.numCycles 597348283 # number of cpu cycles simulated
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system.cpu.num_insts 597325393 # Number of instructions executed
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system.cpu.numCycles 600604284 # number of cpu cycles simulated
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system.cpu.num_insts 600581394 # Number of instructions executed
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system.cpu.num_refs 219174038 # Number of memory references
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system.cpu.workload.PROG:num_syscalls 48 # Number of system calls
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@ -5,9 +5,9 @@ The Regents of The University of Michigan
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All Rights Reserved
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||||
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M5 compiled Jul 25 2010 20:52:35
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M5 revision ffac9df60637 7512 default tip
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M5 started Jul 26 2010 23:53:12
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M5 compiled Aug 24 2010 15:34:40
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M5 revision 1c687284910c 7619 default qtip round2.patch tip qbase
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M5 started Aug 24 2010 15:44:30
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M5 executing on zizzer
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command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/00.gzip/arm/linux/simple-timing -re tests/run.py build/ARM_SE/tests/fast/long/00.gzip/arm/linux/simple-timing
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Global frequency set at 1000000000000 ticks per second
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@ -1,11 +1,11 @@
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---------- Begin Simulation Statistics ----------
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host_inst_rate 1588198 # Simulator instruction rate (inst/s)
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host_mem_usage 204824 # Number of bytes of host memory used
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host_seconds 374.87 # Real time elapsed on the host
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host_tick_rate 2155749682 # Simulator tick rate (ticks/s)
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host_inst_rate 1674821 # Simulator instruction rate (inst/s)
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host_mem_usage 210020 # Number of bytes of host memory used
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host_seconds 357.42 # Real time elapsed on the host
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host_tick_rate 2260963263 # Simulator tick rate (ticks/s)
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sim_freq 1000000000000 # Frequency of simulated ticks
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sim_insts 595363823 # Number of instructions simulated
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sim_insts 598619824 # Number of instructions simulated
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sim_seconds 0.808121 # Number of seconds simulated
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sim_ticks 808121048000 # Number of ticks simulated
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system.cpu.dcache.ReadReq_accesses 147793610 # number of ReadReq accesses(hits+misses)
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@ -226,7 +226,7 @@ system.cpu.l2cache.warmup_cycle 0 # Cy
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system.cpu.l2cache.writebacks 61092 # number of writebacks
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system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
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system.cpu.numCycles 1616242096 # number of cpu cycles simulated
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system.cpu.num_insts 595363823 # Number of instructions executed
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system.cpu.num_insts 598619824 # Number of instructions executed
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system.cpu.num_refs 219174038 # Number of memory references
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system.cpu.workload.PROG:num_syscalls 48 # Number of system calls
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@ -5,9 +5,9 @@ The Regents of The University of Michigan
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All Rights Reserved
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||||
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M5 compiled Jul 25 2010 20:52:35
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M5 revision ffac9df60637 7512 default tip
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M5 started Jul 26 2010 23:59:27
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M5 compiled Aug 24 2010 15:34:40
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M5 revision 1c687284910c 7619 default qtip round2.patch tip qbase
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M5 started Aug 24 2010 15:38:49
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M5 executing on zizzer
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command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/10.mcf/arm/linux/simple-atomic -re tests/run.py build/ARM_SE/tests/fast/long/10.mcf/arm/linux/simple-atomic
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Global frequency set at 1000000000000 ticks per second
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@ -28,4 +28,4 @@ simplex iterations : 2663
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flow value : 3080014995
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checksum : 68389
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optimal
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Exiting @ tick 54182628000 because target called exit()
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Exiting @ tick 54215549000 because target called exit()
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@ -1,13 +1,13 @@
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---------- Begin Simulation Statistics ----------
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host_inst_rate 2639601 # Simulator instruction rate (inst/s)
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host_mem_usage 330716 # Number of bytes of host memory used
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host_seconds 34.53 # Real time elapsed on the host
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host_tick_rate 1569281777 # Simulator tick rate (ticks/s)
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host_inst_rate 2482902 # Simulator instruction rate (inst/s)
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host_mem_usage 335796 # Number of bytes of host memory used
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host_seconds 36.73 # Real time elapsed on the host
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host_tick_rate 1475953499 # Simulator tick rate (ticks/s)
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sim_freq 1000000000000 # Frequency of simulated ticks
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sim_insts 91136893 # Number of instructions simulated
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sim_seconds 0.054183 # Number of seconds simulated
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sim_ticks 54182628000 # Number of ticks simulated
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sim_insts 91202735 # Number of instructions simulated
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sim_seconds 0.054216 # Number of seconds simulated
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sim_ticks 54215549000 # Number of ticks simulated
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system.cpu.dtb.accesses 0 # DTB accesses
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system.cpu.dtb.hits 0 # DTB hits
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system.cpu.dtb.misses 0 # DTB misses
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@ -28,8 +28,8 @@ system.cpu.itb.write_accesses 0 # DT
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system.cpu.itb.write_hits 0 # DTB write hits
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system.cpu.itb.write_misses 0 # DTB write misses
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system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
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system.cpu.numCycles 108365257 # number of cpu cycles simulated
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system.cpu.num_insts 91136893 # Number of instructions executed
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system.cpu.numCycles 108431099 # number of cpu cycles simulated
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system.cpu.num_insts 91202735 # Number of instructions executed
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system.cpu.num_refs 27330336 # Number of memory references
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system.cpu.workload.PROG:num_syscalls 442 # Number of system calls
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@ -5,9 +5,9 @@ The Regents of The University of Michigan
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All Rights Reserved
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||||
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M5 compiled Jul 25 2010 20:52:35
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M5 revision ffac9df60637 7512 default tip
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M5 started Jul 26 2010 23:53:12
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M5 compiled Aug 24 2010 15:34:40
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M5 revision 1c687284910c 7619 default qtip round2.patch tip qbase
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M5 started Aug 24 2010 15:38:31
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M5 executing on zizzer
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command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/10.mcf/arm/linux/simple-timing -re tests/run.py build/ARM_SE/tests/fast/long/10.mcf/arm/linux/simple-timing
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Global frequency set at 1000000000000 ticks per second
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@ -1,11 +1,11 @@
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---------- Begin Simulation Statistics ----------
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host_inst_rate 1187634 # Simulator instruction rate (inst/s)
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host_mem_usage 338364 # Number of bytes of host memory used
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host_seconds 76.72 # Real time elapsed on the host
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host_tick_rate 1983393949 # Simulator tick rate (ticks/s)
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host_inst_rate 1413696 # Simulator instruction rate (inst/s)
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host_mem_usage 343480 # Number of bytes of host memory used
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host_seconds 64.50 # Real time elapsed on the host
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host_tick_rate 2359219725 # Simulator tick rate (ticks/s)
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sim_freq 1000000000000 # Frequency of simulated ticks
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sim_insts 91110245 # Number of instructions simulated
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sim_insts 91176087 # Number of instructions simulated
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sim_seconds 0.152158 # Number of seconds simulated
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sim_ticks 152158072000 # Number of ticks simulated
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system.cpu.dcache.ReadReq_accesses 22564820 # number of ReadReq accesses(hits+misses)
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@ -226,7 +226,7 @@ system.cpu.l2cache.warmup_cycle 0 # Cy
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system.cpu.l2cache.writebacks 35 # number of writebacks
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system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
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system.cpu.numCycles 304316144 # number of cpu cycles simulated
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system.cpu.num_insts 91110245 # Number of instructions executed
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system.cpu.num_insts 91176087 # Number of instructions executed
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system.cpu.num_refs 27330336 # Number of memory references
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system.cpu.workload.PROG:num_syscalls 442 # Number of system calls
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@ -5,9 +5,9 @@ The Regents of The University of Michigan
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All Rights Reserved
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||||
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||||
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M5 compiled Jul 25 2010 20:52:35
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M5 revision ffac9df60637 7512 default tip
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M5 started Jul 26 2010 23:59:31
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M5 compiled Aug 24 2010 15:34:40
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M5 revision 1c687284910c 7619 default qtip round2.patch tip qbase
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M5 started Aug 24 2010 15:44:22
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M5 executing on zizzer
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command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/20.parser/arm/linux/simple-atomic -re tests/run.py build/ARM_SE/tests/fast/long/20.parser/arm/linux/simple-atomic
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Global frequency set at 1000000000000 ticks per second
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@ -72,4 +72,4 @@ info: Increasing stack size by one page.
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about 2 million people attended
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the five best costumes got prizes
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No errors!
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Exiting @ tick 284221891000 because target called exit()
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Exiting @ tick 285716811500 because target called exit()
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@ -1,13 +1,13 @@
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---------- Begin Simulation Statistics ----------
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host_inst_rate 3798348 # Simulator instruction rate (inst/s)
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host_mem_usage 200684 # Number of bytes of host memory used
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host_seconds 147.02 # Real time elapsed on the host
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host_tick_rate 1933283176 # Simulator tick rate (ticks/s)
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host_inst_rate 4358961 # Simulator instruction rate (inst/s)
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host_mem_usage 206092 # Number of bytes of host memory used
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host_seconds 128.79 # Real time elapsed on the host
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host_tick_rate 2218414400 # Simulator tick rate (ticks/s)
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sim_freq 1000000000000 # Frequency of simulated ticks
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sim_insts 558414014 # Number of instructions simulated
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sim_seconds 0.284222 # Number of seconds simulated
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sim_ticks 284221891000 # Number of ticks simulated
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sim_insts 561403855 # Number of instructions simulated
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sim_seconds 0.285717 # Number of seconds simulated
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sim_ticks 285716811500 # Number of ticks simulated
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system.cpu.dtb.accesses 0 # DTB accesses
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system.cpu.dtb.hits 0 # DTB hits
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system.cpu.dtb.misses 0 # DTB misses
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@ -28,8 +28,8 @@ system.cpu.itb.write_accesses 0 # DT
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system.cpu.itb.write_hits 0 # DTB write hits
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system.cpu.itb.write_misses 0 # DTB write misses
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system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
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system.cpu.numCycles 568443783 # number of cpu cycles simulated
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system.cpu.num_insts 558414014 # Number of instructions executed
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system.cpu.numCycles 571433624 # number of cpu cycles simulated
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system.cpu.num_insts 561403855 # Number of instructions executed
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system.cpu.num_refs 184987503 # Number of memory references
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system.cpu.workload.PROG:num_syscalls 548 # Number of system calls
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@ -5,9 +5,9 @@ The Regents of The University of Michigan
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All Rights Reserved
|
||||
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||||
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||||
M5 compiled Jul 25 2010 20:52:35
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||||
M5 revision ffac9df60637 7512 default tip
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||||
M5 started Jul 26 2010 23:53:12
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M5 compiled Aug 24 2010 15:34:40
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M5 revision 1c687284910c 7619 default qtip round2.patch tip qbase
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M5 started Aug 24 2010 15:39:26
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M5 executing on zizzer
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command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/20.parser/arm/linux/simple-timing -re tests/run.py build/ARM_SE/tests/fast/long/20.parser/arm/linux/simple-timing
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Global frequency set at 1000000000000 ticks per second
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@ -1,11 +1,11 @@
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---------- Begin Simulation Statistics ----------
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host_inst_rate 1423169 # Simulator instruction rate (inst/s)
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host_mem_usage 208376 # Number of bytes of host memory used
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host_seconds 391.02 # Real time elapsed on the host
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host_tick_rate 1931572776 # Simulator tick rate (ticks/s)
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host_inst_rate 1894447 # Simulator instruction rate (inst/s)
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host_mem_usage 213780 # Number of bytes of host memory used
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host_seconds 295.32 # Real time elapsed on the host
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host_tick_rate 2557466745 # Simulator tick rate (ticks/s)
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sim_freq 1000000000000 # Frequency of simulated ticks
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sim_insts 556480686 # Number of instructions simulated
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sim_insts 559470527 # Number of instructions simulated
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sim_seconds 0.755275 # Number of seconds simulated
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sim_ticks 755274721000 # Number of ticks simulated
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system.cpu.dcache.ReadReq_accesses 127326326 # number of ReadReq accesses(hits+misses)
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@ -226,7 +226,7 @@ system.cpu.l2cache.warmup_cycle 531606891000 # Cy
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system.cpu.l2cache.writebacks 206160 # number of writebacks
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system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
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system.cpu.numCycles 1510549442 # number of cpu cycles simulated
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system.cpu.num_insts 556480686 # Number of instructions executed
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system.cpu.num_insts 559470527 # Number of instructions executed
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system.cpu.num_refs 184987503 # Number of memory references
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system.cpu.workload.PROG:num_syscalls 548 # Number of system calls
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@ -5,9 +5,9 @@ The Regents of The University of Michigan
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|||
All Rights Reserved
|
||||
|
||||
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||||
M5 compiled Jul 25 2010 20:52:35
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||||
M5 revision ffac9df60637 7512 default tip
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||||
M5 started Jul 26 2010 23:56:52
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M5 compiled Aug 24 2010 15:34:40
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M5 revision 1c687284910c 7619 default qtip round2.patch tip qbase
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||||
M5 started Aug 24 2010 15:34:42
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M5 executing on zizzer
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command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/30.eon/arm/linux/simple-atomic -re tests/run.py build/ARM_SE/tests/fast/long/30.eon/arm/linux/simple-atomic
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Global frequency set at 1000000000000 ticks per second
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@ -18,4 +18,4 @@ info: Increasing stack size by one page.
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info: Increasing stack size by one page.
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info: Increasing stack size by one page.
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OO-style eon Time= 0.210000
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Exiting @ tick 210098857000 because target called exit()
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Exiting @ tick 210200321500 because target called exit()
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@ -1,13 +1,13 @@
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---------- Begin Simulation Statistics ----------
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host_inst_rate 2179170 # Simulator instruction rate (inst/s)
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host_mem_usage 205868 # Number of bytes of host memory used
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host_seconds 158.12 # Real time elapsed on the host
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host_tick_rate 1328711028 # Simulator tick rate (ticks/s)
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host_inst_rate 2356342 # Simulator instruction rate (inst/s)
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host_mem_usage 210592 # Number of bytes of host memory used
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host_seconds 146.32 # Real time elapsed on the host
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host_tick_rate 1436586032 # Simulator tick rate (ticks/s)
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sim_freq 1000000000000 # Frequency of simulated ticks
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sim_insts 344575026 # Number of instructions simulated
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sim_seconds 0.210099 # Number of seconds simulated
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sim_ticks 210098857000 # Number of ticks simulated
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sim_insts 344777955 # Number of instructions simulated
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sim_seconds 0.210200 # Number of seconds simulated
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sim_ticks 210200321500 # Number of ticks simulated
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system.cpu.dtb.accesses 0 # DTB accesses
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system.cpu.dtb.hits 0 # DTB hits
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system.cpu.dtb.misses 0 # DTB misses
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@ -28,8 +28,8 @@ system.cpu.itb.write_accesses 0 # DT
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system.cpu.itb.write_hits 0 # DTB write hits
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system.cpu.itb.write_misses 0 # DTB write misses
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system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
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system.cpu.numCycles 420197715 # number of cpu cycles simulated
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system.cpu.num_insts 344575026 # Number of instructions executed
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system.cpu.numCycles 420400644 # number of cpu cycles simulated
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system.cpu.num_insts 344777955 # Number of instructions executed
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system.cpu.num_refs 177028576 # Number of memory references
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system.cpu.workload.PROG:num_syscalls 191 # Number of system calls
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|||
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@ -5,9 +5,9 @@ The Regents of The University of Michigan
|
|||
All Rights Reserved
|
||||
|
||||
|
||||
M5 compiled Jul 25 2010 20:52:35
|
||||
M5 revision ffac9df60637 7512 default tip
|
||||
M5 started Jul 26 2010 23:53:36
|
||||
M5 compiled Aug 24 2010 15:34:40
|
||||
M5 revision 1c687284910c 7619 default qtip round2.patch tip qbase
|
||||
M5 started Aug 24 2010 15:37:41
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||||
M5 executing on zizzer
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||||
command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/30.eon/arm/linux/simple-timing -re tests/run.py build/ARM_SE/tests/fast/long/30.eon/arm/linux/simple-timing
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Global frequency set at 1000000000000 ticks per second
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@ -1,11 +1,11 @@
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---------- Begin Simulation Statistics ----------
|
||||
host_inst_rate 1001528 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 213556 # Number of bytes of host memory used
|
||||
host_seconds 343.67 # Real time elapsed on the host
|
||||
host_tick_rate 1530053892 # Simulator tick rate (ticks/s)
|
||||
host_inst_rate 1023413 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 218276 # Number of bytes of host memory used
|
||||
host_seconds 336.52 # Real time elapsed on the host
|
||||
host_tick_rate 1562566741 # Simulator tick rate (ticks/s)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
sim_insts 344196749 # Number of instructions simulated
|
||||
sim_insts 344399678 # Number of instructions simulated
|
||||
sim_seconds 0.525836 # Number of seconds simulated
|
||||
sim_ticks 525836291000 # Number of ticks simulated
|
||||
system.cpu.dcache.ReadReq_accesses 94586725 # number of ReadReq accesses(hits+misses)
|
||||
|
|
@ -226,7 +226,7 @@ system.cpu.l2cache.warmup_cycle 0 # Cy
|
|||
system.cpu.l2cache.writebacks 0 # number of writebacks
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.numCycles 1051672582 # number of cpu cycles simulated
|
||||
system.cpu.num_insts 344196749 # Number of instructions executed
|
||||
system.cpu.num_insts 344399678 # Number of instructions executed
|
||||
system.cpu.num_refs 177028576 # Number of memory references
|
||||
system.cpu.workload.PROG:num_syscalls 191 # Number of system calls
|
||||
|
||||
|
|
|
|||
|
|
@ -5,9 +5,9 @@ The Regents of The University of Michigan
|
|||
All Rights Reserved
|
||||
|
||||
|
||||
M5 compiled Jul 25 2010 20:52:35
|
||||
M5 revision ffac9df60637 7512 default tip
|
||||
M5 started Jul 26 2010 23:53:56
|
||||
M5 compiled Aug 24 2010 15:34:40
|
||||
M5 revision 1c687284910c 7619 default qtip round2.patch tip qbase
|
||||
M5 started Aug 24 2010 15:34:43
|
||||
M5 executing on zizzer
|
||||
command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/40.perlbmk/arm/linux/simple-atomic -re tests/run.py build/ARM_SE/tests/fast/long/40.perlbmk/arm/linux/simple-atomic
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
|
|
@ -1390,4 +1390,4 @@ info: Increasing stack size by one page.
|
|||
2000: 760651391
|
||||
1000: 4031656975
|
||||
0: 2206428413
|
||||
Exiting @ tick 922809447000 because target called exit()
|
||||
Exiting @ tick 924828408500 because target called exit()
|
||||
|
|
|
|||
|
|
@ -1,13 +1,13 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
host_inst_rate 2704949 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 202656 # Number of bytes of host memory used
|
||||
host_seconds 680.13 # Real time elapsed on the host
|
||||
host_tick_rate 1356804201 # Simulator tick rate (ticks/s)
|
||||
host_inst_rate 3147097 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 207700 # Number of bytes of host memory used
|
||||
host_seconds 585.86 # Real time elapsed on the host
|
||||
host_tick_rate 1578574708 # Simulator tick rate (ticks/s)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
sim_insts 1839728999 # Number of instructions simulated
|
||||
sim_seconds 0.922809 # Number of seconds simulated
|
||||
sim_ticks 922809447000 # Number of ticks simulated
|
||||
sim_insts 1843766922 # Number of instructions simulated
|
||||
sim_seconds 0.924828 # Number of seconds simulated
|
||||
sim_ticks 924828408500 # Number of ticks simulated
|
||||
system.cpu.dtb.accesses 0 # DTB accesses
|
||||
system.cpu.dtb.hits 0 # DTB hits
|
||||
system.cpu.dtb.misses 0 # DTB misses
|
||||
|
|
@ -28,8 +28,8 @@ system.cpu.itb.write_accesses 0 # DT
|
|||
system.cpu.itb.write_hits 0 # DTB write hits
|
||||
system.cpu.itb.write_misses 0 # DTB write misses
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.numCycles 1845618895 # number of cpu cycles simulated
|
||||
system.cpu.num_insts 1839728999 # Number of instructions executed
|
||||
system.cpu.numCycles 1849656818 # number of cpu cycles simulated
|
||||
system.cpu.num_insts 1843766922 # Number of instructions executed
|
||||
system.cpu.num_refs 908401146 # Number of memory references
|
||||
system.cpu.workload.PROG:num_syscalls 1411 # Number of system calls
|
||||
|
||||
|
|
|
|||
|
|
@ -5,9 +5,9 @@ The Regents of The University of Michigan
|
|||
All Rights Reserved
|
||||
|
||||
|
||||
M5 compiled Jul 25 2010 20:52:35
|
||||
M5 revision ffac9df60637 7512 default tip
|
||||
M5 started Jul 26 2010 23:56:56
|
||||
M5 compiled Aug 24 2010 15:34:40
|
||||
M5 revision 1c687284910c 7619 default qtip round2.patch tip qbase
|
||||
M5 started Aug 24 2010 15:43:18
|
||||
M5 executing on zizzer
|
||||
command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/40.perlbmk/arm/linux/simple-timing -re tests/run.py build/ARM_SE/tests/fast/long/40.perlbmk/arm/linux/simple-timing
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
|
|
|
|||
|
|
@ -1,11 +1,11 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
host_inst_rate 1313947 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 210340 # Number of bytes of host memory used
|
||||
host_seconds 1391.71 # Real time elapsed on the host
|
||||
host_tick_rate 1703921021 # Simulator tick rate (ticks/s)
|
||||
host_inst_rate 1398740 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 215468 # Number of bytes of host memory used
|
||||
host_seconds 1310.23 # Real time elapsed on the host
|
||||
host_tick_rate 1809883950 # Simulator tick rate (ticks/s)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
sim_insts 1828637582 # Number of instructions simulated
|
||||
sim_insts 1832675505 # Number of instructions simulated
|
||||
sim_seconds 2.371370 # Number of seconds simulated
|
||||
sim_ticks 2371369572000 # Number of ticks simulated
|
||||
system.cpu.dcache.ReadReq_accesses 620364065 # number of ReadReq accesses(hits+misses)
|
||||
|
|
@ -226,7 +226,7 @@ system.cpu.l2cache.warmup_cycle 0 # Cy
|
|||
system.cpu.l2cache.writebacks 66101 # number of writebacks
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.numCycles 4742739144 # number of cpu cycles simulated
|
||||
system.cpu.num_insts 1828637582 # Number of instructions executed
|
||||
system.cpu.num_insts 1832675505 # Number of instructions executed
|
||||
system.cpu.num_refs 908401146 # Number of memory references
|
||||
system.cpu.workload.PROG:num_syscalls 1411 # Number of system calls
|
||||
|
||||
|
|
|
|||
|
|
@ -5,12 +5,12 @@ The Regents of The University of Michigan
|
|||
All Rights Reserved
|
||||
|
||||
|
||||
M5 compiled Jul 25 2010 20:52:35
|
||||
M5 revision ffac9df60637 7512 default tip
|
||||
M5 started Jul 26 2010 23:53:12
|
||||
M5 compiled Aug 24 2010 15:34:40
|
||||
M5 revision 1c687284910c 7619 default qtip round2.patch tip qbase
|
||||
M5 started Aug 24 2010 15:37:09
|
||||
M5 executing on zizzer
|
||||
command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/50.vortex/arm/linux/simple-atomic -re tests/run.py build/ARM_SE/tests/fast/long/50.vortex/arm/linux/simple-atomic
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
info: Increasing stack size by one page.
|
||||
Exiting @ tick 52792656500 because target called exit()
|
||||
Exiting @ tick 53034982000 because target called exit()
|
||||
|
|
|
|||
|
|
@ -1,13 +1,13 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
host_inst_rate 4246205 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 204740 # Number of bytes of host memory used
|
||||
host_seconds 23.16 # Real time elapsed on the host
|
||||
host_tick_rate 2279192640 # Simulator tick rate (ticks/s)
|
||||
host_inst_rate 2664701 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 209976 # Number of bytes of host memory used
|
||||
host_seconds 37.09 # Real time elapsed on the host
|
||||
host_tick_rate 1429827283 # Simulator tick rate (ticks/s)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
sim_insts 98353426 # Number of instructions simulated
|
||||
sim_seconds 0.052793 # Number of seconds simulated
|
||||
sim_ticks 52792656500 # Number of ticks simulated
|
||||
sim_insts 98838077 # Number of instructions simulated
|
||||
sim_seconds 0.053035 # Number of seconds simulated
|
||||
sim_ticks 53034982000 # Number of ticks simulated
|
||||
system.cpu.dtb.accesses 0 # DTB accesses
|
||||
system.cpu.dtb.hits 0 # DTB hits
|
||||
system.cpu.dtb.misses 0 # DTB misses
|
||||
|
|
@ -28,8 +28,8 @@ system.cpu.itb.write_accesses 0 # DT
|
|||
system.cpu.itb.write_hits 0 # DTB write hits
|
||||
system.cpu.itb.write_misses 0 # DTB write misses
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.numCycles 105585314 # number of cpu cycles simulated
|
||||
system.cpu.num_insts 98353426 # Number of instructions executed
|
||||
system.cpu.numCycles 106069965 # number of cpu cycles simulated
|
||||
system.cpu.num_insts 98838077 # Number of instructions executed
|
||||
system.cpu.num_refs 47871034 # Number of memory references
|
||||
system.cpu.workload.PROG:num_syscalls 1946 # Number of system calls
|
||||
|
||||
|
|
|
|||
|
|
@ -5,9 +5,9 @@ The Regents of The University of Michigan
|
|||
All Rights Reserved
|
||||
|
||||
|
||||
M5 compiled Jul 25 2010 20:52:35
|
||||
M5 revision ffac9df60637 7512 default tip
|
||||
M5 started Jul 26 2010 23:59:20
|
||||
M5 compiled Aug 24 2010 15:34:40
|
||||
M5 revision 1c687284910c 7619 default qtip round2.patch tip qbase
|
||||
M5 started Aug 24 2010 15:39:36
|
||||
M5 executing on zizzer
|
||||
command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/50.vortex/arm/linux/simple-timing -re tests/run.py build/ARM_SE/tests/fast/long/50.vortex/arm/linux/simple-timing
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
|
|
|
|||
|
|
@ -1,11 +1,11 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
host_inst_rate 1206944 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 212432 # Number of bytes of host memory used
|
||||
host_seconds 80.79 # Real time elapsed on the host
|
||||
host_tick_rate 1653060218 # Simulator tick rate (ticks/s)
|
||||
host_inst_rate 1745846 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 217668 # Number of bytes of host memory used
|
||||
host_seconds 56.13 # Real time elapsed on the host
|
||||
host_tick_rate 2379327214 # Simulator tick rate (ticks/s)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
sim_insts 97512652 # Number of instructions simulated
|
||||
sim_insts 97997303 # Number of instructions simulated
|
||||
sim_seconds 0.133556 # Number of seconds simulated
|
||||
sim_ticks 133556162000 # Number of ticks simulated
|
||||
system.cpu.dcache.ReadReq_accesses 27164439 # number of ReadReq accesses(hits+misses)
|
||||
|
|
@ -226,7 +226,7 @@ system.cpu.l2cache.warmup_cycle 0 # Cy
|
|||
system.cpu.l2cache.writebacks 88579 # number of writebacks
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.numCycles 267112324 # number of cpu cycles simulated
|
||||
system.cpu.num_insts 97512652 # Number of instructions executed
|
||||
system.cpu.num_insts 97997303 # Number of instructions executed
|
||||
system.cpu.num_refs 47871034 # Number of memory references
|
||||
system.cpu.workload.PROG:num_syscalls 1946 # Number of system calls
|
||||
|
||||
|
|
|
|||
|
|
@ -5,9 +5,9 @@ The Regents of The University of Michigan
|
|||
All Rights Reserved
|
||||
|
||||
|
||||
M5 compiled Jul 25 2010 20:52:35
|
||||
M5 revision ffac9df60637 7512 default tip
|
||||
M5 started Jul 26 2010 23:53:12
|
||||
M5 compiled Aug 24 2010 15:34:40
|
||||
M5 revision 1c687284910c 7619 default qtip round2.patch tip qbase
|
||||
M5 started Aug 24 2010 15:40:33
|
||||
M5 executing on zizzer
|
||||
command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/60.bzip2/arm/linux/simple-atomic -re tests/run.py build/ARM_SE/tests/fast/long/60.bzip2/arm/linux/simple-atomic
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
|
|
@ -29,4 +29,4 @@ Uncompressing Data
|
|||
Uncompressed data 1048576 bytes in length
|
||||
Uncompressed data compared correctly
|
||||
Tested 1MB buffer: OK!
|
||||
Exiting @ tick 846553003000 because target called exit()
|
||||
Exiting @ tick 854705615000 because target called exit()
|
||||
|
|
|
|||
|
|
@ -1,13 +1,13 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
host_inst_rate 3961270 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 197588 # Number of bytes of host memory used
|
||||
host_seconds 427.41 # Real time elapsed on the host
|
||||
host_tick_rate 1980637218 # Simulator tick rate (ticks/s)
|
||||
host_inst_rate 3154654 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 202692 # Number of bytes of host memory used
|
||||
host_seconds 541.87 # Real time elapsed on the host
|
||||
host_tick_rate 1577328455 # Simulator tick rate (ticks/s)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
sim_insts 1693103458 # Number of instructions simulated
|
||||
sim_seconds 0.846553 # Number of seconds simulated
|
||||
sim_ticks 846553003000 # Number of ticks simulated
|
||||
sim_insts 1709408682 # Number of instructions simulated
|
||||
sim_seconds 0.854706 # Number of seconds simulated
|
||||
sim_ticks 854705615000 # Number of ticks simulated
|
||||
system.cpu.dtb.accesses 0 # DTB accesses
|
||||
system.cpu.dtb.hits 0 # DTB hits
|
||||
system.cpu.dtb.misses 0 # DTB misses
|
||||
|
|
@ -28,8 +28,8 @@ system.cpu.itb.write_accesses 0 # DT
|
|||
system.cpu.itb.write_hits 0 # DTB write hits
|
||||
system.cpu.itb.write_misses 0 # DTB write misses
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.numCycles 1693106007 # number of cpu cycles simulated
|
||||
system.cpu.num_insts 1693103458 # Number of instructions executed
|
||||
system.cpu.numCycles 1709411231 # number of cpu cycles simulated
|
||||
system.cpu.num_insts 1709408682 # Number of instructions executed
|
||||
system.cpu.num_refs 660773876 # Number of memory references
|
||||
system.cpu.workload.PROG:num_syscalls 46 # Number of system calls
|
||||
|
||||
|
|
|
|||
|
|
@ -5,9 +5,9 @@ The Regents of The University of Michigan
|
|||
All Rights Reserved
|
||||
|
||||
|
||||
M5 compiled Jul 25 2010 20:52:35
|
||||
M5 revision ffac9df60637 7512 default tip
|
||||
M5 started Jul 26 2010 23:53:12
|
||||
M5 compiled Aug 24 2010 15:34:40
|
||||
M5 revision 1c687284910c 7619 default qtip round2.patch tip qbase
|
||||
M5 started Aug 24 2010 15:41:22
|
||||
M5 executing on zizzer
|
||||
command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/60.bzip2/arm/linux/simple-timing -re tests/run.py build/ARM_SE/tests/fast/long/60.bzip2/arm/linux/simple-timing
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
|
|
|
|||
|
|
@ -1,11 +1,11 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
host_inst_rate 1188041 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 205272 # Number of bytes of host memory used
|
||||
host_seconds 1420.24 # Real time elapsed on the host
|
||||
host_tick_rate 1757384537 # Simulator tick rate (ticks/s)
|
||||
host_inst_rate 1693548 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 210380 # Number of bytes of host memory used
|
||||
host_seconds 1005.94 # Real time elapsed on the host
|
||||
host_tick_rate 2481166849 # Simulator tick rate (ticks/s)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
sim_insts 1687299939 # Number of instructions simulated
|
||||
sim_insts 1703605163 # Number of instructions simulated
|
||||
sim_seconds 2.495902 # Number of seconds simulated
|
||||
sim_ticks 2495902189000 # Number of ticks simulated
|
||||
system.cpu.dcache.ReadReq_accesses 482384248 # number of ReadReq accesses(hits+misses)
|
||||
|
|
@ -226,7 +226,7 @@ system.cpu.l2cache.warmup_cycle 562275129000 # Cy
|
|||
system.cpu.l2cache.writebacks 1196151 # number of writebacks
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.numCycles 4991804378 # number of cpu cycles simulated
|
||||
system.cpu.num_insts 1687299939 # Number of instructions executed
|
||||
system.cpu.num_insts 1703605163 # Number of instructions executed
|
||||
system.cpu.num_refs 660773876 # Number of memory references
|
||||
system.cpu.workload.PROG:num_syscalls 46 # Number of system calls
|
||||
|
||||
|
|
|
|||
|
|
@ -5,9 +5,9 @@ The Regents of The University of Michigan
|
|||
All Rights Reserved
|
||||
|
||||
|
||||
M5 compiled Jul 25 2010 20:52:35
|
||||
M5 revision ffac9df60637 7512 default tip
|
||||
M5 started Jul 26 2010 23:53:12
|
||||
M5 compiled Aug 24 2010 15:34:40
|
||||
M5 revision 1c687284910c 7619 default qtip round2.patch tip qbase
|
||||
M5 started Aug 24 2010 15:37:46
|
||||
M5 executing on zizzer
|
||||
command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/70.twolf/arm/linux/simple-atomic -re tests/run.py build/ARM_SE/tests/fast/long/70.twolf/arm/linux/simple-atomic
|
||||
Couldn't unlink build/ARM_SE/tests/fast/long/70.twolf/arm/linux/simple-atomic/smred.sav
|
||||
|
|
@ -28,4 +28,4 @@ info: Increasing stack size by one page.
|
|||
76 77 78 79 80 81 82 83 84 85 86 87 88 89 90
|
||||
91 92 93 94 95 96 97 98 99 100 101 102 103 104 105
|
||||
106 107 108 109 110 111 112 113 114 115 116 117 118 119 120
|
||||
122 123 124 Exiting @ tick 102027363500 because target called exit()
|
||||
122 123 124 Exiting @ tick 102180734000 because target called exit()
|
||||
|
|
|
|||
|
|
@ -1,13 +1,13 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
host_inst_rate 4203067 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 200448 # Number of bytes of host memory used
|
||||
host_seconds 44.38 # Real time elapsed on the host
|
||||
host_tick_rate 2299185912 # Simulator tick rate (ticks/s)
|
||||
host_inst_rate 4206748 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 205772 # Number of bytes of host memory used
|
||||
host_seconds 44.41 # Real time elapsed on the host
|
||||
host_tick_rate 2300875527 # Simulator tick rate (ticks/s)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
sim_insts 186512085 # Number of instructions simulated
|
||||
sim_seconds 0.102027 # Number of seconds simulated
|
||||
sim_ticks 102027363500 # Number of ticks simulated
|
||||
sim_insts 186818826 # Number of instructions simulated
|
||||
sim_seconds 0.102181 # Number of seconds simulated
|
||||
sim_ticks 102180734000 # Number of ticks simulated
|
||||
system.cpu.dtb.accesses 0 # DTB accesses
|
||||
system.cpu.dtb.hits 0 # DTB hits
|
||||
system.cpu.dtb.misses 0 # DTB misses
|
||||
|
|
@ -28,8 +28,8 @@ system.cpu.itb.write_accesses 0 # DT
|
|||
system.cpu.itb.write_hits 0 # DTB write hits
|
||||
system.cpu.itb.write_misses 0 # DTB write misses
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.numCycles 204054728 # number of cpu cycles simulated
|
||||
system.cpu.num_insts 186512085 # Number of instructions executed
|
||||
system.cpu.numCycles 204361469 # number of cpu cycles simulated
|
||||
system.cpu.num_insts 186818826 # Number of instructions executed
|
||||
system.cpu.num_refs 42511846 # Number of memory references
|
||||
system.cpu.workload.PROG:num_syscalls 400 # Number of system calls
|
||||
|
||||
|
|
|
|||
|
|
@ -5,9 +5,9 @@ The Regents of The University of Michigan
|
|||
All Rights Reserved
|
||||
|
||||
|
||||
M5 compiled Jul 25 2010 20:52:35
|
||||
M5 revision ffac9df60637 7512 default tip
|
||||
M5 started Jul 26 2010 23:54:29
|
||||
M5 compiled Aug 24 2010 15:34:40
|
||||
M5 revision 1c687284910c 7619 default qtip round2.patch tip qbase
|
||||
M5 started Aug 24 2010 15:39:29
|
||||
M5 executing on zizzer
|
||||
command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/long/70.twolf/arm/linux/simple-timing -re tests/run.py build/ARM_SE/tests/fast/long/70.twolf/arm/linux/simple-timing
|
||||
Couldn't unlink build/ARM_SE/tests/fast/long/70.twolf/arm/linux/simple-timing/smred.sav
|
||||
|
|
|
|||
|
|
@ -1,11 +1,11 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
host_inst_rate 1300701 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 208132 # Number of bytes of host memory used
|
||||
host_seconds 143.02 # Real time elapsed on the host
|
||||
host_tick_rate 1622346657 # Simulator tick rate (ticks/s)
|
||||
host_inst_rate 1662173 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 213456 # Number of bytes of host memory used
|
||||
host_seconds 112.10 # Real time elapsed on the host
|
||||
host_tick_rate 2069793412 # Simulator tick rate (ticks/s)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
sim_insts 186027114 # Number of instructions simulated
|
||||
sim_insts 186333855 # Number of instructions simulated
|
||||
sim_seconds 0.232029 # Number of seconds simulated
|
||||
sim_ticks 232029492000 # Number of ticks simulated
|
||||
system.cpu.dcache.ReadReq_accesses 29640180 # number of ReadReq accesses(hits+misses)
|
||||
|
|
@ -226,7 +226,7 @@ system.cpu.l2cache.warmup_cycle 0 # Cy
|
|||
system.cpu.l2cache.writebacks 0 # number of writebacks
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.numCycles 464058984 # number of cpu cycles simulated
|
||||
system.cpu.num_insts 186027114 # Number of instructions executed
|
||||
system.cpu.num_insts 186333855 # Number of instructions executed
|
||||
system.cpu.num_refs 42511846 # Number of memory references
|
||||
system.cpu.workload.PROG:num_syscalls 400 # Number of system calls
|
||||
|
||||
|
|
|
|||
|
|
@ -5,12 +5,12 @@ The Regents of The University of Michigan
|
|||
All Rights Reserved
|
||||
|
||||
|
||||
M5 compiled Jun 1 2010 16:08:15
|
||||
M5 revision 4b3bf0363048 7414 default qtip tip ext/linux_se_structs.patch
|
||||
M5 started Jun 1 2010 16:09:04
|
||||
M5 executing on harpertown2
|
||||
command line: ./build/ARM_SE/m5.debug -r -e tests/run.py quick/00.hello/arm/linux/simple-atomic
|
||||
M5 compiled Aug 24 2010 15:34:40
|
||||
M5 revision 1c687284910c 7619 default qtip round2.patch tip qbase
|
||||
M5 started Aug 24 2010 15:34:42
|
||||
M5 executing on zizzer
|
||||
command line: build/ARM_SE/m5.fast -d build/ARM_SE/tests/fast/quick/00.hello/arm/linux/simple-atomic -re tests/run.py build/ARM_SE/tests/fast/quick/00.hello/arm/linux/simple-atomic
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
Hello world!
|
||||
Exiting @ tick 2761000 because target called exit()
|
||||
Exiting @ tick 2816000 because target called exit()
|
||||
|
|
|
|||
|
|
@ -1,13 +1,13 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
host_inst_rate 92316 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 191512 # Number of bytes of host memory used
|
||||
host_seconds 0.06 # Real time elapsed on the host
|
||||
host_tick_rate 46039687 # Simulator tick rate (ticks/s)
|
||||
host_inst_rate 6903 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 198548 # Number of bytes of host memory used
|
||||
host_seconds 0.81 # Real time elapsed on the host
|
||||
host_tick_rate 3457658 # Simulator tick rate (ticks/s)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
sim_insts 5510 # Number of instructions simulated
|
||||
sim_insts 5620 # Number of instructions simulated
|
||||
sim_seconds 0.000003 # Number of seconds simulated
|
||||
sim_ticks 2761000 # Number of ticks simulated
|
||||
sim_ticks 2816000 # Number of ticks simulated
|
||||
system.cpu.dtb.accesses 0 # DTB accesses
|
||||
system.cpu.dtb.hits 0 # DTB hits
|
||||
system.cpu.dtb.misses 0 # DTB misses
|
||||
|
|
@ -28,8 +28,8 @@ system.cpu.itb.write_accesses 0 # DT
|
|||
system.cpu.itb.write_hits 0 # DTB write hits
|
||||
system.cpu.itb.write_misses 0 # DTB write misses
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.numCycles 5523 # number of cpu cycles simulated
|
||||
system.cpu.num_insts 5510 # Number of instructions executed
|
||||
system.cpu.numCycles 5633 # number of cpu cycles simulated
|
||||
system.cpu.num_insts 5620 # Number of instructions executed
|
||||
system.cpu.num_refs 2145 # Number of memory references
|
||||
system.cpu.workload.PROG:num_syscalls 13 # Number of system calls
|
||||
|
||||
|
|
|
|||
Loading…
Reference in a new issue