ARM: Don't return the result of a table walk the same cycle it's completed.
The L1 cache may have been accessed to provide this data, which confuses it, if it ends up being accesses twice in one cycle. Instead wait 1 tick which will force the timing simple CPU to forward to its next clock cycle when the translation completes. Also prevent multiple outstanding table walks from occuring at once.
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2 changed files with 75 additions and 8 deletions
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@ -41,13 +41,14 @@
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#include "arch/arm/table_walker.hh"
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#include "arch/arm/tlb.hh"
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#include "dev/io_device.hh"
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#include "cpu/base.hh"
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#include "cpu/thread_context.hh"
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using namespace ArmISA;
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TableWalker::TableWalker(const Params *p)
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: MemObject(p), port(NULL), tlb(NULL),
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currState(NULL), doL1DescEvent(this), doL2DescEvent(this)
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: MemObject(p), port(NULL), tlb(NULL), currState(NULL), pending(false),
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doL1DescEvent(this), doL2DescEvent(this), doProcessEvent(this)
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{
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sctlr = 0;
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}
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@ -115,6 +116,35 @@ TableWalker::walk(RequestPtr _req, ThreadContext *_tc, uint8_t _cid, TLB::Mode _
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currState->isFetch = (currState->mode == TLB::Execute);
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currState->isWrite = (currState->mode == TLB::Write);
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if (!currState->timing)
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return processWalk();
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if (pending) {
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pendingQueue.push_back(currState);
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currState = NULL;
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} else {
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pending = true;
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processWalk();
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}
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return NoFault;
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}
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void
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TableWalker::processWalkWrapper()
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{
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assert(!currState);
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assert(pendingQueue.size());
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currState = pendingQueue.front();
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pendingQueue.pop_front();
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pending = true;
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processWalk();
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}
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Fault
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TableWalker::processWalk()
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{
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Addr ttbr = 0;
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// If translation isn't enabled, we shouldn't be here
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@ -146,6 +176,9 @@ TableWalker::walk(RequestPtr _req, ThreadContext *_tc, uint8_t _cid, TLB::Mode _
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if (currState->timing) {
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currState->transState->finish(f, currState->req,
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currState->tc, currState->mode);
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pending = false;
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nextWalk(currState->tc);
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currState = NULL;
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} else {
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currState->tc = NULL;
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@ -156,7 +189,8 @@ TableWalker::walk(RequestPtr _req, ThreadContext *_tc, uint8_t _cid, TLB::Mode _
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if (currState->timing) {
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port->dmaAction(MemCmd::ReadReq, l1desc_addr, sizeof(uint32_t),
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&doL1DescEvent, (uint8_t*)&currState->l1Desc.data, (Tick)0);
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&doL1DescEvent, (uint8_t*)&currState->l1Desc.data,
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currState->tc->getCpuPtr()->ticks(1));
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DPRINTF(TLBVerbose, "Adding to walker fifo: queue size before adding: %d\n",
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stateQueueL1.size());
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stateQueueL1.push_back(currState);
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@ -167,7 +201,8 @@ TableWalker::walk(RequestPtr _req, ThreadContext *_tc, uint8_t _cid, TLB::Mode _
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flag = Request::UNCACHEABLE;
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}
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port->dmaAction(MemCmd::ReadReq, l1desc_addr, sizeof(uint32_t),
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NULL, (uint8_t*)&currState->l1Desc.data, (Tick)0, flag);
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NULL, (uint8_t*)&currState->l1Desc.data,
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currState->tc->getCpuPtr()->ticks(1), flag);
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doL1Descriptor();
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f = currState->fault;
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}
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@ -498,10 +533,12 @@ TableWalker::doL1Descriptor()
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if (currState->timing) {
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currState->delayed = true;
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port->dmaAction(MemCmd::ReadReq, l2desc_addr, sizeof(uint32_t),
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&doL2DescEvent, (uint8_t*)&currState->l2Desc.data, 0);
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&doL2DescEvent, (uint8_t*)&currState->l2Desc.data,
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currState->tc->getCpuPtr()->ticks(1));
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} else {
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port->dmaAction(MemCmd::ReadReq, l2desc_addr, sizeof(uint32_t),
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NULL, (uint8_t*)&currState->l2Desc.data, 0);
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NULL, (uint8_t*)&currState->l2Desc.data,
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currState->tc->getCpuPtr()->ticks(1));
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doL2Descriptor();
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}
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return;
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@ -589,6 +626,9 @@ TableWalker::doL1DescriptorWrapper()
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currState->transState->finish(currState->fault, currState->req,
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currState->tc, currState->mode);
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pending = false;
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nextWalk(currState->tc);
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currState->req = NULL;
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currState->tc = NULL;
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currState->delayed = false;
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@ -600,10 +640,12 @@ TableWalker::doL1DescriptorWrapper()
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currState->fault = tlb->translateTiming(currState->req, currState->tc,
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currState->transState, currState->mode);
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pending = false;
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nextWalk(currState->tc);
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currState->req = NULL;
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currState->tc = NULL;
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currState->delayed = false;
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delete currState;
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} else {
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// need to do L2 descriptor
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@ -633,15 +675,28 @@ TableWalker::doL2DescriptorWrapper()
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currState->transState, currState->mode);
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}
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stateQueueL2.pop_front();
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pending = false;
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nextWalk(currState->tc);
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currState->req = NULL;
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currState->tc = NULL;
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currState->delayed = false;
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stateQueueL2.pop_front();
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delete currState;
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currState = NULL;
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}
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void
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TableWalker::nextWalk(ThreadContext *tc)
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{
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if (pendingQueue.size())
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schedule(doProcessEvent, tc->getCpuPtr()->nextCycle(curTick+1));
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}
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ArmISA::TableWalker *
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ArmTableWalkerParams::create()
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{
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@ -320,6 +320,11 @@ class TableWalker : public MemObject
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* require an additional level. */
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std::list<WalkerState *> stateQueueL2;
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/** Queue of requests that have passed are waiting because the walker is
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* currently busy. */
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std::list<WalkerState *> pendingQueue;;
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/** Port to issue translation requests from */
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DmaPort *port;
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@ -331,6 +336,9 @@ class TableWalker : public MemObject
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WalkerState *currState;
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/** If a timing translation is currently in progress */
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bool pending;
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public:
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typedef ArmTableWalkerParams Params;
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TableWalker(const Params *p);
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@ -362,7 +370,11 @@ class TableWalker : public MemObject
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void doL2DescriptorWrapper();
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EventWrapper<TableWalker, &TableWalker::doL2DescriptorWrapper> doL2DescEvent;
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Fault processWalk();
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void processWalkWrapper();
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EventWrapper<TableWalker, &TableWalker::processWalkWrapper> doProcessEvent;
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void nextWalk(ThreadContext *tc);
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};
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