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ARM: Add two unimplemented miscellaneous registers.

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Adds MISCREG_ID_MMFR2 and removes break on access to MISCREG_CLIDR. Both
registers now return values that are consistent with current ARM
implementations.
This commit is contained in:
Wade Walker 2011-07-15 11:53:34 -05:00
parent d919930c3c
commit e6672d1f29
2 changed files with 11 additions and 6 deletions
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11
src/arch/arm/isa.cc
View file

@ -186,12 +186,19 @@ ISA::readMiscReg(int misc_reg, ThreadContext *tc)
case MISCREG_MPIDR:
return tc->cpuId();
break;
case MISCREG_ID_MMFR0:
return 0x03; // VMSAv7 support
case MISCREG_ID_MMFR2:
return 0x01230000; // no HW access | WFI stalling | ISB and DSB
// | all TLB maintenance | no Harvard
case MISCREG_ID_MMFR3:
return 0xF0102211; // SuperSec | Coherent TLB | Bcast Maint |
// BP Maint | Cache Maint Set/way | Cache Maint MVA
case MISCREG_CLIDR:
warn_once("The clidr register always reports 0 caches.\n");
break;
warn_once("clidr LoUIS field of 0b001 to match current "
"ARM implementations.\n");
return 0x00200000;
case MISCREG_CCSIDR:
warn_once("The ccsidr register isn't implemented and "
"always reads as 0.\n");
@ -203,8 +210,6 @@ ISA::readMiscReg(int misc_reg, ThreadContext *tc)
case MISCREG_ID_PFR1:
warn("reading unimplmented register ID_PFR1");
return 0;
case MISCREG_ID_MMFR0:
return 0x03; //VMSAz7
case MISCREG_CTR:
return 0x86468006; // V7, 64 byte cache line, load/exclusive is exact
case MISCREG_ACTLR:

6
src/arch/arm/miscregs.hh
View file

@ -150,6 +150,7 @@ namespace ArmISA
MISCREG_V2POWUR,
MISCREG_V2POWUW,
MISCREG_ID_MMFR0,
MISCREG_ID_MMFR2,
MISCREG_ID_MMFR3,
MISCREG_ACTLR,
MISCREG_PMCR,
@ -181,7 +182,6 @@ namespace ArmISA
MISCREG_ID_DFR0,
MISCREG_ID_AFR0,
MISCREG_ID_MMFR1,
MISCREG_ID_MMFR2,
MISCREG_AIDR,
MISCREG_ADFSR,
MISCREG_AIFSR,
@ -231,7 +231,7 @@ namespace ArmISA
"scr", "sder", "par",
"v2pcwpr", "v2pcwpw", "v2pcwur", "v2pcwuw",
"v2powpr", "v2powpw", "v2powur", "v2powuw",
"id_mmfr0", "id_mmfr3", "actlr", "pmcr", "pmccntr",
"id_mmfr0", "id_mmfr2", "id_mmfr3", "actlr", "pmcr", "pmccntr",
"pmcntenset", "pmcntenclr", "pmovsr",
"pmswinc", "pmselr", "pmceid0",
"pmceid1", "pmc_other", "pmxevcntr",
@ -241,7 +241,7 @@ namespace ArmISA
// Unimplemented below
"tcmtr",
"id_dfr0", "id_afr0",
"id_mmfr1", "id_mmfr2",
"id_mmfr1",
"aidr", "adfsr", "aifsr",
"dcimvac", "dcisw", "mccsw",
"dccmvau",