Only respond if the pkt needs a response.

Fix an issue with memory handling writebacks.

src/mem/cache/base_cache.hh:
src/mem/tport.cc:
    Only respond if the pkt needs a response.
src/mem/physical.cc:
    Make physical memory respond to writebacks, set satisfied for invalidates/upgrades.

--HG--
extra : convert_revision : 7601987a7923e54a6d1a168def4f8133d8de19fd

src/mem/cache/base_cache.hh

@@ -516,9 +516,11 @@ class BaseCache : public MemObject
      */
     void respond(Packet *pkt, Tick time)
     {
+        if (pkt->needsResponse()) {
             CacheEvent *reqCpu = new CacheEvent(cpuSidePort, pkt);
             reqCpu->schedule(time);
         }
+    }
 
     /**
      * Send a reponse to the slave interface and calculate miss latency.
@@ -530,9 +532,11 @@ class BaseCache : public MemObject
         if (!pkt->req->isUncacheable()) {
             missLatency[pkt->cmdToIndex()][0/*pkt->req->getThreadNum()*/] += time - pkt->time;
         }
+        if (pkt->needsResponse()) {
             CacheEvent *reqCpu = new CacheEvent(cpuSidePort, pkt);
             reqCpu->schedule(time);
         }
+    }
 
     /**
      * Suppliess the data if cache to cache transfers are enabled.
@@ -542,6 +546,7 @@ class BaseCache : public MemObject
     {
 //        assert("Implement\n" && 0);
 //	mi->respond(pkt,curTick + hitLatency);
+        assert (pkt->needsResponse());
         CacheEvent *reqMem = new CacheEvent(memSidePort, pkt);
         reqMem->schedule(time);
     }

src/mem/physical.cc

@@ -197,22 +197,25 @@ PhysicalMemory::doFunctionalAccess(Packet *pkt)
 {
     assert(pkt->getAddr() + pkt->getSize() < params()->addrRange.size());
 
-    switch (pkt->cmd) {
+    if (pkt->isRead()) {
-      case Packet::ReadReq:
         if (pkt->req->isLocked()) {
             trackLoadLocked(pkt->req);
         }
         memcpy(pkt->getPtr<uint8_t>(),
                pmemAddr + pkt->getAddr() - params()->addrRange.start,
                pkt->getSize());
-        break;
+    }
-      case Packet::WriteReq:
+    else if (pkt->isWrite()) {
         if (writeOK(pkt->req)) {
             memcpy(pmemAddr + pkt->getAddr() - params()->addrRange.start,
                    pkt->getPtr<uint8_t>(), pkt->getSize());
         }
-        break;
+    }
-      default:
+    else if (pkt->isInvalidate()) {
+        //upgrade or invalidate
+        pkt->flags |= SATISFIED;
+    }
+    else {
         panic("unimplemented");
     }
 

src/mem/tport.cc

@@ -47,9 +47,11 @@ SimpleTimingPort::recvTiming(Packet *pkt)
     // if we ever added it back.
     assert(pkt->result != Packet::Nacked);
     Tick latency = recvAtomic(pkt);
-    // turn packet around to go back to requester
+    // turn packet around to go back to requester if response expected
+    if (pkt->needsResponse()) {
         pkt->makeTimingResponse();
         sendTimingLater(pkt, latency);
+    }
     return true;
 }