sanchayanmaity/gem5
1
0
Fork 0
Code Issues Pull requests Projects Releases Packages Wiki Activity

ARM: Add support for the clidr register.

Browse source 
This register will always report 0 caches as implemented. It's not clear how
to find out how many there really are when dealing with an arbitrary
hierarchy.
This commit is contained in:
Gabe Black 2010-06-02 12:58:09 -05:00
parent 896c7617c4
commit e658b6fed4
2 changed files with 8 additions and 3 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

5
src/arch/arm/isa.hh
View file

@ -164,6 +164,11 @@ namespace ArmISA
panic("Unimplemented CP15 register %s read.\n", panic("Unimplemented CP15 register %s read.\n",
miscRegName[misc_reg]); miscRegName[misc_reg]);
} }
switch (misc_reg) {
case MISCREG_CLIDR:
warn("The clidr register always reports 0 caches.\n");
break;
}
return readMiscRegNoEffect(misc_reg); return readMiscRegNoEffect(misc_reg);
} }

6
src/arch/arm/miscregs.hh
View file

@ -92,6 +92,7 @@ namespace ArmISA
MISCREG_CP15DSB, MISCREG_CP15DSB,
MISCREG_CP15DMB, MISCREG_CP15DMB,
MISCREG_CPACR, MISCREG_CPACR,
MISCREG_CLIDR,
MISCREG_CP15_UNIMP_START, MISCREG_CP15_UNIMP_START,
MISCREG_CTR = MISCREG_CP15_UNIMP_START, MISCREG_CTR = MISCREG_CP15_UNIMP_START,
MISCREG_TCMTR, MISCREG_TCMTR,
@ -113,7 +114,6 @@ namespace ArmISA
MISCREG_ID_ISAR4, MISCREG_ID_ISAR4,
MISCREG_ID_ISAR5, MISCREG_ID_ISAR5,
MISCREG_CCSIDR, MISCREG_CCSIDR,
MISCREG_CLIDR,
MISCREG_AIDR, MISCREG_AIDR,
MISCREG_CSSELR, MISCREG_CSSELR,
MISCREG_ACTLR, MISCREG_ACTLR,
@ -160,12 +160,12 @@ namespace ArmISA
"fpsr", "fpsid", "fpscr", "fpexc", "fpsr", "fpsid", "fpscr", "fpexc",
"sctlr", "dccisw", "dccimvac", "sctlr", "dccisw", "dccimvac",
"contextidr", "tpidrurw", "tpidruro", "tpidrprw", "contextidr", "tpidrurw", "tpidruro", "tpidrprw",
"cp15isb", "cp15dsb", "cp15dmb", "cpacr", "cp15isb", "cp15dsb", "cp15dmb", "cpacr", "clidr",
"ctr", "tcmtr", "mpuir", "mpidr", "midr", "ctr", "tcmtr", "mpuir", "mpidr", "midr",
"id_pfr0", "id_pfr1", "id_dfr0", "id_afr0", "id_pfr0", "id_pfr1", "id_dfr0", "id_afr0",
"id_mmfr0", "id_mmfr1", "id_mmfr2", "id_mmfr3", "id_mmfr0", "id_mmfr1", "id_mmfr2", "id_mmfr3",
"id_isar0", "id_isar1", "id_isar2", "id_isar3", "id_isar4", "id_isar5", "id_isar0", "id_isar1", "id_isar2", "id_isar3", "id_isar4", "id_isar5",
"ccsidr", "clidr", "aidr", "csselr", "actlr", "ccsidr", "aidr", "csselr", "actlr",
"dfsr", "ifsr", "adfsr", "aifsr", "dfar", "ifar", "dfsr", "ifsr", "adfsr", "aifsr", "dfar", "ifar",
"drbar", "irbar", "drsr", "irsr", "dracr", "iracr", "drbar", "irbar", "drsr", "irsr", "dracr", "iracr",
"rgnr", "icialluis", "bpiallis", "iciallu", "icimvau", "rgnr", "icialluis", "bpiallis", "iciallu", "icimvau",