ruby: moved cache stats from Profiler to CacheMemory
Caches are now responsible for their own statistic gathering. This requires a direct callback from the protocol on misses, and so all future protocols need to take this into account.
This commit is contained in:
Derek Hower
parent
308419b947
commit
e59d0e3e89
12 changed files with 557 additions and 561 deletions
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@ -58,6 +58,7 @@ machine(L1Cache, "MI Example L1 Cache"): LATENCY_CACHE_RESPONSE_LATENCY LATENCY
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Entry lookup(Address);
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void changePermission(Address, AccessPermission);
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bool isTagPresent(Address);
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void profileMiss(CacheMsg);
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}
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// TBE fields
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@ -259,6 +260,12 @@ machine(L1Cache, "MI Example L1 Cache"): LATENCY_CACHE_RESPONSE_LATENCY LATENCY
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profileMsgDelay(2, forwardRequestNetwork_in.dequeue_getDelayCycles());
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}
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action(p_profileMiss, "p", desc="Profile cache miss") {
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peek(mandatoryQueue_in, CacheMsg) {
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cacheMemory.profileMiss(in_msg);
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}
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}
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action(r_load_hit, "r", desc="Notify sequencer the load completed.") {
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DEBUG_EXPR(cacheMemory[address].DataBlk);
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sequencer.readCallback(address, cacheMemory[address].DataBlk);
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@ -326,6 +333,7 @@ machine(L1Cache, "MI Example L1 Cache"): LATENCY_CACHE_RESPONSE_LATENCY LATENCY
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v_allocateTBE;
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i_allocateL1CacheBlock;
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a_issueRequest;
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p_profileMiss;
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m_popMandatoryQueue;
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}
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@ -333,6 +341,7 @@ machine(L1Cache, "MI Example L1 Cache"): LATENCY_CACHE_RESPONSE_LATENCY LATENCY
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v_allocateTBE;
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i_allocateL1CacheBlock;
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a_issueRequest;
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p_profileMiss;
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m_popMandatoryQueue;
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}
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@ -48,7 +48,7 @@ CacheProfiler::CacheProfiler(string description)
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{
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m_description = description;
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m_requestTypeVec_ptr = new Vector<int>;
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m_requestTypeVec_ptr->setSize(int(GenericRequestType_NUM));
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m_requestTypeVec_ptr->setSize(int(CacheRequestType_NUM));
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clearStats();
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}
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@ -70,30 +70,22 @@ void CacheProfiler::printStats(ostream& out) const
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out << description << "_total_hw_prefetches: " << m_hw_prefetches << endl;
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double trans_executed = double(g_system_ptr->getProfiler()->getTotalTransactionsExecuted());
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double inst_executed = double(g_system_ptr->getProfiler()->getTotalInstructionsExecuted());
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out << description << "_misses_per_transaction: " << double(m_misses) / trans_executed << endl;
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out << description << "_misses_per_instruction: " << double(m_misses) / inst_executed << endl;
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out << description << "_instructions_per_misses: ";
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if (m_misses > 0) {
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out << inst_executed / double(m_misses) << endl;
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} else {
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out << "NaN" << endl;
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}
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out << endl;
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int requests = 0;
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for(int i=0; i<int(GenericRequestType_NUM); i++) {
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for(int i=0; i<int(CacheRequestType_NUM); i++) {
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requests += m_requestTypeVec_ptr->ref(i);
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}
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assert(m_misses == requests);
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if (requests > 0) {
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for(int i=0; i<int(GenericRequestType_NUM); i++){
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for(int i=0; i<int(CacheRequestType_NUM); i++){
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if (m_requestTypeVec_ptr->ref(i) > 0) {
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out << description << "_request_type_" << GenericRequestType_to_string(GenericRequestType(i)) << ": "
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out << description << "_request_type_" << CacheRequestType_to_string(CacheRequestType(i)) << ": "
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<< (100.0 * double((m_requestTypeVec_ptr->ref(i)))) / double(requests)
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<< "%" << endl;
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}
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@ -116,7 +108,7 @@ void CacheProfiler::printStats(ostream& out) const
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void CacheProfiler::clearStats()
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{
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for(int i=0; i<int(GenericRequestType_NUM); i++) {
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for(int i=0; i<int(CacheRequestType_NUM); i++) {
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m_requestTypeVec_ptr->ref(i) = 0;
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}
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m_requestSize.clear();
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@ -130,7 +122,7 @@ void CacheProfiler::clearStats()
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}
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}
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void CacheProfiler::addStatSample(GenericRequestType requestType, AccessModeType type, int msgSize, PrefetchBit pfBit)
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void CacheProfiler::addStatSample(CacheRequestType requestType, AccessModeType type, int msgSize, PrefetchBit pfBit)
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{
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m_misses++;
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@ -44,7 +44,7 @@
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#include "mem/ruby/common/Histogram.hh"
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#include "mem/protocol/AccessModeType.hh"
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#include "mem/protocol/PrefetchBit.hh"
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#include "mem/protocol/GenericRequestType.hh"
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#include "mem/protocol/CacheRequestType.hh"
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template <class TYPE> class Vector;
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@ -60,7 +60,7 @@ public:
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void printStats(ostream& out) const;
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void clearStats();
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void addStatSample(GenericRequestType requestType, AccessModeType type, int msgSize, PrefetchBit pfBit);
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void addStatSample(CacheRequestType requestType, AccessModeType type, int msgSize, PrefetchBit pfBit);
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void print(ostream& out) const;
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private:
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@ -380,9 +380,9 @@ void Profiler::printStats(ostream& out, bool short_stats)
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out << endl;
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m_L1D_cache_profiler_ptr->printStats(out);
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m_L1I_cache_profiler_ptr->printStats(out);
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m_L2_cache_profiler_ptr->printStats(out);
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// m_L1D_cache_profiler_ptr->printStats(out);
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// m_L1I_cache_profiler_ptr->printStats(out);
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// m_L2_cache_profiler_ptr->printStats(out);
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out << endl;
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@ -773,25 +773,6 @@ void Profiler::clearStats()
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m_ruby_start = g_eventQueue_ptr->getTime();
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}
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void Profiler::addPrimaryStatSample(const CacheMsg& msg, NodeID id)
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{
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if (Protocol::m_TwoLevelCache) {
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if (msg.getType() == CacheRequestType_IFETCH) {
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addL1IStatSample(msg, id);
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} else {
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addL1DStatSample(msg, id);
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}
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// profile the address after an L1 miss (outside of the processor for CMP)
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if (Protocol::m_CMP) {
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addAddressTraceSample(msg, id);
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}
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} else {
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addL2StatSample(CacheRequestType_to_GenericRequestType(msg.getType()),
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msg.getAccessMode(), msg.getSize(), msg.getPrefetch(), id);
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addAddressTraceSample(msg, id);
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}
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}
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void Profiler::profileConflictingRequests(const Address& addr)
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{
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assert(addr == line_address(addr));
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@ -805,39 +786,6 @@ void Profiler::profileConflictingRequests(const Address& addr)
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m_conflicting_map_ptr->add(addr, current_time);
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}
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void Profiler::addSecondaryStatSample(CacheRequestType requestType, AccessModeType type, int msgSize, PrefetchBit pfBit, NodeID id)
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{
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addSecondaryStatSample(CacheRequestType_to_GenericRequestType(requestType), type, msgSize, pfBit, id);
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}
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void Profiler::addSecondaryStatSample(GenericRequestType requestType, AccessModeType type, int msgSize, PrefetchBit pfBit, NodeID id)
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{
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addL2StatSample(requestType, type, msgSize, pfBit, id);
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}
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void Profiler::addL2StatSample(GenericRequestType requestType, AccessModeType type, int msgSize, PrefetchBit pfBit, NodeID id)
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{
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m_perProcTotalMisses[id]++;
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if (type == AccessModeType_SupervisorMode) {
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m_perProcSupervisorMisses[id]++;
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} else {
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m_perProcUserMisses[id]++;
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}
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m_L2_cache_profiler_ptr->addStatSample(requestType, type, msgSize, pfBit);
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}
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void Profiler::addL1DStatSample(const CacheMsg& msg, NodeID id)
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{
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m_L1D_cache_profiler_ptr->addStatSample(CacheRequestType_to_GenericRequestType(msg.getType()),
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msg.getAccessMode(), msg.getSize(), msg.getPrefetch());
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}
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void Profiler::addL1IStatSample(const CacheMsg& msg, NodeID id)
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{
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m_L1I_cache_profiler_ptr->addStatSample(CacheRequestType_to_GenericRequestType(msg.getType()),
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msg.getAccessMode(), msg.getSize(), msg.getPrefetch());
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}
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void Profiler::addAddressTraceSample(const CacheMsg& msg, NodeID id)
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{
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if (msg.getType() != CacheRequestType_IFETCH) {
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@ -1055,30 +1003,6 @@ int64 Profiler::getTotalTransactionsExecuted() const
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}
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// The following case statement converts CacheRequestTypes to GenericRequestTypes
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// allowing all profiling to be done with a single enum type instead of slow strings
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GenericRequestType Profiler::CacheRequestType_to_GenericRequestType(const CacheRequestType& type) {
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switch (type) {
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case CacheRequestType_LD:
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return GenericRequestType_LD;
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break;
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case CacheRequestType_ST:
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return GenericRequestType_ST;
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break;
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case CacheRequestType_ATOMIC:
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return GenericRequestType_ATOMIC;
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break;
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case CacheRequestType_IFETCH:
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return GenericRequestType_IFETCH;
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break;
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case CacheRequestType_NULL:
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return GenericRequestType_NULL;
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break;
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default:
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ERROR_MSG("Unexpected cache request type");
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}
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}
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void Profiler::rubyWatch(int id){
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//int rn_g1 = 0;//SIMICS_get_register_number(id, "g1");
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uint64 tr = 0;//SIMICS_read_register(id, rn_g1);
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@ -126,9 +126,6 @@ public:
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AddressProfiler* getAddressProfiler() { return m_address_profiler_ptr; }
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AddressProfiler* getInstructionProfiler() { return m_inst_profiler_ptr; }
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void addPrimaryStatSample(const CacheMsg& msg, NodeID id);
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void addSecondaryStatSample(GenericRequestType requestType, AccessModeType type, int msgSize, PrefetchBit pfBit, NodeID id);
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void addSecondaryStatSample(CacheRequestType requestType, AccessModeType type, int msgSize, PrefetchBit pfBit, NodeID id);
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void addAddressTraceSample(const CacheMsg& msg, NodeID id);
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void profileRequest(const string& requestStr);
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@ -206,12 +203,6 @@ public:
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private:
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//added by SS
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vector<string> m_memory_control_names;
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// Private Methods
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void addL2StatSample(GenericRequestType requestType, AccessModeType type, int msgSize, PrefetchBit pfBit, NodeID id);
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void addL1DStatSample(const CacheMsg& msg, NodeID id);
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void addL1IStatSample(const CacheMsg& msg, NodeID id);
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GenericRequestType CacheRequestType_to_GenericRequestType(const CacheRequestType& type);
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// Private copy constructor and assignment operator
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Profiler(const Profiler& obj);
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@ -79,33 +79,11 @@ void profile_sharing(const Address& addr, AccessType type, NodeID requestor, con
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g_system_ptr->getProfiler()->profileSharing(addr, type, requestor, sharers, owner);
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}
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void profile_miss(const CacheMsg& msg, NodeID id)
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{
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// CMP profile address after L1 misses, not L2
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ASSERT (!Protocol::m_CMP);
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g_system_ptr->getProfiler()->addAddressTraceSample(msg, id);
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g_system_ptr->getProfiler()->profileConflictingRequests(msg.getLineAddress());
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g_system_ptr->getProfiler()->addSecondaryStatSample(msg.getType(),
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msg.getAccessMode(), msg.getSize(), msg.getPrefetch(), id);
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}
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void profile_L1Cache_miss(const CacheMsg& msg, NodeID id)
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{
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g_system_ptr->getProfiler()->addPrimaryStatSample(msg, id);
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}
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void profileMsgDelay(int virtualNetwork, int delayCycles)
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{
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g_system_ptr->getProfiler()->profileMsgDelay(virtualNetwork, delayCycles);
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}
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void profile_L2Cache_miss(GenericRequestType requestType, AccessModeType type, int msgSize, PrefetchBit pfBit, NodeID nodeID)
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{
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g_system_ptr->getProfiler()->addSecondaryStatSample(requestType, type, msgSize, pfBit, nodeID);
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}
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void profile_token_retry(const Address& addr, AccessType type, int count)
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{
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g_system_ptr->getProfiler()->getAddressProfiler()->profileRetry(addr, type, count);
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@ -52,6 +52,8 @@
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#include "mem/ruby/slicc_interface/AbstractCacheEntry.hh"
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#include "mem/ruby/system/System.hh"
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#include "mem/ruby/slicc_interface/AbstractController.hh"
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#include "mem/ruby/profiler/CacheProfiler.hh"
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#include "mem/protocol/CacheMsg.hh"
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#include <vector>
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class CacheMemory {
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@ -111,6 +113,8 @@ public:
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// Set this address to most recently used
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void setMRU(const Address& address);
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void profileMiss(const CacheMsg & msg);
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void getMemoryValue(const Address& addr, char* value,
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unsigned int size_in_bytes );
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void setMemoryValue(const Address& addr, char* value,
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@ -123,6 +127,8 @@ public:
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void print(ostream& out) const;
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void printData(ostream& out) const;
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void printStats(ostream& out) const;
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private:
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// Private Methods
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@ -154,6 +160,8 @@ private:
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AbstractReplacementPolicy *m_replacementPolicy_ptr;
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CacheProfiler* m_profiler_ptr;
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int m_cache_num_sets;
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int m_cache_num_set_bits;
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int m_cache_assoc;
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@ -182,6 +190,7 @@ inline
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CacheMemory::CacheMemory(const string & name)
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: m_cache_name(name)
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{
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m_profiler_ptr = new CacheProfiler(name);
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}
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inline
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@ -495,6 +504,13 @@ void CacheMemory::setMRU(const Address& address)
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g_eventQueue_ptr->getTime());
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}
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inline
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void CacheMemory::profileMiss(const CacheMsg & msg)
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{
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m_profiler_ptr->addStatSample(msg.getType(), msg.getAccessMode(),
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msg.getSize(), msg.getPrefetch());
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}
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inline
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void CacheMemory::recordCacheContents(CacheRecorder& tr) const
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{
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@ -545,6 +561,12 @@ void CacheMemory::printData(ostream& out) const
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out << "printData() not supported" << endl;
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}
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inline
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void CacheMemory::printStats(ostream& out) const
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{
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m_profiler_ptr->printStats(out);
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}
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inline
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void CacheMemory::getMemoryValue(const Address& addr, char* value,
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unsigned int size_in_bytes ){
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@ -335,6 +335,10 @@ void RubySystem::printStats(ostream& out)
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m_profiler_ptr->printStats(out);
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m_network_ptr->printStats(out);
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for (map<string, CacheMemory*>::const_iterator it = m_caches.begin();
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it != m_caches.end(); it++) {
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(*it).second->printStats(out);
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}
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for (map<string, AbstractController*>::const_iterator it = m_controllers.begin();
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it != m_controllers.end(); it++) {
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(*it).second->printStats(out);
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File diff suppressed because it is too large
Load diff
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@ -1,76 +1,76 @@
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["-r", "tests/configs/../../src/mem/ruby/config/MI_example-homogeneous.rb", "-p", "8", "-m", "1", "-s", "1024"]
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print config: 1
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system.cpu1: completed 10000 read accesses @3641101
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system.cpu6: completed 10000 read accesses @3657885
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system.cpu0: completed 10000 read accesses @3682054
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system.cpu4: completed 10000 read accesses @3686756
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system.cpu3: completed 10000 read accesses @3686791
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system.cpu2: completed 10000 read accesses @3714721
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system.cpu5: completed 10000 read accesses @3718986
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system.cpu7: completed 10000 read accesses @3739388
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system.cpu1: completed 20000 read accesses @6773990
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system.cpu4: completed 20000 read accesses @6790313
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system.cpu0: completed 20000 read accesses @6796672
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system.cpu3: completed 20000 read accesses @6797278
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system.cpu6: completed 20000 read accesses @6823694
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system.cpu2: completed 20000 read accesses @6833547
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system.cpu5: completed 20000 read accesses @6854676
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system.cpu7: completed 20000 read accesses @6875905
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system.cpu1: completed 30000 read accesses @9853256
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system.cpu3: completed 30000 read accesses @9906665
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system.cpu0: completed 30000 read accesses @9931557
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system.cpu4: completed 30000 read accesses @9952518
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system.cpu5: completed 30000 read accesses @9976242
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system.cpu2: completed 30000 read accesses @9981306
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system.cpu6: completed 30000 read accesses @10008066
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system.cpu7: completed 30000 read accesses @10011960
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system.cpu1: completed 40000 read accesses @13015878
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system.cpu3: completed 40000 read accesses @13040111
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system.cpu5: completed 40000 read accesses @13079687
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system.cpu0: completed 40000 read accesses @13099309
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system.cpu2: completed 40000 read accesses @13115004
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system.cpu4: completed 40000 read accesses @13143910
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system.cpu6: completed 40000 read accesses @13150020
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system.cpu7: completed 40000 read accesses @13161356
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system.cpu3: completed 50000 read accesses @16125452
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system.cpu1: completed 50000 read accesses @16181745
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system.cpu5: completed 50000 read accesses @16184066
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system.cpu0: completed 50000 read accesses @16216286
|
||||
system.cpu2: completed 50000 read accesses @16257216
|
||||
system.cpu4: completed 50000 read accesses @16263973
|
||||
system.cpu6: completed 50000 read accesses @16288792
|
||||
system.cpu7: completed 50000 read accesses @16318993
|
||||
system.cpu3: completed 60000 read accesses @19283536
|
||||
system.cpu0: completed 60000 read accesses @19309937
|
||||
system.cpu1: completed 60000 read accesses @19317676
|
||||
system.cpu2: completed 60000 read accesses @19325470
|
||||
system.cpu5: completed 60000 read accesses @19327514
|
||||
system.cpu6: completed 60000 read accesses @19417822
|
||||
system.cpu4: completed 60000 read accesses @19447479
|
||||
system.cpu7: completed 60000 read accesses @19480386
|
||||
system.cpu0: completed 70000 read accesses @22411174
|
||||
system.cpu3: completed 70000 read accesses @22411178
|
||||
system.cpu2: completed 70000 read accesses @22414508
|
||||
system.cpu5: completed 70000 read accesses @22453684
|
||||
system.cpu1: completed 70000 read accesses @22473724
|
||||
system.cpu4: completed 70000 read accesses @22564254
|
||||
system.cpu6: completed 70000 read accesses @22590390
|
||||
system.cpu7: completed 70000 read accesses @22646034
|
||||
system.cpu3: completed 80000 read accesses @25536114
|
||||
system.cpu0: completed 80000 read accesses @25565410
|
||||
system.cpu2: completed 80000 read accesses @25581306
|
||||
system.cpu1: completed 80000 read accesses @25643150
|
||||
system.cpu5: completed 80000 read accesses @25659302
|
||||
system.cpu4: completed 80000 read accesses @25672250
|
||||
system.cpu6: completed 80000 read accesses @25729734
|
||||
system.cpu7: completed 80000 read accesses @25780094
|
||||
system.cpu3: completed 90000 read accesses @28701520
|
||||
system.cpu2: completed 90000 read accesses @28736898
|
||||
system.cpu0: completed 90000 read accesses @28740612
|
||||
system.cpu5: completed 90000 read accesses @28751484
|
||||
system.cpu1: completed 90000 read accesses @28768980
|
||||
system.cpu4: completed 90000 read accesses @28819348
|
||||
system.cpu6: completed 90000 read accesses @28888794
|
||||
system.cpu7: completed 90000 read accesses @28938947
|
||||
system.cpu3: completed 100000 read accesses @31820150
|
||||
system.cpu1: completed 10000 read accesses @3663630
|
||||
system.cpu2: completed 10000 read accesses @3663638
|
||||
system.cpu5: completed 10000 read accesses @3680002
|
||||
system.cpu7: completed 10000 read accesses @3691164
|
||||
system.cpu3: completed 10000 read accesses @3698130
|
||||
system.cpu4: completed 10000 read accesses @3701748
|
||||
system.cpu6: completed 10000 read accesses @3704092
|
||||
system.cpu0: completed 10000 read accesses @3742302
|
||||
system.cpu2: completed 20000 read accesses @6788966
|
||||
system.cpu7: completed 20000 read accesses @6816416
|
||||
system.cpu5: completed 20000 read accesses @6822351
|
||||
system.cpu4: completed 20000 read accesses @6824056
|
||||
system.cpu1: completed 20000 read accesses @6825604
|
||||
system.cpu3: completed 20000 read accesses @6829578
|
||||
system.cpu6: completed 20000 read accesses @6857232
|
||||
system.cpu0: completed 20000 read accesses @6872452
|
||||
system.cpu5: completed 30000 read accesses @9928492
|
||||
system.cpu2: completed 30000 read accesses @9933192
|
||||
system.cpu7: completed 30000 read accesses @9950074
|
||||
system.cpu4: completed 30000 read accesses @9965775
|
||||
system.cpu6: completed 30000 read accesses @9978835
|
||||
system.cpu0: completed 30000 read accesses @9993926
|
||||
system.cpu1: completed 30000 read accesses @9994767
|
||||
system.cpu3: completed 30000 read accesses @9996366
|
||||
system.cpu5: completed 40000 read accesses @13012070
|
||||
system.cpu2: completed 40000 read accesses @13044972
|
||||
system.cpu7: completed 40000 read accesses @13077010
|
||||
system.cpu4: completed 40000 read accesses @13081178
|
||||
system.cpu1: completed 40000 read accesses @13100740
|
||||
system.cpu0: completed 40000 read accesses @13111135
|
||||
system.cpu6: completed 40000 read accesses @13147706
|
||||
system.cpu3: completed 40000 read accesses @13153176
|
||||
system.cpu5: completed 50000 read accesses @16120762
|
||||
system.cpu2: completed 50000 read accesses @16176586
|
||||
system.cpu7: completed 50000 read accesses @16213417
|
||||
system.cpu4: completed 50000 read accesses @16219872
|
||||
system.cpu6: completed 50000 read accesses @16231538
|
||||
system.cpu1: completed 50000 read accesses @16246976
|
||||
system.cpu3: completed 50000 read accesses @16276612
|
||||
system.cpu0: completed 50000 read accesses @16293234
|
||||
system.cpu5: completed 60000 read accesses @19263804
|
||||
system.cpu4: completed 60000 read accesses @19313220
|
||||
system.cpu2: completed 60000 read accesses @19330470
|
||||
system.cpu7: completed 60000 read accesses @19340197
|
||||
system.cpu6: completed 60000 read accesses @19399766
|
||||
system.cpu0: completed 60000 read accesses @19424570
|
||||
system.cpu1: completed 60000 read accesses @19425712
|
||||
system.cpu3: completed 60000 read accesses @19444952
|
||||
system.cpu5: completed 70000 read accesses @22408750
|
||||
system.cpu4: completed 70000 read accesses @22449746
|
||||
system.cpu7: completed 70000 read accesses @22451736
|
||||
system.cpu2: completed 70000 read accesses @22461052
|
||||
system.cpu0: completed 70000 read accesses @22554296
|
||||
system.cpu1: completed 70000 read accesses @22555310
|
||||
system.cpu3: completed 70000 read accesses @22588935
|
||||
system.cpu6: completed 70000 read accesses @22602456
|
||||
system.cpu5: completed 80000 read accesses @25540598
|
||||
system.cpu4: completed 80000 read accesses @25577430
|
||||
system.cpu7: completed 80000 read accesses @25617532
|
||||
system.cpu1: completed 80000 read accesses @25644879
|
||||
system.cpu2: completed 80000 read accesses @25660256
|
||||
system.cpu0: completed 80000 read accesses @25710799
|
||||
system.cpu3: completed 80000 read accesses @25716714
|
||||
system.cpu6: completed 80000 read accesses @25776606
|
||||
system.cpu5: completed 90000 read accesses @28693458
|
||||
system.cpu4: completed 90000 read accesses @28705416
|
||||
system.cpu7: completed 90000 read accesses @28729734
|
||||
system.cpu1: completed 90000 read accesses @28778532
|
||||
system.cpu2: completed 90000 read accesses @28801770
|
||||
system.cpu0: completed 90000 read accesses @28857559
|
||||
system.cpu6: completed 90000 read accesses @28885159
|
||||
system.cpu3: completed 90000 read accesses @28894168
|
||||
system.cpu7: completed 100000 read accesses @31814464
|
||||
hack: be nice to actually delete the event here
|
||||
|
|
|
|||
|
|
@ -5,11 +5,11 @@ The Regents of The University of Michigan
|
|||
All Rights Reserved
|
||||
|
||||
|
||||
M5 compiled Jul 13 2009 11:01:42
|
||||
M5 revision 57650468aff1+ 6297+ default
|
||||
M5 started Jul 13 2009 11:01:45
|
||||
M5 compiled Jul 19 2009 14:52:18
|
||||
M5 revision 544d33334ee1+ 6369+ default tip
|
||||
M5 started Jul 19 2009 14:52:23
|
||||
M5 executing on clover-01.cs.wisc.edu
|
||||
command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/50.memtest/alpha/linux/memtest-ruby -re tests/run.py build/ALPHA_SE/tests/fast/quick/50.memtest/alpha/linux/memtest-ruby
|
||||
Global frequency set at 1000000000000 ticks per second
|
||||
info: Entering event queue @ 0. Starting simulation...
|
||||
Exiting @ tick 31820150 because maximum number of loads reached
|
||||
Exiting @ tick 31814464 because maximum number of loads reached
|
||||
|
|
|
|||
|
|
@ -1,34 +1,34 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
host_mem_usage 1538632 # Number of bytes of host memory used
|
||||
host_seconds 2021.99 # Real time elapsed on the host
|
||||
host_tick_rate 15737 # Simulator tick rate (ticks/s)
|
||||
host_mem_usage 1538656 # Number of bytes of host memory used
|
||||
host_seconds 2552.36 # Real time elapsed on the host
|
||||
host_tick_rate 12465 # Simulator tick rate (ticks/s)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
sim_seconds 0.000032 # Number of seconds simulated
|
||||
sim_ticks 31820150 # Number of ticks simulated
|
||||
sim_ticks 31814464 # Number of ticks simulated
|
||||
system.cpu0.num_copies 0 # number of copy accesses completed
|
||||
system.cpu0.num_reads 99856 # number of read accesses completed
|
||||
system.cpu0.num_writes 53852 # number of write accesses completed
|
||||
system.cpu0.num_reads 99342 # number of read accesses completed
|
||||
system.cpu0.num_writes 53699 # number of write accesses completed
|
||||
system.cpu1.num_copies 0 # number of copy accesses completed
|
||||
system.cpu1.num_reads 99692 # number of read accesses completed
|
||||
system.cpu1.num_writes 53561 # number of write accesses completed
|
||||
system.cpu1.num_reads 99812 # number of read accesses completed
|
||||
system.cpu1.num_writes 53757 # number of write accesses completed
|
||||
system.cpu2.num_copies 0 # number of copy accesses completed
|
||||
system.cpu2.num_reads 99805 # number of read accesses completed
|
||||
system.cpu2.num_writes 53565 # number of write accesses completed
|
||||
system.cpu2.num_reads 99597 # number of read accesses completed
|
||||
system.cpu2.num_writes 53671 # number of write accesses completed
|
||||
system.cpu3.num_copies 0 # number of copy accesses completed
|
||||
system.cpu3.num_reads 100000 # number of read accesses completed
|
||||
system.cpu3.num_writes 53663 # number of write accesses completed
|
||||
system.cpu3.num_reads 99365 # number of read accesses completed
|
||||
system.cpu3.num_writes 53444 # number of write accesses completed
|
||||
system.cpu4.num_copies 0 # number of copy accesses completed
|
||||
system.cpu4.num_reads 99420 # number of read accesses completed
|
||||
system.cpu4.num_writes 53889 # number of write accesses completed
|
||||
system.cpu4.num_reads 99713 # number of read accesses completed
|
||||
system.cpu4.num_writes 54044 # number of write accesses completed
|
||||
system.cpu5.num_copies 0 # number of copy accesses completed
|
||||
system.cpu5.num_reads 99788 # number of read accesses completed
|
||||
system.cpu5.num_writes 53529 # number of write accesses completed
|
||||
system.cpu5.num_reads 99943 # number of read accesses completed
|
||||
system.cpu5.num_writes 53789 # number of write accesses completed
|
||||
system.cpu6.num_copies 0 # number of copy accesses completed
|
||||
system.cpu6.num_reads 99210 # number of read accesses completed
|
||||
system.cpu6.num_writes 53902 # number of write accesses completed
|
||||
system.cpu6.num_reads 99307 # number of read accesses completed
|
||||
system.cpu6.num_writes 53603 # number of write accesses completed
|
||||
system.cpu7.num_copies 0 # number of copy accesses completed
|
||||
system.cpu7.num_reads 99182 # number of read accesses completed
|
||||
system.cpu7.num_writes 54075 # number of write accesses completed
|
||||
system.cpu7.num_reads 100000 # number of read accesses completed
|
||||
system.cpu7.num_writes 53881 # number of write accesses completed
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
Loading…
Reference in a new issue