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inorder: add necessary debug flag header files

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This commit is contained in:
Korey Sewell 2011-06-19 21:43:41 -04:00
parent 59686795e3
commit e572c01120
7 changed files with 9 additions and 8 deletions
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1
src/cpu/inorder/cpu.cc
View file

@ -52,6 +52,7 @@
#include "debug/InOrderCPU.hh" #include "debug/InOrderCPU.hh"
#include "debug/RefCount.hh" #include "debug/RefCount.hh"
#include "debug/SkedCache.hh" #include "debug/SkedCache.hh"
#include "debug/Quiesce.hh"
#include "mem/translating_port.hh" #include "mem/translating_port.hh"
#include "params/InOrderCPU.hh" #include "params/InOrderCPU.hh"
#include "sim/process.hh" #include "sim/process.hh"

1
src/cpu/inorder/resource.cc
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@ -36,6 +36,7 @@
#include "cpu/inorder/cpu.hh" #include "cpu/inorder/cpu.hh"
#include "cpu/inorder/resource.hh" #include "cpu/inorder/resource.hh"
#include "cpu/inorder/resource_pool.hh" #include "cpu/inorder/resource_pool.hh"
#include "debug/ExecFaulting.hh"
#include "debug/RefCount.hh" #include "debug/RefCount.hh"
#include "debug/ResReqCount.hh" #include "debug/ResReqCount.hh"
#include "debug/Resource.hh" #include "debug/Resource.hh"

1
src/cpu/inorder/resources/branch_predictor.cc
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@ -33,6 +33,7 @@
#include "cpu/inorder/resources/branch_predictor.hh" #include "cpu/inorder/resources/branch_predictor.hh"
#include "debug/InOrderBPred.hh" #include "debug/InOrderBPred.hh"
#include "debug/InOrderStage.hh" #include "debug/InOrderStage.hh"
#include "debug/Resource.hh"
using namespace std; using namespace std;
using namespace TheISA; using namespace TheISA;

4
src/cpu/inorder/resources/cache_unit.cc
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@ -98,7 +98,7 @@ CacheUnit::CachePort::recvStatusChange(Status status)
bool bool
CacheUnit::CachePort::recvTiming(Packet *pkt) CacheUnit::CachePort::recvTiming(Packet *pkt)
{ {
DPRINTF(Cache, "RecvTiming: Pkt %x,\n", pkt->getAddr()); DPRINTF(InOrderCachePort, "RecvTiming: Pkt %x,\n", pkt->getAddr());
if (pkt->isError()) if (pkt->isError())
DPRINTF(InOrderCachePort, "Got error packet back for address: %x\n", DPRINTF(InOrderCachePort, "Got error packet back for address: %x\n",
@ -1218,7 +1218,7 @@ CacheUnitEvent::process()
//@todo: eventually, we should do a timing translation w/ //@todo: eventually, we should do a timing translation w/
// hw page table walk on tlb miss // hw page table walk on tlb miss
DPRINTF(Fault, "Handling Fault %s : [sn:%i] %x\n", inst->fault->name(), inst->seqNum, inst->getMemAddr()); DPRINTF(InOrderTLB, "Handling Fault %s : [sn:%i] %x\n", inst->fault->name(), inst->seqNum, inst->getMemAddr());
inst->fault->invoke(tlb_res->cpu->tcBase(tid), inst->staticInst); inst->fault->invoke(tlb_res->cpu->tcBase(tid), inst->staticInst);
tlb_res->tlbBlocked[tid] = false; tlb_res->tlbBlocked[tid] = false;

4
src/cpu/inorder/resources/decode_unit.cc
View file

@ -62,12 +62,12 @@ DecodeUnit::execute(int slot_num)
if (inst->fault != NoFault) { if (inst->fault != NoFault) {
inst->setBackSked(cpu->faultSked); inst->setBackSked(cpu->faultSked);
DPRINTF(Decode,"[tid:%i]: Fault found for instruction [sn:%i]\n", DPRINTF(InOrderDecode,"[tid:%i]: Fault found for instruction [sn:%i]\n",
inst->readTid(), inst->seqNum); inst->readTid(), inst->seqNum);
} else { } else {
assert(!inst->staticInst->isMacroop()); assert(!inst->staticInst->isMacroop());
inst->setBackSked(cpu->createBackEndSked(inst)); inst->setBackSked(cpu->createBackEndSked(inst));
DPRINTF(Decode,"Decoded instruction [sn:%i]: %s : 0x%x\n", DPRINTF(InOrderDecode,"Decoded instruction [sn:%i]: %s : 0x%x\n",
inst->seqNum, inst->instName(), inst->seqNum, inst->instName(),
inst->staticInst->machInst); inst->staticInst->machInst);
} }

1
src/cpu/inorder/resources/execution_unit.cc
View file

@ -35,6 +35,7 @@
#include "cpu/inorder/resources/execution_unit.hh" #include "cpu/inorder/resources/execution_unit.hh"
#include "cpu/inorder/cpu.hh" #include "cpu/inorder/cpu.hh"
#include "cpu/inorder/resource_pool.hh" #include "cpu/inorder/resource_pool.hh"
#include "debug/Fault.hh"
#include "debug/InOrderExecute.hh" #include "debug/InOrderExecute.hh"
#include "debug/InOrderStall.hh" #include "debug/InOrderStall.hh"

5
src/cpu/inorder/resources/fetch_seq_unit.cc
View file

@ -209,13 +209,10 @@ FetchSeqUnit::squash(DynInstPtr inst, int squash_stage,
} }
if (bdelay_inst) { if (bdelay_inst) {
DPRINTF(Resource, "Evaluating %s v. %s\n",
bdelay_inst->pc, nextPC);
if (bdelay_inst->pc.instAddr() == nextPC.instAddr()) { if (bdelay_inst->pc.instAddr() == nextPC.instAddr()) {
bdelay_inst->pc = nextPC; bdelay_inst->pc = nextPC;
advancePC(nextPC, inst->staticInst); advancePC(nextPC, inst->staticInst);
DPRINTF(Resource, "Advanced PC to %s\n", nextPC); DPRINTF(InOrderFetchSeq, "Advanced PC to %s\n", nextPC);
} }
} }
} else { } else {