mem: Page Table long lines
Trimmed down all the lines greater than 78 characters.
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4 changed files with 24 additions and 12 deletions
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@ -141,7 +141,8 @@ class MultiLevelPageTable : public PageTableBase
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bool walk(Addr vaddr, bool allocate, Addr &PTE_addr);
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public:
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MultiLevelPageTable(const std::string &__name, uint64_t _pid, System *_sys);
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MultiLevelPageTable(const std::string &__name, uint64_t _pid,
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System *_sys);
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~MultiLevelPageTable();
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void initState(ThreadContext* tc);
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@ -49,7 +49,8 @@ using namespace std;
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using namespace TheISA;
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template <class ISAOps>
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MultiLevelPageTable<ISAOps>::MultiLevelPageTable(const std::string &__name, uint64_t _pid, System *_sys)
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MultiLevelPageTable<ISAOps>::MultiLevelPageTable(const std::string &__name,
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uint64_t _pid, System *_sys)
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: PageTableBase(__name, _pid), system(_sys),
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logLevelSize(PageTableLayout),
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numLevels(logLevelSize.size())
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@ -109,7 +110,8 @@ MultiLevelPageTable<ISAOps>::walk(Addr vaddr, bool allocate, Addr &PTE_addr)
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assert(log_req_size >= PageShift);
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uint64_t npages = 1 << (log_req_size - PageShift);
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DPRINTF(MMU, "Allocating %d pages needed for entry in level %d\n", npages, i-1);
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DPRINTF(MMU, "Allocating %d pages needed for entry in level %d\n",
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npages, i - 1);
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/* allocate new entry */
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Addr next_entry_paddr = system->allocPhysPages(npages);
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@ -121,7 +123,8 @@ MultiLevelPageTable<ISAOps>::walk(Addr vaddr, bool allocate, Addr &PTE_addr)
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p.write<PageTableEntry>(entry_addr, entry);
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}
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DPRINTF(MMU, "Level %d base: %d offset: %d entry: %d\n", i, level_base, offsets[i], next_entry_pnum);
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DPRINTF(MMU, "Level %d base: %d offset: %d entry: %d\n",
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i, level_base, offsets[i], next_entry_pnum);
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level_base = next_entry_pnum;
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}
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@ -133,7 +136,8 @@ MultiLevelPageTable<ISAOps>::walk(Addr vaddr, bool allocate, Addr &PTE_addr)
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template <class ISAOps>
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void
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MultiLevelPageTable<ISAOps>::map(Addr vaddr, Addr paddr, int64_t size, bool clobber)
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MultiLevelPageTable<ISAOps>::map(Addr vaddr, Addr paddr,
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int64_t size, bool clobber)
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{
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// starting address must be page aligned
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assert(pageOffset(vaddr) == 0);
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@ -153,7 +157,7 @@ MultiLevelPageTable<ISAOps>::map(Addr vaddr, Addr paddr, int64_t size, bool clob
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p.write<PageTableEntry>(PTE_addr, PTE);
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DPRINTF(MMU, "New mapping: %#x-%#x\n", vaddr, paddr);
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} else {
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fatal("address 0x%x already mapped to %x", vaddr, entry_paddr);
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fatal("addr 0x%x already mapped to %x", vaddr, entry_paddr);
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}
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eraseCacheEntry(vaddr);
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@ -175,7 +179,9 @@ MultiLevelPageTable<ISAOps>::remap(Addr vaddr, int64_t size, Addr new_vaddr)
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PortProxy &p = system->physProxy;
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for (; size > 0; size -= pageSize, vaddr += pageSize, new_vaddr += pageSize) {
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for (; size > 0;
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size -= pageSize, vaddr += pageSize, new_vaddr += pageSize)
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{
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Addr PTE_addr;
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if (walk(vaddr, false, PTE_addr)) {
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PageTableEntry PTE = p.read<PageTableEntry>(PTE_addr);
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@ -306,7 +312,8 @@ MultiLevelPageTable<ISAOps>::serialize(std::ostream &os)
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template <class ISAOps>
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void
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MultiLevelPageTable<ISAOps>::unserialize(Checkpoint *cp, const std::string §ion)
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MultiLevelPageTable<ISAOps>::unserialize(Checkpoint *cp,
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const std::string §ion)
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{
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paramIn(cp, section, "ptable.pointer", basePtr);
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}
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@ -51,7 +51,8 @@
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using namespace std;
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using namespace TheISA;
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FuncPageTable::FuncPageTable(const std::string &__name, uint64_t _pid, Addr _pageSize)
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FuncPageTable::FuncPageTable(const std::string &__name,
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uint64_t _pid, Addr _pageSize)
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: PageTableBase(__name, _pid, _pageSize)
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{
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}
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@ -71,7 +72,7 @@ FuncPageTable::map(Addr vaddr, Addr paddr, int64_t size, bool clobber)
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for (; size > 0; size -= pageSize, vaddr += pageSize, paddr += pageSize) {
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if (!clobber && (pTable.find(vaddr) != pTable.end())) {
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// already mapped
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fatal("FuncPageTable::allocate: address 0x%x already mapped", vaddr);
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fatal("FuncPageTable::allocate: addr 0x%x already mapped", vaddr);
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}
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pTable[vaddr] = TheISA::TlbEntry(pid, vaddr, paddr);
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@ -89,7 +90,9 @@ FuncPageTable::remap(Addr vaddr, int64_t size, Addr new_vaddr)
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DPRINTF(MMU, "moving pages from vaddr %08p to %08p, size = %d\n", vaddr,
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new_vaddr, size);
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for (; size > 0; size -= pageSize, vaddr += pageSize, new_vaddr += pageSize) {
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for (; size > 0;
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size -= pageSize, vaddr += pageSize, new_vaddr += pageSize)
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{
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assert(pTable.find(vaddr) != pTable.end());
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pTable[new_vaddr] = pTable[vaddr];
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@ -93,7 +93,8 @@ class PageTableBase
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Addr pageAlign(Addr a) { return (a & ~offsetMask); }
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Addr pageOffset(Addr a) { return (a & offsetMask); }
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virtual void map(Addr vaddr, Addr paddr, int64_t size, bool clobber = false) = 0;
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virtual void map(Addr vaddr, Addr paddr, int64_t size,
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bool clobber = false) = 0;
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virtual void remap(Addr vaddr, int64_t size, Addr new_vaddr) = 0;
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virtual void unmap(Addr vaddr, int64_t size) = 0;
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