Make mulitple consoles work and be distinguishable from each other

src/dev/alpha/tsunamireg.h:
    get rid of things that aren't really tsunami registers
src/dev/platform.hh:
src/dev/uart.cc:
    the uart pointer isn't used anymore
src/dev/simconsole.cc:
    make the simconsole print something more useful to distinguish between various consoles in a single system
src/dev/uart8250.hh:
    put the needed uart defines in here rather than including them from tsunamireg
src/python/m5/objects/T1000.py:
    add a console to the T1000 config for the hypervisor

--HG--
extra : convert_revision : 76ca92122e611eaf76b989bc699582eef8297be8
This commit is contained in:
Ali Saidi 2007-02-13 15:58:06 -05:00
parent dc7ef3d489
commit e3dcbc94f7
6 changed files with 22 additions and 28 deletions

View file

@ -136,15 +136,6 @@
/* Added for keyboard accesses */ /* Added for keyboard accesses */
#define TSDEV_KBD 0x64 #define TSDEV_KBD 0x64
/* Added for ATA PCI DMA */
#define ATA_PCI_DMA 0x00
#define ATA_PCI_DMA2 0x02
#define ATA_PCI_DMA3 0x16
#define ATA_PCI_DMA4 0x17
#define ATA_PCI_DMA5 0x1a
#define ATA_PCI_DMA6 0x11
#define ATA_PCI_DMA7 0x14
#define TSDEV_RTC_ADDR 0x70 #define TSDEV_RTC_ADDR 0x70
#define TSDEV_RTC_DATA 0x71 #define TSDEV_RTC_DATA 0x71
@ -155,18 +146,6 @@
#define TSUNAMI_PCI0_IO TSUNAMI_UNCACHABLE_BIT + PCHIP_PCI0_IO #define TSUNAMI_PCI0_IO TSUNAMI_UNCACHABLE_BIT + PCHIP_PCI0_IO
// UART Defines
#define UART_IER_RDI 0x01
#define UART_IER_THRI 0x02
#define UART_IER_RLSI 0x04
#define UART_LSR_TEMT 0x40
#define UART_LSR_THRE 0x20
#define UART_LSR_DR 0x01
#define UART_MCR_LOOP 0x10
// System Control PortB Status Bits // System Control PortB Status Bits
#define PORTB_SPKR_HIGH 0x20 #define PORTB_SPKR_HIGH 0x20

View file

@ -55,9 +55,6 @@ class Platform : public SimObject
/** Pointer to the interrupt controller */ /** Pointer to the interrupt controller */
IntrControl *intrctrl; IntrControl *intrctrl;
/** Pointer to the UART, set by the uart */
Uart *uart;
/** Pointer to the system for info about the memory system. */ /** Pointer to the system for info about the memory system. */
System *system; System *system;

View file

@ -364,7 +364,12 @@ ConsoleListener::listen(int port)
port++; port++;
} }
ccprintf(cerr, "Listening for console connection on port %d\n", port);
int p1, p2;
p2 = name().rfind('.') - 1;
p1 = name().rfind('.', p2);
ccprintf(cerr, "Listening for %s connection on port %d\n",
name().substr(p1+1,p2-p1), port);
event = new Event(this, listener.getfd(), POLLIN); event = new Event(this, listener.getfd(), POLLIN);
pollQueue.schedule(event); pollQueue.schedule(event);

View file

@ -47,7 +47,6 @@ Uart::Uart(Params *p)
// set back pointers // set back pointers
cons->uart = this; cons->uart = this;
platform->uart = this;
} }
DEFINE_SIM_OBJECT_CLASS_NAME("Uart", Uart) DEFINE_SIM_OBJECT_CLASS_NAME("Uart", Uart)

View file

@ -35,7 +35,6 @@
#ifndef __DEV_UART8250_HH__ #ifndef __DEV_UART8250_HH__
#define __DEV_UART8250_HH__ #define __DEV_UART8250_HH__
#include "dev/alpha/tsunamireg.h"
#include "base/range.hh" #include "base/range.hh"
#include "dev/io_device.hh" #include "dev/io_device.hh"
#include "dev/uart.hh" #include "dev/uart.hh"
@ -54,6 +53,18 @@ const uint8_t IIR_TXID = 0x02; /* Tx Data */
const uint8_t IIR_RXID = 0x04; /* Rx Data */ const uint8_t IIR_RXID = 0x04; /* Rx Data */
const uint8_t IIR_LINE = 0x06; /* Rx Line Status (highest priority)*/ const uint8_t IIR_LINE = 0x06; /* Rx Line Status (highest priority)*/
const uint8_t UART_IER_RDI = 0x01;
const uint8_t UART_IER_THRI = 0x02;
const uint8_t UART_IER_RLSI = 0x04;
const uint8_t UART_LSR_TEMT = 0x40;
const uint8_t UART_LSR_THRE = 0x20;
const uint8_t UART_LSR_DR = 0x01;
const uint8_t UART_MCR_LOOP = 0x10;
class SimConsole; class SimConsole;
class Platform; class Platform;

View file

@ -69,16 +69,19 @@ class T1000(Platform):
fake_ssi = IsaFake(pio_addr=0xff00000000, pio_size=0x10000000) fake_ssi = IsaFake(pio_addr=0xff00000000, pio_size=0x10000000)
#warn_access="Accessing SSI -- Unimplemented!") #warn_access="Accessing SSI -- Unimplemented!")
hconsole = SimConsole(listener = ConsoleListener())
hvuart = Uart8250(pio_addr=0xfff0c2c000) hvuart = Uart8250(pio_addr=0xfff0c2c000)
htod = DumbTOD() htod = DumbTOD()
pconsole = SimConsole(listener = ConsoleListener())
puart0 = Uart8250(pio_addr=0x1f10000000) puart0 = Uart8250(pio_addr=0x1f10000000)
console = SimConsole(listener = ConsoleListener())
# Attach I/O devices to specified bus object. Can't do this # Attach I/O devices to specified bus object. Can't do this
# earlier, since the bus object itself is typically defined at the # earlier, since the bus object itself is typically defined at the
# System level. # System level.
def attachIO(self, bus): def attachIO(self, bus):
self.hvuart.sim_console = self.hconsole
self.puart0.sim_console = self.pconsole
self.fake_clk.pio = bus.port self.fake_clk.pio = bus.port
self.fake_membnks.pio = bus.port self.fake_membnks.pio = bus.port
self.fake_iob.pio = bus.port self.fake_iob.pio = bus.port