Merge zizzer:/bk/m5

into  zeep.eecs.umich.edu:/z/saidi/work/m5.head

cpu/simple/cpu.cc:
    remove initCPU from constructor
dev/alpha_console.cc:
    we are panicing, so no need to return a fault

--HG--
extra : convert_revision : 72389ea0c96e91a55f35b884200325224bfb6ed9

arch/alpha/ev5.cc

@@ -70,13 +70,16 @@ AlphaISA::swap_palshadow(RegFile *regs, bool use_shadow)
 //  Machine dependent functions
 //
 void
-AlphaISA::initCPU(RegFile *regs)
+AlphaISA::initCPU(RegFile *regs, int cpuId)
 {
-    initIPRs(regs);
+    initIPRs(regs, cpuId);
     // CPU comes up with PAL regs enabled
     swap_palshadow(regs, true);
 
-    regs->pc = regs->ipr[IPR_PAL_BASE] + fault_addr(ResetFault);
+    regs->intRegFile[16] = cpuId;
+    regs->intRegFile[0] = cpuId;
+
+    regs->pc = regs->ipr[IPR_PAL_BASE] + fault_addr[Reset_Fault];
     regs->npc = regs->pc + sizeof(MachInst);
 }
 
@@ -84,15 +87,25 @@ AlphaISA::initCPU(RegFile *regs)
 //
 // alpha exceptions - value equals trap address, update with MD_FAULT_TYPE
 //
-const Addr
+Addr
-AlphaISA::fault_addr(Fault fault)
+AlphaISA::fault_addr[Num_Faults] = {
-{
+    0x0000,	/* No_Fault */
-        //Check for the system wide faults
+    0x0001,	/* Reset_Fault */
-        if(fault == NoFault) return 0x0000;
+    0x0401,	/* Machine_Check_Fault */
-        else if(fault == MachineCheckFault) return 0x0401;
+    0x0501,	/* Arithmetic_Fault */
-        else if(fault == AlignmentFault) return 0x0301;
+    0x0101,	/* Interrupt_Fault */
-        //Deal with the alpha specific faults
+    0x0201,	/* Ndtb_Miss_Fault */
-        return ((AlphaFault*)fault)->vect;
+    0x0281,	/* Pdtb_Miss_Fault */
+    0x0301,	/* Alignment_Fault */
+    0x0381,	/* DTB_Fault_Fault */
+    0x0381,	/* DTB_Acv_Fault */
+    0x0181,	/* ITB_Miss_Fault */
+    0x0181,	/* ITB_Fault_Fault */
+    0x0081,	/* ITB_Acv_Fault */
+    0x0481,	/* Unimplemented_Opcode_Fault */
+    0x0581,	/* Fen_Fault */
+    0x2001,	/* Pal_Fault */
+    0x0501,	/* Integer_Overflow_Fault: maps to Arithmetic_Fault */
 };
 
 const int AlphaISA::reg_redir[AlphaISA::NumIntRegs] = {
@@ -106,13 +119,14 @@ const int AlphaISA::reg_redir[AlphaISA::NumIntRegs] = {
 //
 //
 void
-AlphaISA::initIPRs(RegFile *regs)
+AlphaISA::initIPRs(RegFile *regs, int cpuId)
 {
     uint64_t *ipr = regs->ipr;
 
     bzero((char *)ipr, NumInternalProcRegs * sizeof(InternalProcReg));
     ipr[IPR_PAL_BASE] = PalBase;
     ipr[IPR_MCSR] = 0x6;
+    ipr[IPR_PALtemp16] = cpuId;
 }
 
 
@@ -158,7 +172,7 @@ AlphaISA::processInterrupts(CPU *cpu)
     if (ipl && ipl > ipr[IPR_IPLR]) {
         ipr[IPR_ISR] = summary;
         ipr[IPR_INTID] = ipl;
-        cpu->trap(InterruptFault);
+        cpu->trap(Interrupt_Fault);
         DPRINTF(Flow, "Interrupt! IPLR=%d ipl=%d summary=%x\n",
                 ipr[IPR_IPLR], ipl, summary);
     }
@@ -179,23 +193,23 @@ AlphaISA::zeroRegisters(CPU *cpu)
 void
 ExecContext::ev5_trap(Fault fault)
 {
-    DPRINTF(Fault, "Fault %s at PC: %#x\n", fault->name, regs.pc);
+    DPRINTF(Fault, "Fault %s at PC: %#x\n", FaultName(fault), regs.pc);
-    cpu->recordEvent(csprintf("Fault %s", fault->name));
+    cpu->recordEvent(csprintf("Fault %s", FaultName(fault)));
 
     assert(!misspeculating());
     kernelStats->fault(fault);
 
-    if (fault == ArithmeticFault)
+    if (fault == Arithmetic_Fault)
         panic("Arithmetic traps are unimplemented!");
 
     AlphaISA::InternalProcReg *ipr = regs.ipr;
 
     // exception restart address
-    if (fault != InterruptFault || !inPalMode())
+    if (fault != Interrupt_Fault || !inPalMode())
         ipr[AlphaISA::IPR_EXC_ADDR] = regs.pc;
 
-    if (fault == PalFault || fault == ArithmeticFault /* ||
+    if (fault == Pal_Fault || fault == Arithmetic_Fault /* ||
-        fault == InterruptFault && !inPalMode() */) {
+        fault == Interrupt_Fault && !inPalMode() */) {
         // traps...  skip faulting instruction
         ipr[AlphaISA::IPR_EXC_ADDR] += 4;
     }
@@ -203,7 +217,7 @@ ExecContext::ev5_trap(Fault fault)
     if (!inPalMode())
         AlphaISA::swap_palshadow(&regs, true);
 
-    regs.pc = ipr[AlphaISA::IPR_PAL_BASE] + AlphaISA::fault_addr(fault);
+    regs.pc = ipr[AlphaISA::IPR_PAL_BASE] + AlphaISA::fault_addr[fault];
     regs.npc = regs.pc + sizeof(MachInst);
 }
 
@@ -212,13 +226,13 @@ void
 AlphaISA::intr_post(RegFile *regs, Fault fault, Addr pc)
 {
     InternalProcReg *ipr = regs->ipr;
-    bool use_pc = (fault == NoFault);
+    bool use_pc = (fault == No_Fault);
 
-    if (fault == ArithmeticFault)
+    if (fault == Arithmetic_Fault)
         panic("arithmetic faults NYI...");
 
     // compute exception restart address
-    if (use_pc || fault == PalFault || fault == ArithmeticFault) {
+    if (use_pc || fault == Pal_Fault || fault == Arithmetic_Fault) {
         // traps...  skip faulting instruction
         ipr[IPR_EXC_ADDR] = regs->pc + 4;
     } else {
@@ -228,7 +242,7 @@ AlphaISA::intr_post(RegFile *regs, Fault fault, Addr pc)
 
     // jump to expection address (PAL PC bit set here as well...)
     if (!use_pc)
-        regs->npc = ipr[IPR_PAL_BASE] + fault_addr(fault);
+        regs->npc = ipr[IPR_PAL_BASE] + fault_addr[fault];
     else
         regs->npc = ipr[IPR_PAL_BASE] + pc;
 
@@ -241,7 +255,7 @@ ExecContext::hwrei()
     uint64_t *ipr = regs.ipr;
 
     if (!inPalMode())
-        return UnimplementedOpcodeFault;
+        return Unimplemented_Opcode_Fault;
 
     setNextPC(ipr[AlphaISA::IPR_EXC_ADDR]);
 
@@ -255,7 +269,7 @@ ExecContext::hwrei()
     }
 
     // FIXME: XXX check for interrupts? XXX
-    return NoFault;
+    return No_Fault;
 }
 
 uint64_t
@@ -353,12 +367,12 @@ ExecContext::readIpr(int idx, Fault &fault)
       case AlphaISA::IPR_DTB_IAP:
       case AlphaISA::IPR_ITB_IA:
       case AlphaISA::IPR_ITB_IAP:
-        fault = UnimplementedOpcodeFault;
+        fault = Unimplemented_Opcode_Fault;
         break;
 
       default:
         // invalid IPR
-        fault = UnimplementedOpcodeFault;
+        fault = Unimplemented_Opcode_Fault;
         break;
     }
 
@@ -377,7 +391,7 @@ ExecContext::setIpr(int idx, uint64_t val)
     uint64_t old;
 
     if (misspeculating())
-        return NoFault;
+        return No_Fault;
 
     switch (idx) {
       case AlphaISA::IPR_PALtemp0:
@@ -523,7 +537,7 @@ ExecContext::setIpr(int idx, uint64_t val)
       case AlphaISA::IPR_ITB_PTE_TEMP:
       case AlphaISA::IPR_DTB_PTE_TEMP:
         // read-only registers
-        return UnimplementedOpcodeFault;
+        return Unimplemented_Opcode_Fault;
 
       case AlphaISA::IPR_HWINT_CLR:
       case AlphaISA::IPR_SL_XMIT:
@@ -625,11 +639,11 @@ ExecContext::setIpr(int idx, uint64_t val)
 
       default:
         // invalid IPR
-        return UnimplementedOpcodeFault;
+        return Unimplemented_Opcode_Fault;
     }
 
     // no error...
-    return NoFault;
+    return No_Fault;
 }
 
 /**

cpu/o3/cpu.cc

@@ -137,8 +137,6 @@ FullO3CPU<Impl>::FullO3CPU(Params &params)
         system->execContexts[i] =
             new ExecContext(this, i, system, itb, dtb, mem);
 
-        // initialize CPU, including PC
-        TheISA::initCPU(&system->execContexts[i]->regs);
         execContexts.push_back(system->execContexts[i]);
 #else
         if (i < params.workload.size()) {
@@ -250,6 +248,7 @@ FullO3CPU<Impl>::init()
         // that it can start properly.
 #if FULL_SYSTEM
         ExecContext *src_xc = system->execContexts[0];
+        TheISA::initCPU(&src_xc->regs, src_xc->cpu_id);
 #else
         ExecContext *src_xc = thread[0];
 #endif

cpu/simple/cpu.cc

@@ -84,6 +84,21 @@ SimpleCPU::TickEvent::TickEvent(SimpleCPU *c, int w)
 {
 }
 
+
+void
+SimpleCPU::init()
+{
+    BaseCPU::init();
+#if FULL_SYSTEM
+    for (int i = 0; i < execContexts.size(); ++i) {
+        ExecContext *xc = execContexts[i];
+
+        // initialize CPU, including PC
+        TheISA::initCPU(&xc->regs, xc->cpu_id);
+    }
+#endif
+}
+
 void
 SimpleCPU::TickEvent::process()
 {
@@ -124,8 +139,6 @@ SimpleCPU::SimpleCPU(Params *p)
 #if FULL_SYSTEM
     xc = new ExecContext(this, 0, p->system, p->itb, p->dtb, p->mem);
 
-    // initialize CPU, including PC
-    initCPU(&xc->regs);
 #else
     xc = new ExecContext(this, /* thread_num */ 0, p->process, /* asid */ 0);
 #endif // !FULL_SYSTEM

cpu/simple/cpu.hh

@@ -68,6 +68,7 @@ class SimpleCPU : public BaseCPU
   public:
     // main simulation loop (one cycle)
     void tick();
+    virtual void init();
 
   private:
     struct TickEvent : public Event

dev/alpha_access.h

@@ -33,7 +33,7 @@
  * System Console Memory Mapped Register Definition
  */
 
-#define ALPHA_ACCESS_VERSION (1303)
+#define ALPHA_ACCESS_VERSION (1305)
 
 #ifdef CONSOLE
 typedef unsigned uint32_t;
@@ -67,9 +67,7 @@ struct AlphaAccess
     uint64_t	inputChar;		// 68: Placeholder for input
 
     // MP boot
-    uint64_t	bootStrapImpure;	// 70:
+    uint64_t	cpuStack[64];	        // 70:
-    uint32_t	bootStrapCPU;		// 78:
-    uint32_t	align2;			// 7C: Dummy placeholder for alignment
 };
 
 #endif // __ALPHA_ACCESS_H__

dev/alpha_console.cc

@@ -81,9 +81,7 @@ AlphaConsole::AlphaConsole(const string &name, SimConsole *cons, SimpleDisk *d,
     alphaAccess->diskOperation = 0;
     alphaAccess->outputChar = 0;
     alphaAccess->inputChar = 0;
-    alphaAccess->bootStrapImpure = 0;
+    bzero(alphaAccess->cpuStack, sizeof(alphaAccess->cpuStack));
-    alphaAccess->bootStrapCPU = 0;
-    alphaAccess->align2 = 0;
 
     system->setAlphaAccess(addr);
 }
@@ -123,9 +121,6 @@ AlphaConsole::read(MemReqPtr &req, uint8_t *data)
                 case offsetof(AlphaAccess, numCPUs):
                     *(uint32_t*)data = alphaAccess->numCPUs;
                     break;
-                case offsetof(AlphaAccess, bootStrapCPU):
-                    *(uint32_t*)data = alphaAccess->bootStrapCPU;
-                    break;
                 case offsetof(AlphaAccess, intrClockFrequency):
                     *(uint32_t*)data = alphaAccess->intrClockFrequency;
                     break;
@@ -176,11 +171,14 @@ AlphaConsole::read(MemReqPtr &req, uint8_t *data)
                 case offsetof(AlphaAccess, outputChar):
                     *(uint64_t*)data = alphaAccess->outputChar;
                     break;
-                case offsetof(AlphaAccess, bootStrapImpure):
-                    *(uint64_t*)data = alphaAccess->bootStrapImpure;
-                    break;
                 default:
-                    panic("Unknown 64bit access, %#x\n", daddr);
+                    int cpunum = (daddr - offsetof(AlphaAccess, cpuStack)) /
+                                 sizeof(alphaAccess->cpuStack[0]);
+
+                    if (cpunum >= 0 && cpunum < 64)
+                        *(uint64_t*)data = alphaAccess->cpuStack[cpunum];
+                    else
+                        panic("Unknown 64bit access, %#x\n", daddr);
             }
             break;
         default:
@@ -240,24 +238,18 @@ AlphaConsole::write(MemReqPtr &req, const uint8_t *data)
         console->out((char)(val & 0xff));
         break;
 
-      case offsetof(AlphaAccess, bootStrapImpure):
-        alphaAccess->bootStrapImpure = val;
-        break;
-
-      case offsetof(AlphaAccess, bootStrapCPU):
-        warn("%d: Trying to launch another CPU!", curTick);
-        assert(val > 0 && "Must not access primary cpu");
-
-        other_xc = req->xc->system->execContexts[val];
-        other_xc->regs.intRegFile[16] = val;
-        other_xc->regs.ipr[TheISA::IPR_PALtemp16] = val;
-        other_xc->regs.intRegFile[0] = val;
-        other_xc->regs.intRegFile[30] = alphaAccess->bootStrapImpure;
         other_xc->activate(); //Start the cpu
         break;
 
       default:
-        return MachineCheckFault;
+        int cpunum = (daddr - offsetof(AlphaAccess, cpuStack)) /
+                     sizeof(alphaAccess->cpuStack[0]);
+        warn("%d: Trying to launch CPU number %d!", curTick, cpunum);
+        assert(val > 0 && "Must not access primary cpu");
+        if (cpunum >= 0 && cpunum < 64)
+            alphaAccess->cpuStack[cpunum] = val;
+        else
+            panic("Unknown 64bit access, %#x\n", daddr);
     }
 
     return NoFault;
@@ -288,8 +280,7 @@ AlphaConsole::Access::serialize(ostream &os)
     SERIALIZE_SCALAR(diskOperation);
     SERIALIZE_SCALAR(outputChar);
     SERIALIZE_SCALAR(inputChar);
-    SERIALIZE_SCALAR(bootStrapImpure);
+    SERIALIZE_ARRAY(cpuStack,64);
-    SERIALIZE_SCALAR(bootStrapCPU);
 }
 
 void
@@ -311,8 +302,7 @@ AlphaConsole::Access::unserialize(Checkpoint *cp, const std::string &section)
     UNSERIALIZE_SCALAR(diskOperation);
     UNSERIALIZE_SCALAR(outputChar);
     UNSERIALIZE_SCALAR(inputChar);
-    UNSERIALIZE_SCALAR(bootStrapImpure);
+    UNSERIALIZE_ARRAY(cpuStack, 64);
-    UNSERIALIZE_SCALAR(bootStrapCPU);
 }
 
 void

dev/alpha_console.hh

@@ -96,7 +96,7 @@ class AlphaConsole : public PioDevice
     BaseCPU *cpu;
 
     Addr addr;
-    static const Addr size = 0x80; // equal to sizeof(alpha_access);
+    static const Addr size = sizeof(struct AlphaAccess);
 
   public:
     /** Standard Constructor */

sim/system.cc

@@ -307,11 +307,9 @@ System::registerExecContext(ExecContext *xc, int id)
 void
 System::startup()
 {
-    if (!execContexts.empty()) {
+    int i;
-        // activate with zero delay so that we start ticking right
+    for (i = 0; i < execContexts.size(); i++)
-        // away on cycle 0
+        execContexts[i]->activate(0);
-        execContexts[0]->activate(0);
-    }
 }
 
 void