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arch: Cleanup unused ISA traits constants

Browse source 
This patch prunes unused values, and also unifies how the values are
defined (not using an enum for ALPHA), aligning the use of int vs Addr
etc.

The patch also removes the duplication of PageBytes/PageShift and
VMPageSize/LogVMPageSize. For all ISAs the two pairs had identical
values and the latter has been removed.
This commit is contained in:
Andreas Hansson 2014-09-03 07:42:21 -04:00
parent 23c8540756
commit e1ac962939
24 changed files with 75 additions and 129 deletions
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14
src/arch/alpha/isa_traits.hh
View file

@ -109,19 +109,7 @@ enum mode_type
mode_number // number of modes
};
// Constants Related to the number of registers
enum {
LogVMPageSize = 13, // 8K bytes
VMPageSize = (1 << LogVMPageSize),
BranchPredAddrShiftAmt = 2, // instructions are 4-byte aligned
MachineBytes = 8,
WordBytes = 4,
HalfwordBytes = 2,
ByteBytes = 1
};
const int MachineBytes = 8;
// return a no-op instruction... used for instruction fetch faults
// Alpha UNOP (ldq_u r31,0(r0))

6
src/arch/alpha/process.cc
View file

@ -49,7 +49,7 @@ AlphaLiveProcess::AlphaLiveProcess(LiveProcessParams *params,
: LiveProcess(params, objFile)
{
brk_point = objFile->dataBase() + objFile->dataSize() + objFile->bssSize();
brk_point = roundUp(brk_point, VMPageSize);
brk_point = roundUp(brk_point, PageBytes);
// Set up stack. On Alpha, stack goes below text section. This
// code should get moved to some architecture-specific spot.
@ -83,7 +83,7 @@ AlphaLiveProcess::argsInit(int intSize, int pageSize)
// seem to be a problem.
// check out _dl_aux_init() in glibc/elf/dl-support.c for details
// --Lisa
auxv.push_back(auxv_t(M5_AT_PAGESZ, AlphaISA::VMPageSize));
auxv.push_back(auxv_t(M5_AT_PAGESZ, AlphaISA::PageBytes));
auxv.push_back(auxv_t(M5_AT_CLKTCK, 100));
auxv.push_back(auxv_t(M5_AT_PHDR, elfObject->programHeaderTable()));
DPRINTF(Loader, "auxv at PHDR %08p\n", elfObject->programHeaderTable());
@ -193,7 +193,7 @@ AlphaLiveProcess::initState()
LiveProcess::initState();
argsInit(MachineBytes, VMPageSize);
argsInit(MachineBytes, PageBytes);
ThreadContext *tc = system->getThreadContext(contextIds[0]);
tc->setIntReg(GlobalPointerReg, objFile->globalPointer());

11
src/arch/arm/isa_traits.hh
View file

@ -51,8 +51,6 @@
namespace LittleEndianGuest {}
#define TARGET_ARM
namespace ArmISA
{
using namespace LittleEndianGuest;
@ -101,16 +99,7 @@ namespace ArmISA
// return a no-op instruction... used for instruction fetch faults
const ExtMachInst NoopMachInst = 0x01E320F000ULL;
const int LogVMPageSize = 12; // 4K bytes
const int VMPageSize = (1 << LogVMPageSize);
// Shouldn't this be 1 because of Thumb?! Dynamic? --Ali
const int BranchPredAddrShiftAmt = 2; // instructions are 4-byte aligned
const int MachineBytes = 4;
const int WordBytes = 4;
const int HalfwordBytes = 2;
const int ByteBytes = 1;
const uint32_t HighVecs = 0xFFFF0000;

10
src/arch/arm/process.cc
View file

@ -74,7 +74,7 @@ ArmLiveProcess32::ArmLiveProcess32(LiveProcessParams *params,
// Set up break point (Top of Heap)
brk_point = objFile->dataBase() + objFile->dataSize() + objFile->bssSize();
brk_point = roundUp(brk_point, VMPageSize);
brk_point = roundUp(brk_point, PageBytes);
// Set up region for mmaps. For now, start at bottom of kuseg space.
mmap_start = mmap_end = 0x40000000L;
@ -91,7 +91,7 @@ ArmLiveProcess64::ArmLiveProcess64(LiveProcessParams *params,
// Set up break point (Top of Heap)
brk_point = objFile->dataBase() + objFile->dataSize() + objFile->bssSize();
brk_point = roundUp(brk_point, VMPageSize);
brk_point = roundUp(brk_point, PageBytes);
// Set up region for mmaps. For now, start at bottom of kuseg space.
mmap_start = mmap_end = 0x4000000000L;
@ -101,7 +101,7 @@ void
ArmLiveProcess32::initState()
{
LiveProcess::initState();
argsInit<uint32_t>(VMPageSize, INTREG_SP);
argsInit<uint32_t>(PageBytes, INTREG_SP);
for (int i = 0; i < contextIds.size(); i++) {
ThreadContext * tc = system->getThreadContext(contextIds[i]);
CPACR cpacr = tc->readMiscReg(MISCREG_CPACR);
@ -120,7 +120,7 @@ void
ArmLiveProcess64::initState()
{
LiveProcess::initState();
argsInit<uint64_t>(VMPageSize, INTREG_SP0);
argsInit<uint64_t>(PageBytes, INTREG_SP0);
for (int i = 0; i < contextIds.size(); i++) {
ThreadContext * tc = system->getThreadContext(contextIds[i]);
CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
@ -203,7 +203,7 @@ ArmLiveProcess::argsInit(int pageSize, IntRegIndex spIndex)
//XXX Figure out what these should be
auxv.push_back(auxv_t(M5_AT_HWCAP, features));
//The system page size
auxv.push_back(auxv_t(M5_AT_PAGESZ, ArmISA::VMPageSize));
auxv.push_back(auxv_t(M5_AT_PAGESZ, ArmISA::PageBytes));
//Frequency at which times() increments
auxv.push_back(auxv_t(M5_AT_CLKTCK, 0x64));
// For statically linked executables, this is the virtual address of the

1
src/arch/arm/utility.cc
View file

@ -85,6 +85,7 @@ getArgument(ThreadContext *tc, int &number, uint16_t size, bool fp)
}
} else {
if (size == (uint16_t)(-1))
// todo: should this not be sizeof(uint32_t) rather?
size = ArmISA::MachineBytes;
if (number < NumArgumentRegs) {

10
src/arch/mips/isa_traits.hh
View file

@ -145,16 +145,6 @@ enum mode_type
// return a no-op instruction... used for instruction fetch faults
const ExtMachInst NoopMachInst = 0x00000000;
const int LogVMPageSize = 13; // 8K bytes
const int VMPageSize = (1 << LogVMPageSize);
const int BranchPredAddrShiftAmt = 2; // instructions are 4-byte aligned
const int MachineBytes = 4;
const int WordBytes = 4;
const int HalfwordBytes = 2;
const int ByteBytes = 1;
const int ANNOTE_NONE = 0;
const uint32_t ITOUCH_ANNOTE = 0xffffffff;

6
src/arch/mips/process.cc
View file

@ -58,7 +58,7 @@ MipsLiveProcess::MipsLiveProcess(LiveProcessParams * params,
// Set up break point (Top of Heap)
brk_point = objFile->dataBase() + objFile->dataSize() + objFile->bssSize();
brk_point = roundUp(brk_point, VMPageSize);
brk_point = roundUp(brk_point, PageBytes);
// Set up region for mmaps. Start it 1GB above the top of the heap.
mmap_start = mmap_end = brk_point + 0x40000000L;
@ -69,7 +69,7 @@ MipsLiveProcess::initState()
{
LiveProcess::initState();
argsInit<uint32_t>(VMPageSize);
argsInit<uint32_t>(PageBytes);
}
template<class IntType>
@ -88,7 +88,7 @@ MipsLiveProcess::argsInit(int pageSize)
if (elfObject)
{
// Set the system page size
auxv.push_back(auxv_t(M5_AT_PAGESZ, MipsISA::VMPageSize));
auxv.push_back(auxv_t(M5_AT_PAGESZ, MipsISA::PageBytes));
// Set the frequency at which time() increments
auxv.push_back(auxv_t(M5_AT_CLKTCK, 100));
// For statically linked executables, this is the virtual

3
src/arch/null/isa_traits.hh
View file

@ -51,9 +51,6 @@ namespace NullISA
const Addr PageShift = 12;
const Addr PageBytes = ULL(1) << PageShift;
const int LogVMPageSize = 12; // 4K bytes
const int VMPageSize = (1 << LogVMPageSize);
}
#endif //__ARCH_NULL_ISA_TRAITS_HH__

3
src/arch/power/isa_traits.hh
View file

@ -61,9 +61,6 @@ const Addr NPtePageShift = PageShift - PteShift;
const Addr NPtePage = ULL(1) << NPtePageShift;
const Addr PteMask = NPtePage - 1;
const int LogVMPageSize = 12; // 4K bytes
const int VMPageSize = (1 << LogVMPageSize);
const int MachineBytes = 4;
// This is ori 0, 0, 0

6
src/arch/power/process.cc
View file

@ -56,7 +56,7 @@ PowerLiveProcess::PowerLiveProcess(LiveProcessParams *params,
// Set up break point (Top of Heap)
brk_point = objFile->dataBase() + objFile->dataSize() + objFile->bssSize();
brk_point = roundUp(brk_point, VMPageSize);
brk_point = roundUp(brk_point, PageBytes);
// Set up region for mmaps. For now, start at bottom of kuseg space.
mmap_start = mmap_end = 0x70000000L;
@ -67,7 +67,7 @@ PowerLiveProcess::initState()
{
Process::initState();
argsInit(MachineBytes, VMPageSize);
argsInit(MachineBytes, PageBytes);
}
void
@ -98,7 +98,7 @@ PowerLiveProcess::argsInit(int intSize, int pageSize)
//XXX Figure out what these should be
auxv.push_back(auxv_t(M5_AT_HWCAP, features));
//The system page size
auxv.push_back(auxv_t(M5_AT_PAGESZ, PowerISA::VMPageSize));
auxv.push_back(auxv_t(M5_AT_PAGESZ, PowerISA::PageBytes));
//Frequency at which times() increments
auxv.push_back(auxv_t(M5_AT_CLKTCK, 0x64));
// For statically linked executables, this is the virtual address of the

14
src/arch/sparc/isa_traits.hh
View file

@ -41,8 +41,6 @@ namespace BigEndianGuest {}
namespace SparcISA
{
const int MachineBytes = 8;
// This makes sure the big endian versions of certain functions are used.
using namespace BigEndianGuest;
@ -52,21 +50,13 @@ using namespace BigEndianGuest;
// SPARC NOP (sethi %(hi(0), g0)
const MachInst NoopMachInst = 0x01000000;
// 8K. This value is implmentation specific; and should probably
// be somewhere else.
const int LogVMPageSize = 13;
const int VMPageSize = (1 << LogVMPageSize);
// real address virtual mapping
// sort of like alpha super page, but less frequently used
const Addr SegKPMEnd = ULL(0xfffffffc00000000);
const Addr SegKPMBase = ULL(0xfffffac000000000);
// Why does both the previous set of constants and this one exist?
const int PageShift = 13;
const int PageBytes = 1ULL << PageShift;
const int BranchPredAddrShiftAmt = 2;
const Addr PageShift = 13;
const Addr PageBytes = ULL(1) << PageShift;
StaticInstPtr decodeInst(ExtMachInst);

8
src/arch/sparc/process.cc
View file

@ -57,7 +57,7 @@ SparcLiveProcess::SparcLiveProcess(LiveProcessParams * params,
// XXX all the below need to be updated for SPARC - Ali
brk_point = objFile->dataBase() + objFile->dataSize() + objFile->bssSize();
brk_point = roundUp(brk_point, VMPageSize);
brk_point = roundUp(brk_point, PageBytes);
// Set pointer for next thread stack. Reserve 8M for main stack.
next_thread_stack_base = stack_base - (8 * 1024 * 1024);
@ -166,7 +166,7 @@ Sparc32LiveProcess::initState()
pstate.am = 1;
tc->setMiscReg(MISCREG_PSTATE, pstate);
argsInit(32 / 8, VMPageSize);
argsInit(32 / 8, PageBytes);
}
void
@ -180,7 +180,7 @@ Sparc64LiveProcess::initState()
pstate.ie = 1;
tc->setMiscReg(MISCREG_PSTATE, pstate);
argsInit(sizeof(IntReg), VMPageSize);
argsInit(sizeof(IntReg), PageBytes);
}
template<class IntType>
@ -234,7 +234,7 @@ SparcLiveProcess::argsInit(int pageSize)
// Bits which describe the system hardware capabilities
auxv.push_back(auxv_t(M5_AT_HWCAP, hwcap));
// The system page size
auxv.push_back(auxv_t(M5_AT_PAGESZ, SparcISA::VMPageSize));
auxv.push_back(auxv_t(M5_AT_PAGESZ, SparcISA::PageBytes));
// Defined to be 100 in the kernel source.
// Frequency at which times() increments
auxv.push_back(auxv_t(M5_AT_CLKTCK, 100));

10
src/arch/x86/isa_traits.hh
View file

@ -59,14 +59,8 @@ namespace X86ISA
//XXX This needs to be set to an intermediate instruction struct
//which encodes this instruction
//4k. This value is not constant on x86.
const int LogVMPageSize = 12;
const int VMPageSize = (1 << LogVMPageSize);
const int PageShift = 12;
const int PageBytes = 1ULL << PageShift;
const int BranchPredAddrShiftAmt = 0;
const Addr PageShift = 12;
const Addr PageBytes = ULL(1) << PageShift;
// Memory accesses can be unaligned
const bool HasUnalignedMemAcc = true;

14
src/arch/x86/process.cc
View file

@ -86,7 +86,7 @@ X86LiveProcess::X86LiveProcess(LiveProcessParams * params, ObjectFile *objFile,
numSyscallDescs(_numSyscallDescs)
{
brk_point = objFile->dataBase() + objFile->dataSize() + objFile->bssSize();
brk_point = roundUp(brk_point, VMPageSize);
brk_point = roundUp(brk_point, PageBytes);
}
X86_64LiveProcess::X86_64LiveProcess(LiveProcessParams *params,
@ -96,7 +96,7 @@ X86_64LiveProcess::X86_64LiveProcess(LiveProcessParams *params,
{
vsyscallPage.base = 0xffffffffff600000ULL;
vsyscallPage.size = VMPageSize;
vsyscallPage.size = PageBytes;
vsyscallPage.vtimeOffset = 0x400;
vsyscallPage.vgettimeofdayOffset = 0x0;
@ -133,10 +133,10 @@ I386LiveProcess::I386LiveProcess(LiveProcessParams *params,
X86LiveProcess(params, objFile, _syscallDescs, _numSyscallDescs)
{
_gdtStart = ULL(0xffffd000);
_gdtSize = VMPageSize;
_gdtSize = PageBytes;
vsyscallPage.base = 0xffffe000ULL;
vsyscallPage.size = VMPageSize;
vsyscallPage.size = PageBytes;
vsyscallPage.vsyscallOffset = 0x400;
vsyscallPage.vsysexitOffset = 0x410;
@ -163,7 +163,7 @@ X86_64LiveProcess::initState()
{
X86LiveProcess::initState();
argsInit(sizeof(uint64_t), VMPageSize);
argsInit(sizeof(uint64_t), PageBytes);
// Set up the vsyscall page for this process.
allocateMem(vsyscallPage.base, vsyscallPage.size);
@ -258,7 +258,7 @@ I386LiveProcess::initState()
{
X86LiveProcess::initState();
argsInit(sizeof(uint32_t), VMPageSize);
argsInit(sizeof(uint32_t), PageBytes);
/*
* Set up a GDT for this process. The whole GDT wouldn't really be for
@ -474,7 +474,7 @@ X86LiveProcess::argsInit(int pageSize,
//XXX Figure out what these should be
auxv.push_back(auxv_t(M5_AT_HWCAP, features));
//The system page size
auxv.push_back(auxv_t(M5_AT_PAGESZ, X86ISA::VMPageSize));
auxv.push_back(auxv_t(M5_AT_PAGESZ, X86ISA::PageBytes));
//Frequency at which times() increments
//Defined to be 100 in the kernel source.
auxv.push_back(auxv_t(M5_AT_CLKTCK, 100));

8
src/kern/tru64/tru64.hh
View file

@ -548,8 +548,8 @@ class Tru64 : public OperatingSystem
process->next_thread_stack_base -= stack_size;
}
Addr rounded_stack_base = roundDown(stack_base, VMPageSize);
Addr rounded_stack_size = roundUp(stack_size, VMPageSize);
Addr rounded_stack_base = roundDown(stack_base, PageBytes);
Addr rounded_stack_size = roundUp(stack_size, PageBytes);
DPRINTF(SyscallVerbose,
"stack_create: allocating stack @ %#x size %#x "
@ -675,9 +675,9 @@ class Tru64 : public OperatingSystem
*configptr_ptr = htog(config_addr);
// Register this as a valid address range with the process
base_addr = roundDown(base_addr, VMPageSize);
base_addr = roundDown(base_addr, PageBytes);
int size = cur_addr - base_addr;
process->allocateMem(base_addr, roundUp(size, VMPageSize));
process->allocateMem(base_addr, roundUp(size, PageBytes));
config.copyOut(tc->getMemProxy());
slot_state.copyOut(tc->getMemProxy());

2
src/mem/cache/prefetch/base.cc vendored
View file

@ -312,7 +312,7 @@ BasePrefetcher::inPrefetch(Addr address, bool is_secure)
bool
BasePrefetcher::samePage(Addr a, Addr b)
{
return roundDown(a, TheISA::VMPageSize) == roundDown(b, TheISA::VMPageSize);
return roundDown(a, TheISA::PageBytes) == roundDown(b, TheISA::PageBytes);
}

24
src/mem/multi_level_page_table_impl.hh
View file

@ -74,13 +74,13 @@ MultiLevelPageTable<ISAOps>::initState(ThreadContext* tc)
/* setting first level of the page table */
uint64_t log_req_size = floorLog2(sizeof(PageTableEntry)) +
logLevelSize[numLevels-1];
assert(log_req_size >= LogVMPageSize);
uint64_t npages = 1 << (log_req_size - LogVMPageSize);
assert(log_req_size >= PageShift);
uint64_t npages = 1 << (log_req_size - PageShift);
Addr paddr = system->allocPhysPages(npages);
PortProxy &p = system->physProxy;
p.memsetBlob(paddr, 0, npages << LogVMPageSize);
p.memsetBlob(paddr, 0, npages << PageShift);
}
@ -93,7 +93,7 @@ MultiLevelPageTable<ISAOps>::walk(Addr vaddr, bool allocate, Addr &PTE_addr)
Addr level_base = basePtr;
for (int i = numLevels - 1; i > 0; i--) {
Addr entry_addr = (level_base<<LogVMPageSize) +
Addr entry_addr = (level_base<<PageShift) +
offsets[i] * sizeof(PageTableEntry);
PortProxy &p = system->physProxy;
@ -106,16 +106,16 @@ MultiLevelPageTable<ISAOps>::walk(Addr vaddr, bool allocate, Addr &PTE_addr)
uint64_t log_req_size = floorLog2(sizeof(PageTableEntry)) +
logLevelSize[i-1];
assert(log_req_size >= LogVMPageSize);
uint64_t npages = 1 << (log_req_size - LogVMPageSize);
assert(log_req_size >= PageShift);
uint64_t npages = 1 << (log_req_size - PageShift);
DPRINTF(MMU, "Allocating %d pages needed for entry in level %d\n", npages, i-1);
/* allocate new entry */
Addr next_entry_paddr = system->allocPhysPages(npages);
p.memsetBlob(next_entry_paddr, 0, npages << LogVMPageSize);
p.memsetBlob(next_entry_paddr, 0, npages << PageShift);
next_entry_pnum = next_entry_paddr >> LogVMPageSize;
next_entry_pnum = next_entry_paddr >> PageShift;
pTableISAOps.setPnum(entry, next_entry_pnum);
pTableISAOps.setPTEFields(entry);
p.write<PageTableEntry>(entry_addr, entry);
@ -125,7 +125,7 @@ MultiLevelPageTable<ISAOps>::walk(Addr vaddr, bool allocate, Addr &PTE_addr)
level_base = next_entry_pnum;
}
PTE_addr = (level_base<<LogVMPageSize) +
PTE_addr = (level_base<<PageShift) +
offsets[0] * sizeof(PageTableEntry);
DPRINTF(MMU, "Returning PTE_addr: %x\n", PTE_addr);
return true;
@ -148,7 +148,7 @@ MultiLevelPageTable<ISAOps>::map(Addr vaddr, Addr paddr, int64_t size, bool clob
PageTableEntry PTE = p.read<PageTableEntry>(PTE_addr);
Addr entry_paddr = pTableISAOps.getPnum(PTE);
if (!clobber && entry_paddr == 0) {
pTableISAOps.setPnum(PTE, paddr >> LogVMPageSize);
pTableISAOps.setPnum(PTE, paddr >> PageShift);
pTableISAOps.setPTEFields(PTE);
p.write<PageTableEntry>(PTE_addr, PTE);
DPRINTF(MMU, "New mapping: %#x-%#x\n", vaddr, paddr);
@ -193,7 +193,7 @@ MultiLevelPageTable<ISAOps>::remap(Addr vaddr, int64_t size, Addr new_vaddr)
walk(new_vaddr, true, new_PTE_addr);
PageTableEntry new_PTE = p.read<PageTableEntry>(new_PTE_addr);
pTableISAOps.setPnum(new_PTE, paddr>>LogVMPageSize);
pTableISAOps.setPnum(new_PTE, paddr>>PageShift);
pTableISAOps.setPTEFields(new_PTE);
p.write<PageTableEntry>(new_PTE_addr, new_PTE);
DPRINTF(MMU, "Remapping: %#x-%#x\n", vaddr, new_PTE_addr);
@ -285,7 +285,7 @@ MultiLevelPageTable<ISAOps>::lookup(Addr vaddr, TlbEntry &entry)
if (pnum == 0)
return false;
entry = TlbEntry(pid, vaddr, pnum << LogVMPageSize);
entry = TlbEntry(pid, vaddr, pnum << PageShift);
updateCache(page_addr, entry);
} else {
return false;

6
src/mem/page_table.hh
View file

@ -73,7 +73,7 @@ class PageTableBase
public:
PageTableBase(const std::string &__name, uint64_t _pid,
Addr _pageSize = TheISA::VMPageSize)
Addr _pageSize = TheISA::PageBytes)
: pageSize(_pageSize), offsetMask(mask(floorLog2(_pageSize))),
pid(_pid), _name(__name)
{
@ -188,7 +188,7 @@ class FuncPageTable : public PageTableBase
public:
FuncPageTable(const std::string &__name, uint64_t _pid,
Addr _pageSize = TheISA::VMPageSize);
Addr _pageSize = TheISA::PageBytes);
~FuncPageTable();
@ -229,7 +229,7 @@ class NoArchPageTable : public FuncPageTable
{
public:
NoArchPageTable(const std::string &__name, uint64_t _pid, System *_sys,
Addr _pageSize = TheISA::VMPageSize) : FuncPageTable(__name, _pid)
Addr _pageSize = TheISA::PageBytes) : FuncPageTable(__name, _pid)
{
fatal("No architectural page table defined for this ISA.\n");
}

2
src/mem/ruby/common/Address.cc
View file

@ -139,7 +139,7 @@ Address::operator=(const Address& obj)
void
Address::makePageAddress()
{
m_address = maskLowOrderBits(TheISA::LogVMPageSize);
m_address = maskLowOrderBits(TheISA::PageShift);
}
Address

14
src/mem/se_translating_port_proxy.cc
View file

@ -68,7 +68,7 @@ SETranslatingPortProxy::tryReadBlob(Addr addr, uint8_t *p, int size) const
{
int prevSize = 0;
for (ChunkGenerator gen(addr, size, VMPageSize); !gen.done(); gen.next()) {
for (ChunkGenerator gen(addr, size, PageBytes); !gen.done(); gen.next()) {
Addr paddr;
if (!pTable->translate(gen.addr(),paddr))
@ -94,13 +94,13 @@ SETranslatingPortProxy::tryWriteBlob(Addr addr, uint8_t *p, int size) const
{
int prevSize = 0;
for (ChunkGenerator gen(addr, size, VMPageSize); !gen.done(); gen.next()) {
for (ChunkGenerator gen(addr, size, PageBytes); !gen.done(); gen.next()) {
Addr paddr;
if (!pTable->translate(gen.addr(), paddr)) {
if (allocating == Always) {
process->allocateMem(roundDown(gen.addr(), VMPageSize),
VMPageSize);
process->allocateMem(roundDown(gen.addr(), PageBytes),
PageBytes);
} else if (allocating == NextPage) {
// check if we've accessed the next page on the stack
if (!process->fixupStackFault(gen.addr()))
@ -130,13 +130,13 @@ SETranslatingPortProxy::writeBlob(Addr addr, uint8_t *p, int size) const
bool
SETranslatingPortProxy::tryMemsetBlob(Addr addr, uint8_t val, int size) const
{
for (ChunkGenerator gen(addr, size, VMPageSize); !gen.done(); gen.next()) {
for (ChunkGenerator gen(addr, size, PageBytes); !gen.done(); gen.next()) {
Addr paddr;
if (!pTable->translate(gen.addr(), paddr)) {
if (allocating == Always) {
process->allocateMem(roundDown(gen.addr(), VMPageSize),
VMPageSize);
process->allocateMem(roundDown(gen.addr(), PageBytes),
PageBytes);
pTable->translate(gen.addr(), paddr);
} else {
return false;

4
src/sim/process.cc
View file

@ -334,7 +334,7 @@ Process::sim_fd_obj(int tgt_fd)
void
Process::allocateMem(Addr vaddr, int64_t size, bool clobber)
{
int npages = divCeil(size, (int64_t)VMPageSize);
int npages = divCeil(size, (int64_t)PageBytes);
Addr paddr = system->allocPhysPages(npages);
pTable->map(vaddr, paddr, size, clobber);
}
@ -345,7 +345,7 @@ Process::fixupStackFault(Addr vaddr)
// Check if this is already on the stack and there's just no page there
// yet.
if (vaddr >= stack_min && vaddr < stack_base) {
allocateMem(roundDown(vaddr, VMPageSize), VMPageSize);
allocateMem(roundDown(vaddr, PageBytes), PageBytes);
return true;
}

12
src/sim/syscall_emul.cc
View file

@ -148,7 +148,7 @@ exitGroupFunc(SyscallDesc *desc, int callnum, LiveProcess *process,
SyscallReturn
getpagesizeFunc(SyscallDesc *desc, int num, LiveProcess *p, ThreadContext *tc)
{
return (int)VMPageSize;
return (int)PageBytes;
}
@ -167,9 +167,9 @@ brkFunc(SyscallDesc *desc, int num, LiveProcess *p, ThreadContext *tc)
if (new_brk > p->brk_point) {
// might need to allocate some new pages
for (ChunkGenerator gen(p->brk_point, new_brk - p->brk_point,
VMPageSize); !gen.done(); gen.next()) {
PageBytes); !gen.done(); gen.next()) {
if (!p->pTable->translate(gen.addr()))
p->allocateMem(roundDown(gen.addr(), VMPageSize), VMPageSize);
p->allocateMem(roundDown(gen.addr(), PageBytes), PageBytes);
// if the address is already there, zero it out
else {
@ -177,14 +177,14 @@ brkFunc(SyscallDesc *desc, int num, LiveProcess *p, ThreadContext *tc)
SETranslatingPortProxy &tp = tc->getMemProxy();
// split non-page aligned accesses
Addr next_page = roundUp(gen.addr(), VMPageSize);
Addr next_page = roundUp(gen.addr(), PageBytes);
uint32_t size_needed = next_page - gen.addr();
tp.memsetBlob(gen.addr(), zero, size_needed);
if (gen.addr() + VMPageSize > next_page &&
if (gen.addr() + PageBytes > next_page &&
next_page < new_brk &&
p->pTable->translate(next_page))
{
size_needed = VMPageSize - size_needed;
size_needed = PageBytes - size_needed;
tp.memsetBlob(next_page, zero, size_needed);
}
}

10
src/sim/syscall_emul.hh
View file

@ -822,9 +822,9 @@ mremapFunc(SyscallDesc *desc, int callnum, LiveProcess *process, ThreadContext *
if (use_provided_address)
provided_address = process->getSyscallArg(tc, index);
if ((start % TheISA::VMPageSize != 0) ||
(new_length % TheISA::VMPageSize != 0) ||
(provided_address % TheISA::VMPageSize != 0)) {
if ((start % TheISA::PageBytes != 0) ||
(new_length % TheISA::PageBytes != 0) ||
(provided_address % TheISA::PageBytes != 0)) {
warn("mremap failing: arguments not page aligned");
return -EINVAL;
}
@ -1226,8 +1226,8 @@ mmapFunc(SyscallDesc *desc, int num, LiveProcess *p, ThreadContext *tc)
}
}
if ((start % TheISA::VMPageSize) != 0 ||
(length % TheISA::VMPageSize) != 0) {
if ((start % TheISA::PageBytes) != 0 ||
(length % TheISA::PageBytes) != 0) {
warn("mmap failing: arguments not page-aligned: "
"start 0x%x length 0x%x",
start, length);

6
src/sim/system.cc
View file

@ -317,9 +317,9 @@ System::replaceThreadContext(ThreadContext *tc, int context_id)
Addr
System::allocPhysPages(int npages)
{
Addr return_addr = pagePtr << LogVMPageSize;
Addr return_addr = pagePtr << PageShift;
pagePtr += npages;
if ((pagePtr << LogVMPageSize) > physmem.totalSize())
if ((pagePtr << PageShift) > physmem.totalSize())
fatal("Out of memory, please increase size of physical memory.");
return return_addr;
}
@ -333,7 +333,7 @@ System::memSize() const
Addr
System::freeMemSize() const
{
return physmem.totalSize() - (pagePtr << LogVMPageSize);
return physmem.totalSize() - (pagePtr << PageShift);
}
bool