diff --git a/src/arch/alpha/decoder.hh b/src/arch/alpha/decoder.hh
index ef2f5856c..45e737e52 100644
--- a/src/arch/alpha/decoder.hh
+++ b/src/arch/alpha/decoder.hh
@@ -36,36 +36,20 @@
 #include "cpu/static_inst.hh"
 #include "sim/full_system.hh"
 
-class ThreadContext;
-
 namespace AlphaISA
 {
 
 class Decoder
 {
   protected:
-    ThreadContext *tc;
-
     // The extended machine instruction being generated
     ExtMachInst ext_inst;
     bool instDone;
 
   public:
-    Decoder(ThreadContext * _tc) : tc(_tc), instDone(false)
+    Decoder() : instDone(false)
     {}
 
-    ThreadContext *
-    getTC()
-    {
-        return tc;
-    }
-
-    void
-    setTC(ThreadContext * _tc)
-    {
-        tc = _tc;
-    }
-
     void
     process()
     { }
diff --git a/src/arch/arm/decoder.cc b/src/arch/arm/decoder.cc
index b5a73d68b..e957ce0e7 100644
--- a/src/arch/arm/decoder.cc
+++ b/src/arch/arm/decoder.cc
@@ -32,7 +32,6 @@
 #include "arch/arm/isa_traits.hh"
 #include "arch/arm/utility.hh"
 #include "base/trace.hh"
-#include "cpu/thread_context.hh"
 #include "debug/Decoder.hh"
 
 namespace ArmISA
diff --git a/src/arch/arm/decoder.hh b/src/arch/arm/decoder.hh
index 9099e3e2e..83a16da4c 100644
--- a/src/arch/arm/decoder.hh
+++ b/src/arch/arm/decoder.hh
@@ -39,15 +39,12 @@
 #include "base/types.hh"
 #include "cpu/static_inst.hh"
 
-class ThreadContext;
-
 namespace ArmISA
 {
 
 class Decoder
 {
   protected:
-    ThreadContext * tc;
     //The extended machine instruction being generated
     ExtMachInst emi;
     MachInst data;
@@ -72,23 +69,11 @@ class Decoder
         foundIt = false;
     }
 
-    Decoder(ThreadContext * _tc) : tc(_tc), data(0),
-        fpscrLen(0), fpscrStride(0)
+    Decoder() : data(0), fpscrLen(0), fpscrStride(0)
     {
         reset();
     }
 
-    ThreadContext * getTC()
-    {
-        return tc;
-    }
-
-    void
-    setTC(ThreadContext * _tc)
-    {
-        tc = _tc;
-    }
-
     void process();
 
     //Use this to give data to the decoder. This should be used
diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc
index 0df50a85e..ee2799147 100644
--- a/src/arch/arm/isa.cc
+++ b/src/arch/arm/isa.cc
@@ -381,7 +381,7 @@ ISA::setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc)
                 fpscrMask.n = ones;
                 newVal = (newVal & (uint32_t)fpscrMask) |
                          (miscRegs[MISCREG_FPSCR] & ~(uint32_t)fpscrMask);
-                tc->getDecodePtr()->setContext(newVal);
+                tc->getDecoderPtr()->setContext(newVal);
             }
             break;
           case MISCREG_CPSR_Q:
diff --git a/src/arch/mips/decoder.hh b/src/arch/mips/decoder.hh
index 4857eb353..080614dee 100644
--- a/src/arch/mips/decoder.hh
+++ b/src/arch/mips/decoder.hh
@@ -37,34 +37,20 @@
 #include "base/types.hh"
 #include "cpu/static_inst.hh"
 
-class ThreadContext;
-
 namespace MipsISA
 {
 
 class Decoder
 {
   protected:
-    ThreadContext * tc;
     //The extended machine instruction being generated
     ExtMachInst emi;
     bool instDone;
 
   public:
-    Decoder(ThreadContext * _tc) : tc(_tc), instDone(false)
+    Decoder() : instDone(false)
     {}
 
-    ThreadContext *getTC()
-    {
-        return tc;
-    }
-
-    void
-    setTC(ThreadContext *_tc)
-    {
-        tc = _tc;
-    }
-
     void
     process()
     {
diff --git a/src/arch/power/decoder.hh b/src/arch/power/decoder.hh
index 60fc8ca75..830636aed 100644
--- a/src/arch/power/decoder.hh
+++ b/src/arch/power/decoder.hh
@@ -35,37 +35,21 @@
 #include "arch/types.hh"
 #include "cpu/static_inst.hh"
 
-class ThreadContext;
-
 namespace PowerISA
 {
 
 class Decoder
 {
   protected:
-    ThreadContext * tc;
-
     // The extended machine instruction being generated
     ExtMachInst emi;
     bool instDone;
 
   public:
-    Decoder(ThreadContext * _tc) : tc(_tc), instDone(false)
+    Decoder() : instDone(false)
     {
     }
 
-    ThreadContext *
-    getTC()
-    {
-        return tc;
-    }
-
-    void
-    setTC(ThreadContext * _tc)
-    {
-        tc = _tc;
-    }
-
     void
     process()
     {
diff --git a/src/arch/sparc/decoder.hh b/src/arch/sparc/decoder.hh
index f85d5e4de..e7a806d81 100644
--- a/src/arch/sparc/decoder.hh
+++ b/src/arch/sparc/decoder.hh
@@ -35,9 +35,6 @@
 #include "arch/sparc/registers.hh"
 #include "arch/types.hh"
 #include "cpu/static_inst.hh"
-#include "cpu/thread_context.hh"
-
-class ThreadContext;
 
 namespace SparcISA
 {
@@ -45,28 +42,15 @@ namespace SparcISA
 class Decoder
 {
   protected:
-    ThreadContext * tc;
     // The extended machine instruction being generated
     ExtMachInst emi;
     bool instDone;
     MiscReg asi;
 
   public:
-    Decoder(ThreadContext * _tc) : tc(_tc), instDone(false), asi(0)
+    Decoder() : instDone(false), asi(0)
     {}
 
-    ThreadContext *
-    getTC()
-    {
-        return tc;
-    }
-
-    void
-    setTC(ThreadContext * _tc)
-    {
-        tc = _tc;
-    }
-
     void process() {}
 
     void
diff --git a/src/arch/sparc/isa.cc b/src/arch/sparc/isa.cc
index 4cfb93b0d..b8b4e88cc 100644
--- a/src/arch/sparc/isa.cc
+++ b/src/arch/sparc/isa.cc
@@ -29,6 +29,7 @@
  */
 
 #include "arch/sparc/asi.hh"
+#include "arch/sparc/decoder.hh"
 #include "arch/sparc/isa.hh"
 #include "base/bitfield.hh"
 #include "base/trace.hh"
@@ -550,7 +551,7 @@ ISA::setMiscReg(int miscReg, MiscReg val, ThreadContext * tc)
 
     switch (miscReg) {
       case MISCREG_ASI:
-        tc->getDecodePtr()->setContext(val);
+        tc->getDecoderPtr()->setContext(val);
         break;
       case MISCREG_STICK:
       case MISCREG_TICK:
diff --git a/src/arch/x86/decoder.cc b/src/arch/x86/decoder.cc
index 9dcb02902..f42fb28bf 100644
--- a/src/arch/x86/decoder.cc
+++ b/src/arch/x86/decoder.cc
@@ -33,7 +33,6 @@
 #include "base/misc.hh"
 #include "base/trace.hh"
 #include "base/types.hh"
-#include "cpu/thread_context.hh"
 #include "debug/Decoder.hh"
 
 namespace X86ISA
diff --git a/src/arch/x86/decoder.hh b/src/arch/x86/decoder.hh
index 796f9eef9..6f55ab26f 100644
--- a/src/arch/x86/decoder.hh
+++ b/src/arch/x86/decoder.hh
@@ -44,8 +44,6 @@
 #include "cpu/static_inst.hh"
 #include "debug/Decoder.hh"
 
-class ThreadContext;
-
 namespace X86ISA
 {
 
@@ -72,7 +70,6 @@ class Decoder
 
     static InstBytes dummy;
 
-    ThreadContext * tc;
     //The bytes to be predecoded
     MachInst fetchChunk;
     InstBytes *instBytes;
@@ -205,8 +202,7 @@ class Decoder
     static InstCacheMap instCacheMap;
 
   public:
-    Decoder(ThreadContext * _tc) :
-        tc(_tc), basePC(0), origPC(0), offset(0),
+    Decoder() : basePC(0), origPC(0), offset(0),
         outOfBytes(true), instDone(false),
         state(ResetState)
     {
@@ -259,16 +255,6 @@ class Decoder
         state = ResetState;
     }
 
-    ThreadContext * getTC()
-    {
-        return tc;
-    }
-
-    void setTC(ThreadContext * _tc)
-    {
-        tc = _tc;
-    }
-
     void process();
 
     //Use this to give data to the decoder. This should be used
diff --git a/src/cpu/checker/cpu_impl.hh b/src/cpu/checker/cpu_impl.hh
index 40f1cef6a..5637eb08b 100644
--- a/src/cpu/checker/cpu_impl.hh
+++ b/src/cpu/checker/cpu_impl.hh
@@ -306,7 +306,6 @@ Checker<Impl>::verify(DynInstPtr &completed_inst)
                     StaticInstPtr instPtr = NULL;
 
                     //Predecode, ie bundle up an ExtMachInst
-                    thread->decoder.setTC(thread->getTC());
                     //If more fetch data is needed, pass it in.
                     Addr fetchPC = (pcState.instAddr() & PCMask) + fetchOffset;
                     thread->decoder.moreBytes(pcState, fetchPC, machInst);
diff --git a/src/cpu/inorder/resources/fetch_unit.cc b/src/cpu/inorder/resources/fetch_unit.cc
index 0ed59fe2d..49bd0434b 100644
--- a/src/cpu/inorder/resources/fetch_unit.cc
+++ b/src/cpu/inorder/resources/fetch_unit.cc
@@ -59,7 +59,7 @@ FetchUnit::FetchUnit(string res_name, int res_id, int res_width,
       instSize(sizeof(TheISA::MachInst)), fetchBuffSize(params->fetchBuffSize)
 {
     for (int tid = 0; tid < MaxThreads; tid++)
-        decoder[tid] = new Decoder(NULL);
+        decoder[tid] = new Decoder;
 }
 
 FetchUnit::~FetchUnit()
@@ -109,7 +109,6 @@ FetchUnit::createMachInst(std::list<FetchBlock*>::iterator fetch_it,
     MachInst mach_inst =
         TheISA::gtoh(fetchInsts[fetch_offset]);
 
-    decoder[tid]->setTC(cpu->thread[tid]->getTC());
     decoder[tid]->moreBytes(instPC, inst->instAddr(), mach_inst);
     assert(decoder[tid]->instReady());
     inst->setStaticInst(decoder[tid]->decode(instPC));
diff --git a/src/cpu/legiontrace.cc b/src/cpu/legiontrace.cc
index f3ac5e702..b94b8f5fe 100644
--- a/src/cpu/legiontrace.cc
+++ b/src/cpu/legiontrace.cc
@@ -422,7 +422,6 @@ Trace::LegionTraceRecord::dump()
                          << endl;
 
                     TheISA::Decoder *decoder = thread->getDecoderPtr();
-                    decoder->setTC(thread);
                     decoder->moreBytes(m5Pc, m5Pc, shared_data->instruction);
 
                     assert(decoder->instReady());
diff --git a/src/cpu/o3/fetch_impl.hh b/src/cpu/o3/fetch_impl.hh
index 33563f539..9efe30309 100644
--- a/src/cpu/o3/fetch_impl.hh
+++ b/src/cpu/o3/fetch_impl.hh
@@ -134,7 +134,7 @@ DefaultFetch<Impl>::DefaultFetch(O3CPU *_cpu, DerivO3CPUParams *params)
 
     for (int i = 0; i < Impl::MaxThreads; i++) {
         cacheData[i] = NULL;
-        decoder[i] = new TheISA::Decoder(NULL);
+        decoder[i] = new TheISA::Decoder;
     }
 }
 
@@ -1225,9 +1225,8 @@ DefaultFetch<Impl>::fetch(bool &status_change)
                 if (blkOffset >= numInsts)
                     break;
             }
-            MachInst inst = TheISA::gtoh(cacheInsts[blkOffset]);
 
-            decoder[tid]->setTC(cpu->thread[tid]->getTC());
+            MachInst inst = TheISA::gtoh(cacheInsts[blkOffset]);
             decoder[tid]->moreBytes(thisPC, fetchAddr, inst);
 
             if (decoder[tid]->needMoreBytes()) {
diff --git a/src/cpu/simple/base.cc b/src/cpu/simple/base.cc
index 5a9499333..9ca943900 100644
--- a/src/cpu/simple/base.cc
+++ b/src/cpu/simple/base.cc
@@ -380,8 +380,6 @@ BaseSimpleCPU::preExecute()
         TheISA::Decoder *decoder = &(thread->decoder);
 
         //Predecode, ie bundle up an ExtMachInst
-        //This should go away once the constructor can be set up properly
-        decoder->setTC(thread->getTC());
         //If more fetch data is needed, pass it in.
         Addr fetchPC = (pcState.instAddr() & PCMask) + fetchOffset;
         //if(decoder->needMoreBytes())
diff --git a/src/cpu/simple_thread.cc b/src/cpu/simple_thread.cc
index f887e7e48..cf9bb4840 100644
--- a/src/cpu/simple_thread.cc
+++ b/src/cpu/simple_thread.cc
@@ -63,16 +63,16 @@ SimpleThread::SimpleThread(BaseCPU *_cpu, int _thread_num, System *_sys,
                            Process *_process, TheISA::TLB *_itb,
                            TheISA::TLB *_dtb)
     : ThreadState(_cpu, _thread_num, _process), system(_sys), itb(_itb),
-      dtb(_dtb), decoder(NULL)
+      dtb(_dtb)
 {
     clearArchRegs();
     tc = new ProxyThreadContext<SimpleThread>(this);
 }
+
 SimpleThread::SimpleThread(BaseCPU *_cpu, int _thread_num, System *_sys,
                            TheISA::TLB *_itb, TheISA::TLB *_dtb,
                            bool use_kernel_stats)
-    : ThreadState(_cpu, _thread_num, NULL), system(_sys), itb(_itb), dtb(_dtb),
-      decoder(NULL)
+    : ThreadState(_cpu, _thread_num, NULL), system(_sys), itb(_itb), dtb(_dtb)
 {
     tc = new ProxyThreadContext<SimpleThread>(this);
 
@@ -99,7 +99,7 @@ SimpleThread::SimpleThread(BaseCPU *_cpu, int _thread_num, System *_sys,
 }
 
 SimpleThread::SimpleThread()
-    : ThreadState(NULL, -1, NULL), decoder(NULL)
+    : ThreadState(NULL, -1, NULL)
 {
     tc = new ProxyThreadContext<SimpleThread>(this);
 }